1/* SPDX-License-Identifier: Apache-2.0 */ 2 3#include <arm/armv7-m.dtsi> 4#include "nrf_common.dtsi" 5 6/ { 7 chosen { 8 zephyr,entropy = &rng; 9 zephyr,flash-controller = &flash_controller; 10 }; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "arm,cortex-m4"; 19 reg = <0>; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 23 itm: itm@e0000000 { 24 compatible = "arm,armv7m-itm"; 25 reg = <0xe0000000 0x1000>; 26 swo-ref-frequency = <32000000>; 27 }; 28 }; 29 }; 30 31 soc { 32 ficr: ficr@10000000 { 33 compatible = "nordic,nrf-ficr"; 34 reg = <0x10000000 0x1000>; 35 status = "okay"; 36 }; 37 38 uicr: uicr@10001000 { 39 compatible = "nordic,nrf-uicr"; 40 reg = <0x10001000 0x1000>; 41 status = "okay"; 42 }; 43 44 sram0: memory@20000000 { 45 compatible = "mmio-sram"; 46 }; 47 48 clock: clock@40000000 { 49 compatible = "nordic,nrf-clock"; 50 reg = <0x40000000 0x1000>; 51 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>; 52 status = "okay"; 53 }; 54 55 power: power@40000000 { 56 compatible = "nordic,nrf-power"; 57 reg = <0x40000000 0x1000>; 58 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>; 59 status = "okay"; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 63 gpregret1: gpregret1@4000051c { 64 #address-cells = <1>; 65 #size-cells = <1>; 66 compatible = "nordic,nrf-gpregret"; 67 reg = <0x4000051c 0x1>; 68 status = "okay"; 69 }; 70 71 gpregret2: gpregret2@40000520 { 72 #address-cells = <1>; 73 #size-cells = <1>; 74 compatible = "nordic,nrf-gpregret"; 75 reg = <0x40000520 0x1>; 76 status = "okay"; 77 }; 78 }; 79 80 bprot: bprot@40000000 { 81 compatible = "nordic,nrf-bprot"; 82 reg = <0x40000000 0x1000>; 83 status = "okay"; 84 }; 85 86 radio: radio@40001000 { 87 compatible = "nordic,nrf-radio"; 88 reg = <0x40001000 0x1000>; 89 interrupts = <1 NRF_DEFAULT_IRQ_PRIORITY>; 90 status = "okay"; 91 ble-2mbps-supported; 92 }; 93 94 uart0: uart@40002000 { 95 /* uart can be either UART or UARTE, for the user to pick */ 96 /* compatible = "nordic,nrf-uarte" or "nordic,nrf-uart"; */ 97 compatible = "nordic,nrf-uarte"; 98 reg = <0x40002000 0x1000>; 99 interrupts = <2 NRF_DEFAULT_IRQ_PRIORITY>; 100 status = "disabled"; 101 }; 102 103 i2c0: i2c@40003000 { 104 /* 105 * This i2c node can be TWI, TWIM, or TWIS, 106 * for the user to pick: 107 * compatible = "nordic,nrf-twi" or 108 * "nordic,nrf-twim" or 109 * "nordic,nrf-twis". 110 */ 111 compatible = "nordic,nrf-twim"; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 reg = <0x40003000 0x1000>; 115 clock-frequency = <I2C_BITRATE_STANDARD>; 116 interrupts = <3 NRF_DEFAULT_IRQ_PRIORITY>; 117 easydma-maxcnt-bits = <10>; 118 status = "disabled"; 119 }; 120 121 spi0: spi@40004000 { 122 /* 123 * This spi node can be SPI, SPIM, or SPIS, 124 * for the user to pick: 125 * compatible = "nordic,nrf-spi" or 126 * "nordic,nrf-spim" or 127 * "nordic,nrf-spis". 128 */ 129 compatible = "nordic,nrf-spim"; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 reg = <0x40004000 0x1000>; 133 interrupts = <4 NRF_DEFAULT_IRQ_PRIORITY>; 134 max-frequency = <DT_FREQ_M(8)>; 135 easydma-maxcnt-bits = <10>; 136 status = "disabled"; 137 }; 138 139 gpiote: gpiote@40006000 { 140 compatible = "nordic,nrf-gpiote"; 141 reg = <0x40006000 0x1000>; 142 interrupts = <6 5>; 143 status = "disabled"; 144 }; 145 146 adc: adc@40007000 { 147 compatible = "nordic,nrf-saadc"; 148 reg = <0x40007000 0x1000>; 149 interrupts = <7 NRF_DEFAULT_IRQ_PRIORITY>; 150 status = "disabled"; 151 #io-channel-cells = <1>; 152 }; 153 timer0: timer@40008000 { 154 compatible = "nordic,nrf-timer"; 155 status = "disabled"; 156 reg = <0x40008000 0x1000>; 157 cc-num = <4>; 158 max-bit-width = <32>; 159 interrupts = <8 NRF_DEFAULT_IRQ_PRIORITY>; 160 prescaler = <0>; 161 }; 162 163 timer1: timer@40009000 { 164 compatible = "nordic,nrf-timer"; 165 status = "disabled"; 166 reg = <0x40009000 0x1000>; 167 cc-num = <4>; 168 max-bit-width = <32>; 169 interrupts = <9 NRF_DEFAULT_IRQ_PRIORITY>; 170 prescaler = <0>; 171 }; 172 173 timer2: timer@4000a000 { 174 compatible = "nordic,nrf-timer"; 175 status = "disabled"; 176 reg = <0x4000a000 0x1000>; 177 cc-num = <4>; 178 max-bit-width = <32>; 179 interrupts = <10 NRF_DEFAULT_IRQ_PRIORITY>; 180 prescaler = <0>; 181 }; 182 183 rtc0: rtc@4000b000 { 184 compatible = "nordic,nrf-rtc"; 185 reg = <0x4000b000 0x1000>; 186 cc-num = <3>; 187 interrupts = <11 NRF_DEFAULT_IRQ_PRIORITY>; 188 status = "disabled"; 189 clock-frequency = <32768>; 190 prescaler = <1>; 191 }; 192 193 temp: temp@4000c000 { 194 compatible = "nordic,nrf-temp"; 195 reg = <0x4000c000 0x1000>; 196 interrupts = <12 NRF_DEFAULT_IRQ_PRIORITY>; 197 status = "okay"; 198 }; 199 200 rng: random@4000d000 { 201 compatible = "nordic,nrf-rng"; 202 reg = <0x4000d000 0x1000>; 203 interrupts = <13 NRF_DEFAULT_IRQ_PRIORITY>; 204 status = "okay"; 205 }; 206 207 ecb: ecb@4000e000 { 208 compatible = "nordic,nrf-ecb"; 209 reg = <0x4000e000 0x1000>; 210 interrupts = <14 NRF_DEFAULT_IRQ_PRIORITY>; 211 status = "okay"; 212 }; 213 214 ccm: ccm@4000f000 { 215 compatible = "nordic,nrf-ccm"; 216 reg = <0x4000f000 0x1000>; 217 interrupts = <15 NRF_DEFAULT_IRQ_PRIORITY>; 218 length-field-length-8-bits; 219 status = "okay"; 220 }; 221 222 wdt: wdt0: watchdog@40010000 { 223 compatible = "nordic,nrf-wdt"; 224 reg = <0x40010000 0x1000>; 225 interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>; 226 status = "okay"; 227 }; 228 229 rtc1: rtc@40011000 { 230 compatible = "nordic,nrf-rtc"; 231 reg = <0x40011000 0x1000>; 232 cc-num = <4>; 233 interrupts = <17 NRF_DEFAULT_IRQ_PRIORITY>; 234 status = "disabled"; 235 clock-frequency = <32768>; 236 prescaler = <1>; 237 }; 238 239 qdec: qdec0: qdec@40012000 { 240 compatible = "nordic,nrf-qdec"; 241 reg = <0x40012000 0x1000>; 242 interrupts = <18 NRF_DEFAULT_IRQ_PRIORITY>; 243 status = "disabled"; 244 }; 245 246 comp: comparator@40013000 { 247 compatible = "nordic,nrf-comp"; 248 reg = <0x40013000 0x1000>; 249 interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>; 250 status = "disabled"; 251 #io-channel-cells = <1>; 252 }; 253 254 egu0: swi0: egu@40014000 { 255 compatible = "nordic,nrf-egu", "nordic,nrf-swi"; 256 reg = <0x40014000 0x1000>; 257 interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; 258 status = "okay"; 259 }; 260 261 egu1: swi1: egu@40015000 { 262 compatible = "nordic,nrf-egu", "nordic,nrf-swi"; 263 reg = <0x40015000 0x1000>; 264 interrupts = <21 NRF_DEFAULT_IRQ_PRIORITY>; 265 status = "okay"; 266 }; 267 268 swi2: swi@40016000 { 269 compatible = "nordic,nrf-swi"; 270 reg = <0x40016000 0x1000>; 271 interrupts = <22 NRF_DEFAULT_IRQ_PRIORITY>; 272 status = "okay"; 273 }; 274 275 swi3: swi@40017000 { 276 compatible = "nordic,nrf-swi"; 277 reg = <0x40017000 0x1000>; 278 interrupts = <23 NRF_DEFAULT_IRQ_PRIORITY>; 279 status = "okay"; 280 }; 281 282 swi4: swi@40018000 { 283 compatible = "nordic,nrf-swi"; 284 reg = <0x40018000 0x1000>; 285 interrupts = <24 NRF_DEFAULT_IRQ_PRIORITY>; 286 status = "okay"; 287 }; 288 289 swi5: swi@40019000 { 290 compatible = "nordic,nrf-swi"; 291 reg = <0x40019000 0x1000>; 292 interrupts = <25 NRF_DEFAULT_IRQ_PRIORITY>; 293 status = "okay"; 294 }; 295 296 pwm0: pwm@4001c000 { 297 compatible = "nordic,nrf-pwm"; 298 reg = <0x4001c000 0x1000>; 299 interrupts = <28 NRF_DEFAULT_IRQ_PRIORITY>; 300 status = "disabled"; 301 #pwm-cells = <3>; 302 }; 303 304 pdm0: pdm@4001d000 { 305 compatible = "nordic,nrf-pdm"; 306 reg = <0x4001d000 0x1000>; 307 interrupts = <29 NRF_DEFAULT_IRQ_PRIORITY>; 308 status = "disabled"; 309 }; 310 311 flash_controller: flash-controller@4001e000 { 312 compatible = "nordic,nrf52-flash-controller"; 313 reg = <0x4001e000 0x1000>; 314 partial-erase; 315 316 #address-cells = <1>; 317 #size-cells = <1>; 318 319 320 flash0: flash@0 { 321 compatible = "soc-nv-flash"; 322 erase-block-size = <4096>; 323 write-block-size = <4>; 324 }; 325 }; 326 327 ppi: ppi@4001f000 { 328 compatible = "nordic,nrf-ppi"; 329 reg = <0x4001f000 0x1000>; 330 status = "okay"; 331 }; 332 333 gpio0: gpio@50000000 { 334 compatible = "nordic,nrf-gpio"; 335 gpio-controller; 336 reg = <0x50000000 0x1000>; 337 #gpio-cells = <2>; 338 status = "disabled"; 339 port = <0>; 340 }; 341 }; 342}; 343 344&nvic { 345 arm,num-irq-priority-bits = <3>; 346}; 347