1 /* 2 * xtensa/config/core-isa.h -- minimum required HAL definitions that are 3 * dependent on Xtensa processor CORE configuration 4 * 5 * See <xtensa/config/core.h>, which includes this file, for more details. 6 */ 7 8 /* Xtensa processor core configuration information. 9 10 Copyright (c) 1999-2023 Tensilica Inc. 11 12 Permission is hereby granted, free of charge, to any person obtaining 13 a copy of this software and associated documentation files (the 14 "Software"), to deal in the Software without restriction, including 15 without limitation the rights to use, copy, modify, merge, publish, 16 distribute, sublicense, and/or sell copies of the Software, and to 17 permit persons to whom the Software is furnished to do so, subject to 18 the following conditions: 19 20 The above copyright notice and this permission notice shall be included 21 in all copies or substantial portions of the Software. 22 23 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 26 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 27 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 30 31 #ifndef _XTENSA_CORE_CONFIGURATION_H 32 #define _XTENSA_CORE_CONFIGURATION_H 33 34 #if defined(_LIBC) || defined(_LIBM) || defined(_LIBGLOSS) 35 36 /* Macros used to build newlib and libgloss */ 37 38 #undef XCHAL_HAVE_BE 39 #ifdef __XCHAL_HAVE_BE 40 #define XCHAL_HAVE_BE __XCHAL_HAVE_BE 41 #else 42 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 43 #endif 44 45 #undef XCHAL_HAVE_WINDOWED 46 #ifdef __XCHAL_HAVE_WINDOWED 47 #define XCHAL_HAVE_WINDOWED __XCHAL_HAVE_WINDOWED 48 #else 49 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 50 #endif 51 52 #undef XCHAL_NUM_AREGS 53 #ifdef __XCHAL_NUM_AREGS 54 #define XCHAL_NUM_AREGS __XCHAL_NUM_AREGS 55 #else 56 #define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ 57 #endif 58 59 #undef XCHAL_HAVE_DENSITY 60 #ifdef __XCHAL_HAVE_DENSITY 61 #define XCHAL_HAVE_DENSITY __XCHAL_HAVE_DENSITY 62 #else 63 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 64 #endif 65 66 #undef XCHAL_HAVE_LOOPS 67 #ifdef __XCHAL_HAVE_LOOPS 68 #define XCHAL_HAVE_LOOPS __XCHAL_HAVE_LOOPS 69 #else 70 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 71 #endif 72 73 #undef XCHAL_HAVE_L32R 74 #ifdef __XCHAL_HAVE_L32R 75 #define XCHAL_HAVE_L32R __XCHAL_HAVE_L32R 76 #else 77 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 78 #endif 79 80 #undef XCHAL_HAVE_FP 81 #ifdef __XCHAL_HAVE_FP 82 #define XCHAL_HAVE_FP __XCHAL_HAVE_FP 83 #else 84 #define XCHAL_HAVE_FP 1 /* single prec floating point */ 85 #endif 86 87 #undef XCHAL_HAVE_FP_SQRT 88 #ifdef __XCHAL_HAVE_FP_SQRT 89 #define XCHAL_HAVE_FP_SQRT __XCHAL_HAVE_FP_SQRT 90 #else 91 #define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ 92 #endif 93 94 #undef XCHAL_HAVE_DFP 95 #ifdef __XCHAL_HAVE_DFP 96 #define XCHAL_HAVE_DFP __XCHAL_HAVE_DFP 97 #else 98 #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 99 #endif 100 101 #undef XCHAL_INST_FETCH_WIDTH 102 #ifdef __XCHAL_INST_FETCH_WIDTH 103 #define XCHAL_INST_FETCH_WIDTH __XCHAL_INST_FETCH_WIDTH 104 #else 105 #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 106 #endif 107 108 #else /* defined(_LIBC) || defined(_LIBM) || defined(_LIBGLOSS) */ 109 110 /* Expect that core-isa.h exists in OS/baremetal port */ 111 #include_next <xtensa/config/core-isa.h> 112 113 #endif /* defined(_LIBC) || defined(_LIBM) || defined(_LIBGLOSS) */ 114 115 #endif /* _XTENSA_CORE_CONFIGURATION_H */ 116
