1 /* Copyright (c) 2017 SiFive Inc. All rights reserved. 2 3 This copyrighted material is made available to anyone wishing to use, 4 modify, copy, or redistribute it subject to the terms and conditions 5 of the FreeBSD License. This program is distributed in the hope that 6 it will be useful, but WITHOUT ANY WARRANTY expressed or implied, 7 including the implied warranties of MERCHANTABILITY or FITNESS FOR 8 A PARTICULAR PURPOSE. A copy of this license is available at 9 http://www.opensource.org/licenses. 10 */ 11 12 #ifndef _SYS_FENV_H 13 #define _SYS_FENV_H 14 15 #include <stddef.h> 16 17 #if __riscv_flen 18 19 /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA: 20 * Version 2.1", Section 8.2, "Floating-Point Control and Status 21 * Register": 22 * 23 * Flag Mnemonic Flag Meaning 24 * ------------- ----------------- 25 * NV Invalid Operation 26 * DZ Divide by Zero 27 * OF Overflow 28 * UF Underflow 29 * NX Inexact 30 */ 31 32 #define FE_INVALID 0x00000010 33 #define FE_DIVBYZERO 0x00000008 34 #define FE_OVERFLOW 0x00000004 35 #define FE_UNDERFLOW 0x00000002 36 #define FE_INEXACT 0x00000001 37 38 #define FE_ALL_EXCEPT (FE_INVALID|FE_DIVBYZERO|FE_OVERFLOW|FE_UNDERFLOW|FE_INEXACT) 39 40 /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA: 41 * Version 2.1", Section 8.2, "Floating-Point Control and Status 42 * Register": 43 * 44 * Rounding Mode Mnemonic Meaning Meaning 45 * ------------- ---------------- ------- 46 * 000 RNE Round to Nearest, ties to Even 47 * 001 RTZ Round towards Zero 48 * 010 RDN Round Down (towards −∞) 49 * 011 RUP Round Up (towards +∞) 50 * 100 RMM Round to Nearest, ties to Max Magnitude 51 * 101 Invalid. Reserved for future use. 52 * 110 Invalid. Reserved for future use. 53 * 111 In instruction’s rm field, selects dynamic rounding mode; 54 * In Rounding Mode register, Invalid 55 */ 56 57 #define FE_TONEAREST_MM 0x00000004 58 #define FE_UPWARD 0x00000003 59 #define FE_DOWNWARD 0x00000002 60 #define FE_TOWARDZERO 0x00000001 61 #define FE_TONEAREST 0x00000000 62 63 #define FE_RMODE_MASK 0x7 64 #endif 65 66 /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA: 67 * Version 2.1": 68 * 69 * "The F extension adds 32 floating-point registers, f0–f31, each 32 70 * bits wide, and a floating-point control and status register fcsr, 71 * which contains the operating mode and exception status of the 72 * floating-point unit." 73 */ 74 75 typedef size_t fenv_t; 76 typedef size_t fexcept_t; 77 78 #endif /* _SYS_FENV_H */ 79
