1 /*
2  * Copyright (c) 2022, ARM Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef NEOVERSE_POSEIDON_H
8 #define NEOVERSE_POSEIDON_H
9 
10 
11 #define NEOVERSE_POSEIDON_MIDR                      		U(0x410FD830)
12 
13 /* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
14 #define NEOVERSE_POSEIDON_BHB_LOOP_COUNT			U(132)
15 
16 /*******************************************************************************
17  * CPU Extended Control register specific definitions.
18  ******************************************************************************/
19 #define NEOVERSE_POSEIDON_CPUECTLR_EL1				S3_0_C15_C1_4
20 
21 /*******************************************************************************
22  * CPU Power Control register specific definitions
23  ******************************************************************************/
24 #define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1			S3_0_C15_C2_7
25 #define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
26 
27 #endif /* NEOVERSE_POSEIDON_H */
28