1 /** 2 * @file nbbfc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the NBBFC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup nbbfc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_NBBFC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_NBBFC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup nbbfc 67 * @defgroup nbbfc_registers NBBFC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the NBBFC Peripheral Module. 69 * @details Non Battery-Backed Function Control Register. 70 */ 71 72 /** 73 * @ingroup nbbfc_registers 74 * Structure type to access the NBBFC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t reg0; /**< <tt>\b 0x00:</tt> NBBFC REG0 Register */ 78 __IO uint32_t reg1; /**< <tt>\b 0x04:</tt> NBBFC REG1 Register */ 79 __IO uint32_t reg2; /**< <tt>\b 0x08:</tt> NBBFC REG2 Register */ 80 __IO uint32_t reg3; /**< <tt>\b 0x0C:</tt> NBBFC REG3 Register */ 81 } mxc_nbbfc_regs_t; 82 83 /* Register offsets for module NBBFC */ 84 /** 85 * @ingroup nbbfc_registers 86 * @defgroup NBBFC_Register_Offsets Register Offsets 87 * @brief NBBFC Peripheral Register Offsets from the NBBFC Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_NBBFC_REG0 ((uint32_t)0x00000000UL) /**< Offset from NBBFC Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_NBBFC_REG1 ((uint32_t)0x00000004UL) /**< Offset from NBBFC Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_NBBFC_REG2 ((uint32_t)0x00000008UL) /**< Offset from NBBFC Base Address: <tt> 0x0008</tt> */ 93 #define MXC_R_NBBFC_REG3 ((uint32_t)0x0000000CUL) /**< Offset from NBBFC Base Address: <tt> 0x000C</tt> */ 94 /**@} end of group nbbfc_registers */ 95 96 /** 97 * @ingroup nbbfc_registers 98 * @defgroup NBBFC_REG0 NBBFC_REG0 99 * @brief Register 0. 100 * @{ 101 */ 102 #define MXC_F_NBBFC_REG0_RDSGCSEL_POS 0 /**< REG0_RDSGCSEL Position */ 103 #define MXC_F_NBBFC_REG0_RDSGCSEL ((uint32_t)(0x3FUL << MXC_F_NBBFC_REG0_RDSGCSEL_POS)) /**< REG0_RDSGCSEL Mask */ 104 105 #define MXC_F_NBBFC_REG0_RDSGCSET_POS 6 /**< REG0_RDSGCSET Position */ 106 #define MXC_F_NBBFC_REG0_RDSGCSET ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_RDSGCSET_POS)) /**< REG0_RDSGCSET Mask */ 107 #define MXC_V_NBBFC_REG0_RDSGCSET_INTERNAL ((uint32_t)0x0UL) /**< REG0_RDSGCSET_INTERNAL Value */ 108 #define MXC_S_NBBFC_REG0_RDSGCSET_INTERNAL (MXC_V_NBBFC_REG0_RDSGCSET_INTERNAL << MXC_F_NBBFC_REG0_RDSGCSET_POS) /**< REG0_RDSGCSET_INTERNAL Setting */ 109 #define MXC_V_NBBFC_REG0_RDSGCSET_GRAY_CODE ((uint32_t)0x1UL) /**< REG0_RDSGCSET_GRAY_CODE Value */ 110 #define MXC_S_NBBFC_REG0_RDSGCSET_GRAY_CODE (MXC_V_NBBFC_REG0_RDSGCSET_GRAY_CODE << MXC_F_NBBFC_REG0_RDSGCSET_POS) /**< REG0_RDSGCSET_GRAY_CODE Setting */ 111 112 #define MXC_F_NBBFC_REG0_HYPCGDLY_POS 8 /**< REG0_HYPCGDLY Position */ 113 #define MXC_F_NBBFC_REG0_HYPCGDLY ((uint32_t)(0x3FUL << MXC_F_NBBFC_REG0_HYPCGDLY_POS)) /**< REG0_HYPCGDLY Mask */ 114 115 #define MXC_F_NBBFC_REG0_USBRCKSEL_POS 16 /**< REG0_USBRCKSEL Position */ 116 #define MXC_F_NBBFC_REG0_USBRCKSEL ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_USBRCKSEL_POS)) /**< REG0_USBRCKSEL Mask */ 117 #define MXC_V_NBBFC_REG0_USBRCKSEL_SYS ((uint32_t)0x0UL) /**< REG0_USBRCKSEL_SYS Value */ 118 #define MXC_S_NBBFC_REG0_USBRCKSEL_SYS (MXC_V_NBBFC_REG0_USBRCKSEL_SYS << MXC_F_NBBFC_REG0_USBRCKSEL_POS) /**< REG0_USBRCKSEL_SYS Setting */ 119 #define MXC_V_NBBFC_REG0_USBRCKSEL_DIG ((uint32_t)0x1UL) /**< REG0_USBRCKSEL_DIG Value */ 120 #define MXC_S_NBBFC_REG0_USBRCKSEL_DIG (MXC_V_NBBFC_REG0_USBRCKSEL_DIG << MXC_F_NBBFC_REG0_USBRCKSEL_POS) /**< REG0_USBRCKSEL_DIG Setting */ 121 122 #define MXC_F_NBBFC_REG0_QSPI0SEL_POS 17 /**< REG0_QSPI0SEL Position */ 123 #define MXC_F_NBBFC_REG0_QSPI0SEL ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_QSPI0SEL_POS)) /**< REG0_QSPI0SEL Mask */ 124 #define MXC_V_NBBFC_REG0_QSPI0SEL_MED ((uint32_t)0x0UL) /**< REG0_QSPI0SEL_MED Value */ 125 #define MXC_S_NBBFC_REG0_QSPI0SEL_MED (MXC_V_NBBFC_REG0_QSPI0SEL_MED << MXC_F_NBBFC_REG0_QSPI0SEL_POS) /**< REG0_QSPI0SEL_MED Setting */ 126 #define MXC_V_NBBFC_REG0_QSPI0SEL_QSPI0 ((uint32_t)0x1UL) /**< REG0_QSPI0SEL_QSPI0 Value */ 127 #define MXC_S_NBBFC_REG0_QSPI0SEL_QSPI0 (MXC_V_NBBFC_REG0_QSPI0SEL_QSPI0 << MXC_F_NBBFC_REG0_QSPI0SEL_POS) /**< REG0_QSPI0SEL_QSPI0 Setting */ 128 129 #define MXC_F_NBBFC_REG0_I2C0DGEN0_POS 20 /**< REG0_I2C0DGEN0 Position */ 130 #define MXC_F_NBBFC_REG0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C0DGEN0_POS)) /**< REG0_I2C0DGEN0 Mask */ 131 #define MXC_V_NBBFC_REG0_I2C0DGEN0_DIS ((uint32_t)0x0UL) /**< REG0_I2C0DGEN0_DIS Value */ 132 #define MXC_S_NBBFC_REG0_I2C0DGEN0_DIS (MXC_V_NBBFC_REG0_I2C0DGEN0_DIS << MXC_F_NBBFC_REG0_I2C0DGEN0_POS) /**< REG0_I2C0DGEN0_DIS Setting */ 133 #define MXC_V_NBBFC_REG0_I2C0DGEN0_EN ((uint32_t)0x1UL) /**< REG0_I2C0DGEN0_EN Value */ 134 #define MXC_S_NBBFC_REG0_I2C0DGEN0_EN (MXC_V_NBBFC_REG0_I2C0DGEN0_EN << MXC_F_NBBFC_REG0_I2C0DGEN0_POS) /**< REG0_I2C0DGEN0_EN Setting */ 135 136 #define MXC_F_NBBFC_REG0_I2C0DGEN1_POS 21 /**< REG0_I2C0DGEN1 Position */ 137 #define MXC_F_NBBFC_REG0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C0DGEN1_POS)) /**< REG0_I2C0DGEN1 Mask */ 138 #define MXC_V_NBBFC_REG0_I2C0DGEN1_DIS ((uint32_t)0x0UL) /**< REG0_I2C0DGEN1_DIS Value */ 139 #define MXC_S_NBBFC_REG0_I2C0DGEN1_DIS (MXC_V_NBBFC_REG0_I2C0DGEN1_DIS << MXC_F_NBBFC_REG0_I2C0DGEN1_POS) /**< REG0_I2C0DGEN1_DIS Setting */ 140 #define MXC_V_NBBFC_REG0_I2C0DGEN1_EN ((uint32_t)0x1UL) /**< REG0_I2C0DGEN1_EN Value */ 141 #define MXC_S_NBBFC_REG0_I2C0DGEN1_EN (MXC_V_NBBFC_REG0_I2C0DGEN1_EN << MXC_F_NBBFC_REG0_I2C0DGEN1_POS) /**< REG0_I2C0DGEN1_EN Setting */ 142 143 #define MXC_F_NBBFC_REG0_I2C1DGEN0_POS 22 /**< REG0_I2C1DGEN0 Position */ 144 #define MXC_F_NBBFC_REG0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C1DGEN0_POS)) /**< REG0_I2C1DGEN0 Mask */ 145 #define MXC_V_NBBFC_REG0_I2C1DGEN0_DIS ((uint32_t)0x0UL) /**< REG0_I2C1DGEN0_DIS Value */ 146 #define MXC_S_NBBFC_REG0_I2C1DGEN0_DIS (MXC_V_NBBFC_REG0_I2C1DGEN0_DIS << MXC_F_NBBFC_REG0_I2C1DGEN0_POS) /**< REG0_I2C1DGEN0_DIS Setting */ 147 #define MXC_V_NBBFC_REG0_I2C1DGEN0_EN ((uint32_t)0x1UL) /**< REG0_I2C1DGEN0_EN Value */ 148 #define MXC_S_NBBFC_REG0_I2C1DGEN0_EN (MXC_V_NBBFC_REG0_I2C1DGEN0_EN << MXC_F_NBBFC_REG0_I2C1DGEN0_POS) /**< REG0_I2C1DGEN0_EN Setting */ 149 150 #define MXC_F_NBBFC_REG0_I2C1DGEN1_POS 23 /**< REG0_I2C1DGEN1 Position */ 151 #define MXC_F_NBBFC_REG0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C1DGEN1_POS)) /**< REG0_I2C1DGEN1 Mask */ 152 #define MXC_V_NBBFC_REG0_I2C1DGEN1_DIS ((uint32_t)0x0UL) /**< REG0_I2C1DGEN1_DIS Value */ 153 #define MXC_S_NBBFC_REG0_I2C1DGEN1_DIS (MXC_V_NBBFC_REG0_I2C1DGEN1_DIS << MXC_F_NBBFC_REG0_I2C1DGEN1_POS) /**< REG0_I2C1DGEN1_DIS Setting */ 154 #define MXC_V_NBBFC_REG0_I2C1DGEN1_EN ((uint32_t)0x1UL) /**< REG0_I2C1DGEN1_EN Value */ 155 #define MXC_S_NBBFC_REG0_I2C1DGEN1_EN (MXC_V_NBBFC_REG0_I2C1DGEN1_EN << MXC_F_NBBFC_REG0_I2C1DGEN1_POS) /**< REG0_I2C1DGEN1_EN Setting */ 156 157 /**@} end of group NBBFC_REG0_Register */ 158 159 /** 160 * @ingroup nbbfc_registers 161 * @defgroup NBBFC_REG1 NBBFC_REG1 162 * @brief Register 1. 163 * @{ 164 */ 165 #define MXC_F_NBBFC_REG1_ACEN_POS 0 /**< REG1_ACEN Position */ 166 #define MXC_F_NBBFC_REG1_ACEN ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_ACEN_POS)) /**< REG1_ACEN Mask */ 167 #define MXC_V_NBBFC_REG1_ACEN_DIS ((uint32_t)0x0UL) /**< REG1_ACEN_DIS Value */ 168 #define MXC_S_NBBFC_REG1_ACEN_DIS (MXC_V_NBBFC_REG1_ACEN_DIS << MXC_F_NBBFC_REG1_ACEN_POS) /**< REG1_ACEN_DIS Setting */ 169 #define MXC_V_NBBFC_REG1_ACEN_EN ((uint32_t)0x1UL) /**< REG1_ACEN_EN Value */ 170 #define MXC_S_NBBFC_REG1_ACEN_EN (MXC_V_NBBFC_REG1_ACEN_EN << MXC_F_NBBFC_REG1_ACEN_POS) /**< REG1_ACEN_EN Setting */ 171 172 #define MXC_F_NBBFC_REG1_ACRUN_POS 1 /**< REG1_ACRUN Position */ 173 #define MXC_F_NBBFC_REG1_ACRUN ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_ACRUN_POS)) /**< REG1_ACRUN Mask */ 174 #define MXC_V_NBBFC_REG1_ACRUN_NOT ((uint32_t)0x0UL) /**< REG1_ACRUN_NOT Value */ 175 #define MXC_S_NBBFC_REG1_ACRUN_NOT (MXC_V_NBBFC_REG1_ACRUN_NOT << MXC_F_NBBFC_REG1_ACRUN_POS) /**< REG1_ACRUN_NOT Setting */ 176 #define MXC_V_NBBFC_REG1_ACRUN_RUN ((uint32_t)0x1UL) /**< REG1_ACRUN_RUN Value */ 177 #define MXC_S_NBBFC_REG1_ACRUN_RUN (MXC_V_NBBFC_REG1_ACRUN_RUN << MXC_F_NBBFC_REG1_ACRUN_POS) /**< REG1_ACRUN_RUN Setting */ 178 179 #define MXC_F_NBBFC_REG1_LDTRM_POS 2 /**< REG1_LDTRM Position */ 180 #define MXC_F_NBBFC_REG1_LDTRM ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_LDTRM_POS)) /**< REG1_LDTRM Mask */ 181 182 #define MXC_F_NBBFC_REG1_GAININV_POS 3 /**< REG1_GAININV Position */ 183 #define MXC_F_NBBFC_REG1_GAININV ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_GAININV_POS)) /**< REG1_GAININV Mask */ 184 #define MXC_V_NBBFC_REG1_GAININV_NOT ((uint32_t)0x0UL) /**< REG1_GAININV_NOT Value */ 185 #define MXC_S_NBBFC_REG1_GAININV_NOT (MXC_V_NBBFC_REG1_GAININV_NOT << MXC_F_NBBFC_REG1_GAININV_POS) /**< REG1_GAININV_NOT Setting */ 186 #define MXC_V_NBBFC_REG1_GAININV_RUN ((uint32_t)0x1UL) /**< REG1_GAININV_RUN Value */ 187 #define MXC_S_NBBFC_REG1_GAININV_RUN (MXC_V_NBBFC_REG1_GAININV_RUN << MXC_F_NBBFC_REG1_GAININV_POS) /**< REG1_GAININV_RUN Setting */ 188 189 #define MXC_F_NBBFC_REG1_ATOMIC_POS 4 /**< REG1_ATOMIC Position */ 190 #define MXC_F_NBBFC_REG1_ATOMIC ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_ATOMIC_POS)) /**< REG1_ATOMIC Mask */ 191 #define MXC_V_NBBFC_REG1_ATOMIC_NOT ((uint32_t)0x0UL) /**< REG1_ATOMIC_NOT Value */ 192 #define MXC_S_NBBFC_REG1_ATOMIC_NOT (MXC_V_NBBFC_REG1_ATOMIC_NOT << MXC_F_NBBFC_REG1_ATOMIC_POS) /**< REG1_ATOMIC_NOT Setting */ 193 #define MXC_V_NBBFC_REG1_ATOMIC_RUN ((uint32_t)0x1UL) /**< REG1_ATOMIC_RUN Value */ 194 #define MXC_S_NBBFC_REG1_ATOMIC_RUN (MXC_V_NBBFC_REG1_ATOMIC_RUN << MXC_F_NBBFC_REG1_ATOMIC_POS) /**< REG1_ATOMIC_RUN Setting */ 195 196 #define MXC_F_NBBFC_REG1_MU_POS 8 /**< REG1_MU Position */ 197 #define MXC_F_NBBFC_REG1_MU ((uint32_t)(0xFFFUL << MXC_F_NBBFC_REG1_MU_POS)) /**< REG1_MU Mask */ 198 199 /**@} end of group NBBFC_REG1_Register */ 200 201 /** 202 * @ingroup nbbfc_registers 203 * @defgroup NBBFC_REG2 NBBFC_REG2 204 * @brief Register 2. 205 * @{ 206 */ 207 #define MXC_F_NBBFC_REG2_INTTRIM_POS 0 /**< REG2_INTTRIM Position */ 208 #define MXC_F_NBBFC_REG2_INTTRIM ((uint32_t)(0x1FFUL << MXC_F_NBBFC_REG2_INTTRIM_POS)) /**< REG2_INTTRIM Mask */ 209 210 #define MXC_F_NBBFC_REG2_MINTRM_POS 10 /**< REG2_MINTRM Position */ 211 #define MXC_F_NBBFC_REG2_MINTRM ((uint32_t)(0x1FFUL << MXC_F_NBBFC_REG2_MINTRM_POS)) /**< REG2_MINTRM Mask */ 212 213 #define MXC_F_NBBFC_REG2_MAXTRM_POS 20 /**< REG2_MAXTRM Position */ 214 #define MXC_F_NBBFC_REG2_MAXTRM ((uint32_t)(0x1FFUL << MXC_F_NBBFC_REG2_MAXTRM_POS)) /**< REG2_MAXTRM Mask */ 215 216 /**@} end of group NBBFC_REG2_Register */ 217 218 /** 219 * @ingroup nbbfc_registers 220 * @defgroup NBBFC_REG3 NBBFC_REG3 221 * @brief Register 3. 222 * @{ 223 */ 224 #define MXC_F_NBBFC_REG3_DONECNT_POS 0 /**< REG3_DONECNT Position */ 225 #define MXC_F_NBBFC_REG3_DONECNT ((uint32_t)(0xFFUL << MXC_F_NBBFC_REG3_DONECNT_POS)) /**< REG3_DONECNT Mask */ 226 227 /**@} end of group NBBFC_REG3_Register */ 228 229 #ifdef __cplusplus 230 } 231 #endif 232 233 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_NBBFC_REGS_H_ 234
