1 /* 2 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include "sdkconfig.h" 9 #include "esp_assert.h" 10 // #include "esp_flash_partitions.h" 11 12 #define MSPI_TIMING_CONFIG_NUM_DEFAULT 20 //This should be larger than the max available timing config num 13 #define MSPI_TIMING_TEST_DATA_LEN 64 14 #define MSPI_TIMING_PSRAM_TEST_DATA_ADDR 0 15 #define MSPI_TIMING_FLASH_TEST_DATA_ADDR ESP_BOOTLOADER_OFFSET 16 /** 17 * @note BACKGOURND: 18 * 19 * The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock: 20 * 21 * PLL ----| |---- FLASH Module Clock 22 * XTAL ----|----> Core Clock ---->| 23 * RTC8M ----| |---- PSRAM Module Clock 24 * 25 * 26 * DDR stands for double data rate, MSPI samples at both posedge and negedge. So the real spped will be doubled. 27 * Speed from high to low: 120M DDR > 80M DDR > 120 SDR > 80M SDR > ... 28 * 29 * Module with speed lower than 120M SDR doesn't need to be tuned 30 * 31 * @note LIMITATION: 32 * How to determine the core clock on 728. There are 2 limitations. 33 * 34 * 1. MSPI FLASH and PSRAM share the core clock register. Therefore: 35 * MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 36 * 37 * 2. DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2. 38 */ 39 //--------------------------------------FLASH Sampling Mode --------------------------------------// 40 #define MSPI_TIMING_FLASH_DTR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR 41 #define MSPI_TIMING_FLASH_STR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 42 //--------------------------------------FLASH Module Clock --------------------------------------// 43 #if CONFIG_ESPTOOLPY_FLASHFREQ_20M 44 #define MSPI_TIMING_FLASH_MODULE_CLOCK 20 45 #elif CONFIG_ESPTOOLPY_FLASHFREQ_40M 46 #define MSPI_TIMING_FLASH_MODULE_CLOCK 40 47 #elif CONFIG_ESPTOOLPY_FLASHFREQ_80M 48 #define MSPI_TIMING_FLASH_MODULE_CLOCK 80 49 #else //CONFIG_ESPTOOLPY_FLASHFREQ_120M 50 #define MSPI_TIMING_FLASH_MODULE_CLOCK 120 51 #endif 52 //------------------------------------FLASH Needs Tuning or not-------------------------------------// 53 #if MSPI_TIMING_FLASH_DTR_MODE 54 #define MSPI_TIMING_FLASH_NEEDS_TUNING (MSPI_TIMING_FLASH_MODULE_CLOCK > 40) 55 #elif MSPI_TIMING_FLASH_STR_MODE 56 #define MSPI_TIMING_FLASH_NEEDS_TUNING (MSPI_TIMING_FLASH_MODULE_CLOCK > 80) 57 #endif 58 59 //--------------------------------------PSRAM Sampling Mode --------------------------------------// 60 #define MSPI_TIMING_PSRAM_DTR_MODE CONFIG_SPIRAM_MODE_OCT 61 #define MSPI_TIMING_PSRAM_STR_MODE !CONFIG_SPIRAM_MODE_OCT 62 //--------------------------------------PSRAM Module Clock --------------------------------------// 63 #if CONFIG_SPIRAM 64 #if CONFIG_SPIRAM_SPEED_40M 65 #define MSPI_TIMING_PSRAM_MODULE_CLOCK 40 66 #elif CONFIG_SPIRAM_SPEED_80M 67 #define MSPI_TIMING_PSRAM_MODULE_CLOCK 80 68 #else //CONFIG_SPIRAM_SPEED_120M 69 #define MSPI_TIMING_PSRAM_MODULE_CLOCK 120 70 #endif 71 #else //Disable PSRAM 72 #define MSPI_TIMING_PSRAM_MODULE_CLOCK 10 //Define this to 10MHz, because we rely on `MSPI_TIMING_PSRAM_MODULE_CLOCK` macro for calculation and check below, see `Determine the Core Clock` chapter 73 #endif 74 //------------------------------------PSRAM Needs Tuning or not-------------------------------------// 75 #if MSPI_TIMING_PSRAM_DTR_MODE 76 #define MSPI_TIMING_PSRAM_NEEDS_TUNING (MSPI_TIMING_PSRAM_MODULE_CLOCK > 40) 77 #elif MSPI_TIMING_PSRAM_STR_MODE 78 #define MSPI_TIMING_PSRAM_NEEDS_TUNING (MSPI_TIMING_PSRAM_MODULE_CLOCK > 80) 79 #endif 80 81 82 /** 83 * @note Define A feasible core clock below: MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ and MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 84 */ 85 /** 86 * Due to MSPI core clock is used by both MSPI Flash and PSRAM clock, 87 * define the STR/DTR mode here for selecting the core clock: 88 * @note If either Flash or PSRAM, or both of them are set to DTR mode, then we use DIV 2 89 */ 90 #if (MSPI_TIMING_FLASH_DTR_MODE || MSPI_TIMING_PSRAM_DTR_MODE) 91 #define MSPI_TIMING_CORE_CLOCK_DIV 2 92 #else //#if (MSPI_TIMING_FLASH_STR_MODE && (MSPI_TIMING_PSRAM_STR_MODE)) 93 #define MSPI_TIMING_CORE_CLOCK_DIV 1 94 #endif 95 96 ///////////////////////////////////// FLASH CORE CLOCK ///////////////////////////////////// 97 //FLASH 80M DTR 98 #if MSPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_80M 99 #define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160 100 #endif 101 102 //FLASH 120M DTR 103 #if MSPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M 104 #define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 105 #endif 106 107 //FLASH 120M STR 108 #if MSPI_TIMING_FLASH_STR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M 109 #if (MSPI_TIMING_CORE_CLOCK_DIV == 2) 110 #define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 111 #elif (MSPI_TIMING_CORE_CLOCK_DIV == 1) 112 #define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 120 113 #endif 114 #endif //FLASH 120M STR 115 116 ///////////////////////////////////// PSRAM CORE CLOCK ///////////////////////////////////// 117 //PSRAM 80M DTR 118 #if MSPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_80M 119 #define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 160 120 #endif 121 122 //PSRAM 120M STR 123 #if MSPI_TIMING_PSRAM_STR_MODE && CONFIG_SPIRAM_SPEED_120M 124 #if (MSPI_TIMING_CORE_CLOCK_DIV == 2) 125 #define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240 126 #elif (MSPI_TIMING_CORE_CLOCK_DIV == 1) 127 #define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 120 128 #endif 129 #endif //PSRAM 120M STR 130 131 //PSRAM 120M STR 132 #if MSPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_120M 133 #define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240 134 #endif //PSRAM 120M DTR 135 136 137 //------------------------------------------Determine the Core Clock-----------------------------------------------// 138 /** 139 * @note 140 * Limitation 1: 141 * On 728, MSPI FLASH and PSRAM share the core clock register. Therefore, 142 * the expected CORE CLOCK frequencies should be the same. 143 */ 144 #if MSPI_TIMING_FLASH_NEEDS_TUNING && MSPI_TIMING_PSRAM_NEEDS_TUNING 145 ESP_STATIC_ASSERT(MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ, "FLASH and PSRAM Mode configuration are not supported"); 146 #define MSPI_TIMING_CORE_CLOCK_MHZ MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 147 148 //If only FLASH needs tuning, the core clock COULD be as FLASH expected 149 #elif MSPI_TIMING_FLASH_NEEDS_TUNING && !MSPI_TIMING_PSRAM_NEEDS_TUNING 150 ESP_STATIC_ASSERT(MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_PSRAM_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported"); 151 #define MSPI_TIMING_CORE_CLOCK_MHZ MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 152 153 //If only PSRAM needs tuning, the core clock COULD be as PSRAM expected 154 #elif !MSPI_TIMING_FLASH_NEEDS_TUNING && MSPI_TIMING_PSRAM_NEEDS_TUNING 155 ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported"); 156 #define MSPI_TIMING_CORE_CLOCK_MHZ MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 157 158 #else 159 #define MSPI_TIMING_CORE_CLOCK_MHZ 80 160 #endif 161 162 /** 163 * @note 164 * Limitation 2: DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2. 165 */ 166 #define CHECK_POWER_OF_2(n) ((((n) & ((~(n)) + 1))) == (n)) 167 168 #if MSPI_TIMING_FLASH_DTR_MODE 169 ESP_STATIC_ASSERT(CHECK_POWER_OF_2(MSPI_TIMING_CORE_CLOCK_MHZ / MSPI_TIMING_FLASH_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported"); 170 #endif 171 #if MSPI_TIMING_PSRAM_DTR_MODE 172 ESP_STATIC_ASSERT(CHECK_POWER_OF_2(MSPI_TIMING_CORE_CLOCK_MHZ / MSPI_TIMING_PSRAM_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported"); 173 #endif 174 175 176 //------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------// 177 #define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \ 178 (mspi_timing_config_t) { .tuning_config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \ 179 .available_config_num = MSPI_TIMING_##type##_CONFIG_NUM_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \ 180 .default_config_id = MSPI_TIMING_##type##_DEFAULT_CONFIG_ID_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode } 181 182 #define _GET_TUNING_CONFIG(type, core_clock, module_clock, mode) __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) 183 184 #define MSPI_TIMING_FLASH_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(FLASH, core_clock_mhz, module_clock_mhz, mode) 185 #define MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(PSRAM, core_clock_mhz, module_clock_mhz, mode) 186 187 188 189 /** 190 * Timing Tuning Parameters 191 */ 192 //FLASH: core clock 160M, module clock 40M, DTR mode 193 #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE {{1, 0, 0}, {0, 0, 0}, {2, 1, 1}, {2, 0, 1}, {2, 2, 2}, {2, 1, 2}, {1, 0, 1}, {0, 0, 1}} 194 #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE 8 195 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE 2 196 197 //FLASH: core clock 160M, module clock 80M, DTR mode 198 #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE {{0, 0, 0}, {4, 2, 2}, {2, 1, 2}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 2, 3}, {2, 1, 3}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 2, 4}} 199 #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 14 200 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 1 201 202 //FLASH: core clock 240M, module clock 120M, DTR mode 203 #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE {{0, 0, 0}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 1, 4}, {1, 0, 3}, {4, 0, 4}, {0, 0, 3}, {4, 1, 5}} 204 #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 14 205 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 1 206 207 //FLASH: core clock 160M, module clock 80M, STR mode 208 #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_80M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {2, 1, 1}, {2, 0, 1}, {2, 2, 2}, {2, 1, 2}, {1, 0, 1}, {0, 0, 1}} 209 #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_80M_STR_MODE 8 210 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_STR_MODE 2 211 212 //FLASH: core clock 120M, module clock 120M, STR mode 213 #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {1, 0, 1}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {1, 0, 2}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {1, 0, 3}} 214 #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12 215 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 2 216 217 //FLASH: core clock 240M, module clock 120M, STR mode 218 #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {1, 1, 1}, {2, 3, 2}, {1, 0, 1}, {0, 0, 1}, {1, 1, 2}, {2, 3, 3}, {1, 0, 2}, {0, 0, 2}, {1, 1, 3}, {2, 3, 4}} 219 #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 12 220 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 2 221 222 //PSRAM: core clock 80M, module clock 40M, DTR mode 223 #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_40M_DTR_MODE {{1, 0, 0}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 1}, {3, 0, 1}, {1, 0, 1}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 2}, {3, 0, 2}} 224 #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_40M_DTR_MODE 12 225 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_40M_DTR_MODE 4 226 227 //PSRAM: core clock 160M, module clock 80M, DTR mode 228 #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE {{0, 0, 0}, {4, 2, 2}, {2, 1, 2}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 2, 3}, {2, 1, 3}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 2, 4}} 229 #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 14 230 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 5 231 232 //PSRAM: core clock 240M, module clock 120M, STR mode 233 #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {1, 1, 1}, {2, 3, 2}, {1, 0, 1}, {0, 0, 1}, {1, 1, 2}, {2, 3, 3}, {1, 0, 2}, {0, 0, 2}, {1, 1, 3}, {2, 3, 4}} 234 #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 12 235 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 2 236 237 //PSRAM: core clock 120M, module clock 120M, STR mode 238 #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {1, 0, 1}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {1, 0, 2}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {1, 0, 3}} 239 #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12 240 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 2 241 242 //PSRAM: core clock 240M, module clock 120M, DTR mode 243 #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE {{0, 0, 0}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 1, 4}, {1, 0, 3}, {4, 0, 4}, {0, 0, 3}, {4, 1, 5}} 244 #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 14 245 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 1 246 247 //------------------------------------------Frequency Scanning Related-----------------------------------------------// 248 /** 249 * On ESP32S3, only module clock 120M, DDR mode needs frequency scan. Frequency scanning is to get the max workable PLL 250 * frequency under each successfull timing tuning configuration. PLL frequency may fluctuate under high temperature, 251 * this method is to get the tuning configuration that can work under higher PLL frequency. 252 */ 253 #define MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MIN 440 254 #define MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX 600 255 #define MSPI_TIMING_PLL_FREQ_SCAN_THRESH_MHZ_LOW 448 256 #define MSPI_TIMING_PLL_FREQ_SCAN_THRESH_MHZ_HIGH 520 257 #define MSPI_TIMING_PLL_FREQ_SCAN_STEP_MHZ_MODULE_CLK_120M 8 258
