1 /*
2 * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdlib.h>
8 #include <string.h>
9 #include "sdkconfig.h"
10 #include "esp_attr.h"
11 #include "esp_err.h"
12 #include "esp_types.h"
13 #include "esp_log.h"
14 #include "soc/spi_mem_reg.h"
15 #include "soc/io_mux_reg.h"
16 #include "esp_private/mspi_timing_tuning.h"
17 #include "soc/soc.h"
18 #include "soc/rtc.h"
19 #include "hal/spi_flash_hal.h"
20 #include "hal/mspi_timing_tuning_ll.h"
21 #include "hal/clk_tree_ll.h"
22 #include "hal/regi2c_ctrl_ll.h"
23 #include "mspi_timing_config.h"
24 #if CONFIG_IDF_TARGET_ESP32S3
25 #include "esp32s3/rom/cache.h"
26 #endif
27
28 #if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
29 const static char *TAG = "MSPI Timing";
30 static mspi_timing_tuning_param_t s_flash_best_timing_tuning_config;
31 static mspi_timing_tuning_param_t s_psram_best_timing_tuning_config;
32 #endif
33
34 /*------------------------------------------------------------------------------
35 * Common settings
36 *----------------------------------------------------------------------------*/
mspi_timing_set_pin_drive_strength(void)37 void mspi_timing_set_pin_drive_strength(void)
38 {
39 //For now, set them all to 3. Need to check after QVL test results are out. TODO: IDF-3663
40 //Set default clk
41 mspi_timing_ll_set_all_pin_drive(0, 3);
42 }
43
44 /*------------------------------------------------------------------------------
45 * Static functions to get clock configs
46 *----------------------------------------------------------------------------*/
get_mspi_core_clock(void)47 static mspi_timing_config_core_clock_t get_mspi_core_clock(void)
48 {
49 return mspi_timing_config_get_core_clock();
50 }
51
get_flash_clock_divider(void)52 static uint32_t get_flash_clock_divider(void)
53 {
54 #if CONFIG_ESPTOOLPY_FLASHFREQ_20M
55 return MSPI_TIMING_CORE_CLOCK_MHZ / 20;
56 #elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
57 return MSPI_TIMING_CORE_CLOCK_MHZ / 40;
58 #elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
59 return MSPI_TIMING_CORE_CLOCK_MHZ / 80;
60 #elif CONFIG_ESPTOOLPY_FLASHFREQ_120M
61 return MSPI_TIMING_CORE_CLOCK_MHZ / 120;
62 #else
63 abort();
64 #endif
65 }
66
get_psram_clock_divider(void)67 static uint32_t get_psram_clock_divider(void)
68 {
69 #if CONFIG_SPIRAM_SPEED_40M
70 return MSPI_TIMING_CORE_CLOCK_MHZ / 40;
71 #elif CONFIG_SPIRAM_SPEED_80M
72 return MSPI_TIMING_CORE_CLOCK_MHZ / 80;
73 #elif CONFIG_SPIRAM_SPEED_120M
74 return MSPI_TIMING_CORE_CLOCK_MHZ / 120;
75 #else
76 //Will enter this branch only if PSRAM is not enable
77 return 0;
78 #endif
79 }
80
81 #if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
82 /*------------------------------------------------------------------------------
83 * Static functions to do timing tuning
84 *----------------------------------------------------------------------------*/
85 /**
86 * Set timing tuning regs, in order to get successful sample points
87 */
init_spi1_for_tuning(bool is_flash)88 static void init_spi1_for_tuning(bool is_flash)
89 {
90 //Get required core clock and module clock settings
91 mspi_timing_config_core_clock_t core_clock = get_mspi_core_clock();
92 //Set SPI1 core clock. SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
93 mspi_timing_config_set_core_clock(0, core_clock);
94 //Set SPI1 module clock as required
95 if (is_flash) {
96 uint32_t flash_div = get_flash_clock_divider();
97 mspi_timing_config_set_flash_clock(1, flash_div);
98 //Power on HCLK
99 mspi_timinng_ll_enable_flash_hclk(0);
100 } else {
101 //We use SPI1 Flash to tune PSRAM, PSRAM timing related regs do nothing on SPI1
102 uint32_t psram_div = get_psram_clock_divider();
103 mspi_timing_config_set_flash_clock(1, psram_div);
104 //Power on HCLK
105 mspi_timinng_ll_enable_psram_hclk(0);
106 }
107 }
108
109 /**
110 * We use different SPI1 timing tuning config to read data to see if current MSPI sampling is successful.
111 * The sampling result will be stored in an array. In this array, successful item will be 1, failed item will be 0.
112 */
sweep_for_success_sample_points(const uint8_t * reference_data,const mspi_timing_config_t * config,bool is_flash,uint8_t * out_array)113 static void sweep_for_success_sample_points(const uint8_t *reference_data, const mspi_timing_config_t *config, bool is_flash, uint8_t *out_array)
114 {
115 uint32_t config_idx = 0;
116 uint8_t read_data[MSPI_TIMING_TEST_DATA_LEN] = {0};
117
118 for (config_idx = 0; config_idx < config->available_config_num; config_idx++) {
119 memset(read_data, 0, MSPI_TIMING_TEST_DATA_LEN);
120 #if MSPI_TIMING_FLASH_NEEDS_TUNING
121 if (is_flash) {
122 mspi_timing_config_flash_set_tuning_regs(&(config->tuning_config_table[config_idx]));
123 mspi_timing_config_flash_read_data(read_data, MSPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(read_data));
124 }
125 #endif
126 #if MSPI_TIMING_PSRAM_NEEDS_TUNING
127 if (!is_flash) {
128 mspi_timing_config_psram_set_tuning_regs(&(config->tuning_config_table[config_idx]));
129 mspi_timing_config_psram_read_data(read_data, MSPI_TIMING_PSRAM_TEST_DATA_ADDR, MSPI_TIMING_TEST_DATA_LEN);
130 }
131 #endif
132 if (memcmp(reference_data, read_data, sizeof(read_data)) == 0) {
133 out_array[config_idx] = 1;
134 ESP_EARLY_LOGD(TAG, "%d, good", config_idx);
135 } else {
136 ESP_EARLY_LOGD(TAG, "%d, bad", config_idx);
137 }
138 }
139 }
140
141 /**
142 * Find consecutive successful sampling points.
143 * e.g. array: {1, 1, 0, 0, 1, 1, 1, 0}
144 * out_length: 3
145 * outout_end_index: 6
146 */
find_max_consecutive_success_points(uint8_t * array,uint32_t size,uint32_t * out_length,uint32_t * out_end_index)147 static void find_max_consecutive_success_points(uint8_t *array, uint32_t size, uint32_t *out_length, uint32_t *out_end_index)
148 {
149 uint32_t max = 0;
150 uint32_t match_num = 0;
151 uint32_t i = 0;
152 uint32_t end = 0;
153
154 while (i < size) {
155 if (array[i]) {
156 match_num++;
157 } else {
158 if (match_num > max) {
159 max = match_num;
160 end = i - 1;
161 }
162 match_num = 0;
163 }
164 i++;
165 }
166
167 *out_length = match_num > max ? match_num : max;
168 *out_end_index = match_num == size ? size : end;
169 }
170
171 #if (MSPI_TIMING_FLASH_DTR_MODE || MSPI_TIMING_PSRAM_DTR_MODE) && (MSPI_TIMING_CORE_CLOCK_MHZ == 240)
get_working_pll_freq(const uint8_t * reference_data,bool is_flash,uint32_t * out_max_freq,uint32_t * out_min_freq)172 static bool get_working_pll_freq(const uint8_t *reference_data, bool is_flash, uint32_t *out_max_freq, uint32_t *out_min_freq)
173 {
174 uint8_t read_data[MSPI_TIMING_TEST_DATA_LEN] = {0};
175 rtc_cpu_freq_config_t previous_config;
176 rtc_clk_cpu_freq_get_config(&previous_config);
177
178 uint32_t big_num = MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX * 2; //This number should be larger than MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX, for error handling
179 uint32_t max_freq = 0;
180 uint32_t min_freq = big_num;
181 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
182
183 for (int pll_mhz_tuning = MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MIN; pll_mhz_tuning <= MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX; pll_mhz_tuning += 8) {
184 //bbpll calibration start
185 regi2c_ctrl_ll_bbpll_calibration_start();
186
187 /**
188 * pll_mhz = xtal_mhz * (oc_div + 4) / (oc_ref_div + 1)
189 */
190 clk_ll_bbpll_set_frequency_for_mspi_tuning(xtal_freq, pll_mhz_tuning, ((pll_mhz_tuning / 4) - 4), 9);
191
192 //wait calibration done
193 while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
194
195 //bbpll calibration stop
196 regi2c_ctrl_ll_bbpll_calibration_stop();
197
198 memset(read_data, 0, MSPI_TIMING_TEST_DATA_LEN);
199 if (is_flash) {
200 mspi_timing_config_flash_read_data(read_data, MSPI_TIMING_FLASH_TEST_DATA_ADDR, MSPI_TIMING_TEST_DATA_LEN);
201 } else {
202 mspi_timing_config_psram_read_data(read_data, MSPI_TIMING_PSRAM_TEST_DATA_ADDR, MSPI_TIMING_TEST_DATA_LEN);
203 }
204
205 if (memcmp(read_data, reference_data, MSPI_TIMING_TEST_DATA_LEN) == 0) {
206 max_freq = MAX(pll_mhz_tuning, max_freq);
207 min_freq = MIN(pll_mhz_tuning, min_freq);
208
209 //Continue to find successful cases
210 continue;
211 }
212
213 if (max_freq != 0) {
214 //The first fail case after successful case(s) is the end
215 break;
216 }
217
218 //If no break, no successful case found, continue to find successful cases
219 }
220
221 //restore PLL config
222 clk_ll_bbpll_set_freq_mhz(previous_config.source_freq_mhz);
223 //bbpll calibration start
224 regi2c_ctrl_ll_bbpll_calibration_start();
225 //set pll
226 clk_ll_bbpll_set_config(previous_config.source_freq_mhz, xtal_freq);
227 //wait calibration done
228 while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
229 //bbpll calibration stop
230 regi2c_ctrl_ll_bbpll_calibration_stop();
231
232
233 *out_max_freq = max_freq;
234 *out_min_freq = min_freq;
235
236 return (max_freq != 0);
237 }
238 #endif //Frequency Scanning
239
240 #if MSPI_TIMING_FLASH_DTR_MODE || MSPI_TIMING_PSRAM_DTR_MODE
select_best_tuning_config_dtr(mspi_timing_config_t * config,uint32_t consecutive_length,uint32_t end,const uint8_t * reference_data,bool is_flash)241 static uint32_t select_best_tuning_config_dtr(mspi_timing_config_t *config, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_flash)
242 {
243 #if (MSPI_TIMING_CORE_CLOCK_MHZ == 160)
244 //Core clock 160M DTR best point scheme
245 (void) reference_data;
246 (void) is_flash;
247 uint32_t best_point = 0;
248
249 //These numbers will probably be same on other chips, if this version of algorithm is utilised
250 if (consecutive_length <= 2 || consecutive_length >= 6) {
251 //tuning is FAIL, select default point, and generate a warning
252 best_point = config->default_config_id;
253 ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point);
254 } else if (consecutive_length <= 4) {
255 //consecutive length : 3 or 4
256 best_point = end - 1;
257 ESP_EARLY_LOGD(TAG,"tuning success, best point is index %d", best_point);
258 } else {
259 //consecutive point list length equals 5
260 best_point = end - 2;
261 ESP_EARLY_LOGD(TAG,"tuning success, best point is index %d", best_point);
262 }
263
264 return best_point;
265
266 #elif (MSPI_TIMING_CORE_CLOCK_MHZ == 240)
267
268 uint32_t best_point = 0;
269 uint32_t current_point = end + 1 - consecutive_length;
270 bool ret = false;
271
272 //This `max_freq` is the max pll frequency that per MSPI timing tuning config can work
273 uint32_t max_freq = 0;
274 uint32_t temp_max_freq = 0;
275 uint32_t temp_min_freq = 0;
276
277 for (; current_point <= end; current_point++) {
278 if (is_flash) {
279 mspi_timing_config_flash_set_tuning_regs(&(config->tuning_config_table[current_point]));
280 } else {
281 mspi_timing_config_psram_set_tuning_regs(&(config->tuning_config_table[current_point]));
282 }
283
284 ret = get_working_pll_freq(reference_data, is_flash, &temp_max_freq, &temp_min_freq);
285 if (ret && temp_min_freq <= MSPI_TIMING_PLL_FREQ_SCAN_THRESH_MHZ_LOW && temp_max_freq >= MSPI_TIMING_PLL_FREQ_SCAN_THRESH_MHZ_HIGH && temp_max_freq > max_freq) {
286 max_freq = temp_max_freq;
287 best_point = current_point;
288 }
289 ESP_EARLY_LOGD(TAG, "sample point %d, max pll is %d mhz, min pll is %d\n", current_point, temp_max_freq, temp_min_freq);
290 }
291 if (max_freq == 0) {
292 ESP_EARLY_LOGW(TAG, "freq scan tuning fail, best point is fallen back to index %d", end + 1 - consecutive_length);
293 best_point = end + 1 - consecutive_length;
294 } else {
295 ESP_EARLY_LOGD(TAG, "freq scan success, max pll is %dmhz, best point is index %d", max_freq, best_point);
296 }
297
298 return best_point;
299
300 #else
301 //won't reach here
302 abort();
303 #endif
304 }
305 #endif
306
307 #if MSPI_TIMING_FLASH_STR_MODE || MSPI_TIMING_PSRAM_STR_MODE
select_best_tuning_config_str(mspi_timing_config_t * config,uint32_t consecutive_length,uint32_t end)308 static uint32_t select_best_tuning_config_str(mspi_timing_config_t *config, uint32_t consecutive_length, uint32_t end)
309 {
310 #if (MSPI_TIMING_CORE_CLOCK_MHZ == 120 || MSPI_TIMING_CORE_CLOCK_MHZ == 240)
311 //STR best point scheme
312 uint32_t best_point;
313
314 if (consecutive_length <= 2|| consecutive_length >= 5) {
315 //tuning is FAIL, select default point, and generate a warning
316 best_point = config->default_config_id;
317 ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point);
318 } else {
319 //consecutive length : 3 or 4
320 best_point = end - consecutive_length / 2;
321 ESP_EARLY_LOGD(TAG,"tuning success, best point is index %d", best_point);
322 }
323
324 return best_point;
325 #else
326 //won't reach here
327 abort();
328 #endif
329 }
330 #endif
331
select_best_tuning_config(mspi_timing_config_t * config,uint32_t consecutive_length,uint32_t end,const uint8_t * reference_data,bool is_flash)332 static void select_best_tuning_config(mspi_timing_config_t *config, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_flash)
333 {
334 uint32_t best_point = 0;
335 if (is_flash) {
336 #if MSPI_TIMING_FLASH_DTR_MODE
337 best_point = select_best_tuning_config_dtr(config, consecutive_length, end, reference_data, is_flash);
338 #elif MSPI_TIMING_FLASH_STR_MODE
339 best_point = select_best_tuning_config_str(config, consecutive_length, end);
340 #endif
341 s_flash_best_timing_tuning_config = config->tuning_config_table[best_point];
342 ESP_EARLY_LOGI(TAG, "Flash timing tuning index: %d", best_point);
343 } else {
344 #if MSPI_TIMING_PSRAM_DTR_MODE
345 best_point = select_best_tuning_config_dtr(config, consecutive_length, end, reference_data, is_flash);
346 #elif MSPI_TIMING_PSRAM_STR_MODE
347 best_point = select_best_tuning_config_str(config, consecutive_length, end);
348 #endif
349 s_psram_best_timing_tuning_config = config->tuning_config_table[best_point];
350 ESP_EARLY_LOGI(TAG, "PSRAM timing tuning index: %d", best_point);
351 }
352 }
353
do_tuning(const uint8_t * reference_data,mspi_timing_config_t * timing_config,bool is_flash)354 static void do_tuning(const uint8_t *reference_data, mspi_timing_config_t *timing_config, bool is_flash)
355 {
356 /**
357 * We use SPI1 to tune the timing:
358 * 1. Get all SPI1 sampling results.
359 * 2. Find the longest consecutive successful sampling points from the result above.
360 * 3. The middle one will be the best sampling point.
361 */
362 uint32_t consecutive_length = 0;
363 uint32_t last_success_point = 0;
364 uint8_t sample_result[MSPI_TIMING_CONFIG_NUM_DEFAULT] = {0};
365
366 init_spi1_for_tuning(is_flash);
367 sweep_for_success_sample_points(reference_data, timing_config, is_flash, sample_result);
368 find_max_consecutive_success_points(sample_result, MSPI_TIMING_CONFIG_NUM_DEFAULT, &consecutive_length, &last_success_point);
369 select_best_tuning_config(timing_config, consecutive_length, last_success_point, reference_data, is_flash);
370 }
371 #endif //#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
372
373
374 /*------------------------------------------------------------------------------
375 * FLASH Timing Tuning
376 *----------------------------------------------------------------------------*/
377 #if MSPI_TIMING_FLASH_NEEDS_TUNING
get_flash_tuning_configs(mspi_timing_config_t * config)378 static void get_flash_tuning_configs(mspi_timing_config_t *config)
379 {
380 #if MSPI_TIMING_FLASH_DTR_MODE
381 #define FLASH_MODE DTR_MODE
382 #else //MSPI_TIMING_FLASH_STR_MODE
383 #define FLASH_MODE STR_MODE
384 #endif
385
386 #if CONFIG_ESPTOOLPY_FLASHFREQ_20M
387 *config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 20, FLASH_MODE);
388 #elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
389 *config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 40, FLASH_MODE);
390 #elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
391 *config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 80, FLASH_MODE);
392 #elif CONFIG_ESPTOOLPY_FLASHFREQ_120M
393 *config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 120, FLASH_MODE);
394 #endif
395
396 #undef FLASH_MODE
397 }
398
mspi_timing_flash_tuning(void)399 void mspi_timing_flash_tuning(void)
400 {
401 /**
402 * set SPI01 related regs to 20mhz configuration, to get reference data from FLASH
403 * see detailed comments in this function (`mspi_timing_enter_low_speed_mode`)
404 */
405 mspi_timing_enter_low_speed_mode(true);
406
407 //Disable the variable dummy mode when doing timing tuning
408 mspi_timing_ll_enable_flash_variable_dummy(1, false); //GD flash will read error in variable mode with 20MHz
409
410 uint8_t reference_data[MSPI_TIMING_TEST_DATA_LEN] = {0};
411 mspi_timing_config_flash_read_data(reference_data, MSPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(reference_data));
412 mspi_timing_config_t timing_configs = {0};
413 get_flash_tuning_configs(&timing_configs);
414
415 do_tuning(reference_data, &timing_configs, true);
416 mspi_timing_enter_high_speed_mode(true);
417 }
418 #else
mspi_timing_flash_tuning(void)419 void mspi_timing_flash_tuning(void)
420 {
421 //Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned
422 }
423 #endif //MSPI_TIMING_FLASH_NEEDS_TUNING
424
425
426 /*------------------------------------------------------------------------------
427 * PSRAM Timing Tuning
428 *----------------------------------------------------------------------------*/
429 #if MSPI_TIMING_PSRAM_NEEDS_TUNING
get_psram_tuning_configs(mspi_timing_config_t * config)430 static void get_psram_tuning_configs(mspi_timing_config_t *config)
431 {
432 #if MSPI_TIMING_PSRAM_DTR_MODE
433 #define PSRAM_MODE DTR_MODE
434 #else //MSPI_TIMING_PSRAM_STR_MODE
435 #define PSRAM_MODE STR_MODE
436 #endif
437
438 #if CONFIG_SPIRAM_SPEED_40M
439 *config = MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 40, PSRAM_MODE);
440 #elif CONFIG_SPIRAM_SPEED_80M
441 *config = MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 80, PSRAM_MODE);
442 #elif CONFIG_SPIRAM_SPEED_120M
443 *config = MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 120, PSRAM_MODE);
444 #endif
445
446 #undef PSRAM_MODE
447 }
448
mspi_timing_psram_tuning(void)449 void mspi_timing_psram_tuning(void)
450 {
451 /**
452 * set SPI01 related regs to 20mhz configuration, to write reference data to PSRAM
453 * see detailed comments in this function (`mspi_timing_enter_low_speed_mode`)
454 */
455 mspi_timing_enter_low_speed_mode(true);
456
457 // write data into psram, used to do timing tuning test.
458 uint8_t reference_data[MSPI_TIMING_TEST_DATA_LEN];
459 for (int i=0; i < MSPI_TIMING_TEST_DATA_LEN/4; i++) {
460 ((uint32_t *)reference_data)[i] = 0xa5ff005a;
461 }
462 mspi_timing_config_psram_write_data(reference_data, MSPI_TIMING_PSRAM_TEST_DATA_ADDR, MSPI_TIMING_TEST_DATA_LEN);
463 mspi_timing_config_t timing_configs = {0};
464 get_psram_tuning_configs(&timing_configs);
465
466 //Disable the variable dummy mode when doing timing tuning
467 mspi_timing_ll_enable_flash_variable_dummy(1, false);
468 //Get required config, and set them to PSRAM related registers
469 do_tuning(reference_data, &timing_configs, false);
470 mspi_timing_enter_high_speed_mode(true);
471 }
472
473 #else
mspi_timing_psram_tuning(void)474 void mspi_timing_psram_tuning(void)
475 {
476 //Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned
477 }
478 #endif //MSPI_TIMING_PSRAM_NEEDS_TUNING
479
480
481 /*------------------------------------------------------------------------------
482 * APIs to make SPI0 (and SPI1) FLASH work for high/low freq
483 *----------------------------------------------------------------------------*/
484 #if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
clear_timing_tuning_regs(bool control_spi1)485 static void clear_timing_tuning_regs(bool control_spi1)
486 {
487 mspi_timing_config_flash_set_din_mode_num(0, 0, 0); //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg
488 mspi_timing_config_flash_set_extra_dummy(0, 0);
489 if (control_spi1) {
490 mspi_timing_config_flash_set_extra_dummy(1, 0);
491 } else {
492 //Won't touch SPI1 registers
493 }
494
495 mspi_timing_config_psram_set_din_mode_num(0, 0, 0);
496 mspi_timing_config_psram_set_extra_dummy(0, 0);
497 }
498 #endif //#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
499
mspi_timing_enter_low_speed_mode(bool control_spi1)500 void mspi_timing_enter_low_speed_mode(bool control_spi1)
501 {
502 /**
503 * Here we are going to slow the SPI1 frequency to 20Mhz, so we need to set SPI1 din_num and din_mode regs.
504 *
505 * Because SPI0 and SPI1 share the din_num and din_mode regs, so if we clear SPI1 din_num and din_mode to
506 * 0, if the SPI0 flash module clock is still in high freq, it may not work correctly.
507 *
508 * Therefore, here we need to slow both the SPI0 and SPI1 and related timing tuning regs to 20Mhz configuration.
509 */
510
511 //Switch SPI1 and SPI0 clock as 20MHz, set its SPIMEM core clock as 80M and set clock division as 4
512 mspi_timing_config_set_core_clock(0, MSPI_TIMING_CONFIG_CORE_CLOCK_80M); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
513 mspi_timing_config_set_flash_clock(0, 4);
514 if (control_spi1) {
515 //After tuning, won't touch SPI1 again
516 mspi_timing_config_set_flash_clock(1, 4);
517 }
518
519 //Set PSRAM module clock
520 mspi_timing_config_set_psram_clock(0, 4);
521
522 #if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
523 clear_timing_tuning_regs(control_spi1);
524 #endif
525 }
526
527 #if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
set_timing_tuning_regs_as_required(bool control_spi1)528 static void set_timing_tuning_regs_as_required(bool control_spi1)
529 {
530 //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg
531 mspi_timing_config_flash_set_din_mode_num(0, s_flash_best_timing_tuning_config.spi_din_mode, s_flash_best_timing_tuning_config.spi_din_num);
532 mspi_timing_config_flash_set_extra_dummy(0, s_flash_best_timing_tuning_config.extra_dummy_len);
533 if (control_spi1) {
534 mspi_timing_config_flash_set_extra_dummy(1, s_flash_best_timing_tuning_config.extra_dummy_len);
535 }
536
537 mspi_timing_config_psram_set_din_mode_num(0, s_psram_best_timing_tuning_config.spi_din_mode, s_psram_best_timing_tuning_config.spi_din_num);
538 mspi_timing_config_psram_set_extra_dummy(0, s_psram_best_timing_tuning_config.extra_dummy_len);
539 }
540 #endif //#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
541
542 /**
543 * Set SPI0 FLASH and PSRAM module clock, din_num, din_mode and extra dummy,
544 * according to the configuration got from timing tuning function (`calculate_best_flash_tuning_config`).
545 * iF control_spi1 == 1, will also update SPI1 timing registers. Should only be set to 1 when do tuning.
546 *
547 * This function should always be called after `mspi_timing_flash_tuning` or `calculate_best_flash_tuning_config`
548 */
mspi_timing_enter_high_speed_mode(bool control_spi1)549 void mspi_timing_enter_high_speed_mode(bool control_spi1)
550 {
551 mspi_timing_config_core_clock_t core_clock = get_mspi_core_clock();
552 uint32_t flash_div = get_flash_clock_divider();
553 uint32_t psram_div = get_psram_clock_divider();
554
555 //Set SPI01 core clock
556 mspi_timing_config_set_core_clock(0, core_clock); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
557 //Set FLASH module clock
558 mspi_timing_config_set_flash_clock(0, flash_div);
559 if (control_spi1) {
560 mspi_timing_config_set_flash_clock(1, flash_div);
561 }
562 //Set PSRAM module clock
563 mspi_timing_config_set_psram_clock(0, psram_div);
564
565 #if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
566 set_timing_tuning_regs_as_required(true);
567 #endif
568 }
569
mspi_timing_change_speed_mode_cache_safe(bool switch_down)570 void mspi_timing_change_speed_mode_cache_safe(bool switch_down)
571 {
572 Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
573 Cache_Freeze_DCache_Enable(CACHE_FREEZE_ACK_BUSY);
574 if (switch_down) {
575 //enter MSPI low speed mode, extra delays should be removed
576 mspi_timing_enter_low_speed_mode(false);
577 } else {
578 //enter MSPI high speed mode, extra delays should be considered
579 mspi_timing_enter_high_speed_mode(false);
580 }
581 Cache_Freeze_DCache_Disable();
582 Cache_Freeze_ICache_Disable();
583 }
584
585 /*------------------------------------------------------------------------------
586 * APIs to inform SPI1 Flash driver of necessary timing configurations
587 *----------------------------------------------------------------------------*/
spi_timing_is_tuned(void)588 bool spi_timing_is_tuned(void)
589 {
590 #if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
591 return true;
592 #else
593 return false;
594 #endif
595 }
596
597 #if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t * out_timing_config)598 void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config)
599 {
600 // Get clock configuration directly from system.
601 out_timing_config->clock_config.spimem = mspi_timing_config_get_flash_clock_reg();
602
603 // Get extra dummy length here. Therefore, no matter what freq, or mode.
604 // If it needs tuning, it will return correct extra dummy len. If no tuning, it will return 0.
605
606 out_timing_config->extra_dummy = s_flash_best_timing_tuning_config.extra_dummy_len;
607
608 // Get CS setup/hold value here.
609 mspi_timing_config_get_cs_timing(&out_timing_config->cs_setup, &out_timing_config->cs_hold);
610 }
611 #else
spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t * out_timing_config)612 void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config)
613 {
614 // This function shouldn't be called if timing tuning is not used.
615 abort();
616 }
617 #endif // MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
618
