1 /******************************************************************************
2 *
3 * Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 *  Redistributions of source code must retain the above copyright
10 *  notice, this list of conditions and the following disclaimer.
11 *
12 *  Redistributions in binary form must reproduce the above copyright
13 *  notice, this list of conditions and the following disclaimer in the
14 *  documentation and/or other materials provided with the
15 *  distribution.
16 *
17 *  Neither the name of Texas Instruments Incorporated nor the names of
18 *  its contributors may be used to endorse or promote products derived
19 *  from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * MSP432P401R Register Definitions
34 *
35 * This file includes MSP430 style component and register definitions
36 * for legacy components re-used in MSP432
37 *
38 * File creation date: 2017-08-03
39 *
40 ******************************************************************************/
41 
42 #ifndef __MSP432P401R_CLASSIC_H__
43 #define __MSP432P401R_CLASSIC_H__
44 
45 /* Use standard integer types with explicit width */
46 #include <stdint.h>
47 
48 #ifdef __cplusplus
49  extern "C" {
50 #endif
51 
52 /******************************************************************************
53 * Device memory map                                                           *
54 ******************************************************************************/
55 #define __MAIN_MEMORY_START__                              (0x00000000)          /*!< Main Flash memory start address */
56 #define __MAIN_MEMORY_END__                                (0x0003FFFF)          /*!< Main Flash memory end address */
57 #define __BSL_MEMORY_START__                               (0x00202000)          /*!< BSL memory start address */
58 #define __BSL_MEMORY_END__                                 (0x00203FFF)          /*!< BSL memory end address */
59 #define __SRAM_START__                                     (0x20000000)          /*!< SRAM memory start address */
60 #define __SRAM_END__                                       (0x2000FFFF)          /*!< SRAM memory end address */
61 
62 /******************************************************************************
63 * MSP-format peripheral registers                                             *
64 ******************************************************************************/
65 
66 /******************************************************************************
67 * AES256 Registers
68 ******************************************************************************/
69 #define AESACTL0                                 (HWREG16(0x40003C00))           /*!< AES Accelerator Control Register 0 */
70 #define AESACTL1                                 (HWREG16(0x40003C02))           /*!< AES Accelerator Control Register 1 */
71 #define AESASTAT                                 (HWREG16(0x40003C04))           /*!< AES Accelerator Status Register */
72 #define AESAKEY                                  (HWREG16(0x40003C06))           /*!< AES Accelerator Key Register */
73 #define AESADIN                                  (HWREG16(0x40003C08))           /*!< AES Accelerator Data In Register */
74 #define AESADOUT                                 (HWREG16(0x40003C0A))           /*!< AES Accelerator Data Out Register */
75 #define AESAXDIN                                 (HWREG16(0x40003C0C))           /*!< AES Accelerator XORed Data In Register */
76 #define AESAXIN                                  (HWREG16(0x40003C0E))           /*!< AES Accelerator XORed Data In Register */
77 
78 /* Register offsets from AES256_BASE address */
79 #define OFS_AESACTL0                                       (0x0000)              /*!< AES Accelerator Control Register 0 */
80 #define OFS_AESACTL1                                       (0x0002)              /*!< AES Accelerator Control Register 1 */
81 #define OFS_AESASTAT                                       (0x0004)              /*!< AES Accelerator Status Register */
82 #define OFS_AESAKEY                                        (0x0006)              /*!< AES Accelerator Key Register */
83 #define OFS_AESADIN                                        (0x0008)              /*!< AES Accelerator Data In Register */
84 #define OFS_AESADOUT                                       (0x000A)              /*!< AES Accelerator Data Out Register */
85 #define OFS_AESAXDIN                                       (0x000C)              /*!< AES Accelerator XORed Data In Register */
86 #define OFS_AESAXIN                                        (0x000E)              /*!< AES Accelerator XORed Data In Register */
87 
88 
89 /******************************************************************************
90 * CAPTIO0 Registers
91 ******************************************************************************/
92 #define CAPTIO0CTL                               (HWREG16(0x4000540E))           /*!< Capacitive Touch IO x Control Register */
93 
94 /* Register offsets from CAPTIO0_BASE address */
95 #define OFS_CAPTIO0CTL                                     (0x000E)              /*!< Capacitive Touch IO x Control Register */
96 
97 #define CAPTIO0CTL_L                                       (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
98 #define CAPTIO0CTL_H                                       (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
99 
100 /******************************************************************************
101 * CAPTIO1 Registers
102 ******************************************************************************/
103 #define CAPTIO1CTL                               (HWREG16(0x4000580E))           /*!< Capacitive Touch IO x Control Register */
104 
105 /* Register offsets from CAPTIO1_BASE address */
106 #define OFS_CAPTIO1CTL                                     (0x000E)              /*!< Capacitive Touch IO x Control Register */
107 
108 #define CAPTIO1CTL_L                                       (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
109 #define CAPTIO1CTL_H                                       (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
110 
111 /******************************************************************************
112 * COMP_E0 Registers
113 ******************************************************************************/
114 #define CE0CTL0                                  (HWREG16(0x40003400))           /*!< Comparator Control Register 0 */
115 #define CE0CTL1                                  (HWREG16(0x40003402))           /*!< Comparator Control Register 1 */
116 #define CE0CTL2                                  (HWREG16(0x40003404))           /*!< Comparator Control Register 2 */
117 #define CE0CTL3                                  (HWREG16(0x40003406))           /*!< Comparator Control Register 3 */
118 #define CE0INT                                   (HWREG16(0x4000340C))           /*!< Comparator Interrupt Control Register */
119 #define CE0IV                                    (HWREG16(0x4000340E))           /*!< Comparator Interrupt Vector Word Register */
120 
121 /* Register offsets from COMP_E0_BASE address */
122 #define OFS_CE0CTL0                                        (0x0000)              /*!< Comparator Control Register 0 */
123 #define OFS_CE0CTL1                                        (0x0002)              /*!< Comparator Control Register 1 */
124 #define OFS_CE0CTL2                                        (0x0004)              /*!< Comparator Control Register 2 */
125 #define OFS_CE0CTL3                                        (0x0006)              /*!< Comparator Control Register 3 */
126 #define OFS_CE0INT                                         (0x000C)              /*!< Comparator Interrupt Control Register */
127 #define OFS_CE0IV                                          (0x000E)              /*!< Comparator Interrupt Vector Word Register */
128 
129 
130 /******************************************************************************
131 * COMP_E1 Registers
132 ******************************************************************************/
133 #define CE1CTL0                                  (HWREG16(0x40003800))           /*!< Comparator Control Register 0 */
134 #define CE1CTL1                                  (HWREG16(0x40003802))           /*!< Comparator Control Register 1 */
135 #define CE1CTL2                                  (HWREG16(0x40003804))           /*!< Comparator Control Register 2 */
136 #define CE1CTL3                                  (HWREG16(0x40003806))           /*!< Comparator Control Register 3 */
137 #define CE1INT                                   (HWREG16(0x4000380C))           /*!< Comparator Interrupt Control Register */
138 #define CE1IV                                    (HWREG16(0x4000380E))           /*!< Comparator Interrupt Vector Word Register */
139 
140 /* Register offsets from COMP_E1_BASE address */
141 #define OFS_CE1CTL0                                        (0x0000)              /*!< Comparator Control Register 0 */
142 #define OFS_CE1CTL1                                        (0x0002)              /*!< Comparator Control Register 1 */
143 #define OFS_CE1CTL2                                        (0x0004)              /*!< Comparator Control Register 2 */
144 #define OFS_CE1CTL3                                        (0x0006)              /*!< Comparator Control Register 3 */
145 #define OFS_CE1INT                                         (0x000C)              /*!< Comparator Interrupt Control Register */
146 #define OFS_CE1IV                                          (0x000E)              /*!< Comparator Interrupt Vector Word Register */
147 
148 
149 /******************************************************************************
150 * CRC32 Registers
151 ******************************************************************************/
152 #define CRC32DI                                  (HWREG16(0x40004000))           /*!< Data Input for CRC32 Signature Computation */
153 #define CRC32DIRB                                (HWREG16(0x40004004))           /*!< Data In Reverse for CRC32 Computation */
154 #define CRC32INIRES_LO                           (HWREG16(0x40004008))           /*!< CRC32 Initialization and Result, lower 16 bits */
155 #define CRC32INIRES_HI                           (HWREG16(0x4000400A))           /*!< CRC32 Initialization and Result, upper 16 bits */
156 #define CRC32RESR_LO                             (HWREG16(0x4000400C))           /*!< CRC32 Result Reverse, lower 16 bits */
157 #define CRC32RESR_HI                             (HWREG16(0x4000400E))           /*!< CRC32 Result Reverse, Upper 16 bits */
158 #define CRC16DI                                  (HWREG16(0x40004010))           /*!< Data Input for CRC16 computation */
159 #define CRC16DIRB                                (HWREG16(0x40004014))           /*!< CRC16 Data In Reverse */
160 #define CRC16INIRES                              (HWREG16(0x40004018))           /*!< CRC16 Initialization and Result register */
161 #define CRC16RESR                                (HWREG16(0x4000401E))           /*!< CRC16 Result Reverse */
162 
163 /* Register offsets from CRC32_BASE address */
164 #define OFS_CRC32DI                                        (0x0000)              /*!< Data Input for CRC32 Signature Computation */
165 #define OFS_CRC32DIRB                                      (0x0004)              /*!< Data In Reverse for CRC32 Computation */
166 #define OFS_CRC32INIRES_LO                                 (0x0008)              /*!< CRC32 Initialization and Result, lower 16 bits */
167 #define OFS_CRC32INIRES_HI                                 (0x000A)              /*!< CRC32 Initialization and Result, upper 16 bits */
168 #define OFS_CRC32RESR_LO                                   (0x000C)              /*!< CRC32 Result Reverse, lower 16 bits */
169 #define OFS_CRC32RESR_HI                                   (0x000E)              /*!< CRC32 Result Reverse, Upper 16 bits */
170 #define OFS_CRC16DI                                        (0x0010)              /*!< Data Input for CRC16 computation */
171 #define OFS_CRC16DIRB                                      (0x0014)              /*!< CRC16 Data In Reverse */
172 #define OFS_CRC16INIRES                                    (0x0018)              /*!< CRC16 Initialization and Result register */
173 #define OFS_CRC16RESR                                      (0x001E)              /*!< CRC16 Result Reverse */
174 
175 
176 /******************************************************************************
177 * DIO Registers
178 ******************************************************************************/
179 #define PAIN                                     (HWREG16(0x40004C00))           /*!< Port A Input */
180 #define PAOUT                                    (HWREG16(0x40004C02))           /*!< Port A Output */
181 #define PADIR                                    (HWREG16(0x40004C04))           /*!< Port A Direction */
182 #define PAREN                                    (HWREG16(0x40004C06))           /*!< Port A Resistor Enable */
183 #define PADS                                     (HWREG16(0x40004C08))           /*!< Port A Drive Strength */
184 #define PASEL0                                   (HWREG16(0x40004C0A))           /*!< Port A Select 0 */
185 #define PASEL1                                   (HWREG16(0x40004C0C))           /*!< Port A Select 1 */
186 #define P1IV                                     (HWREG16(0x40004C0E))           /*!< Port 1 Interrupt Vector Register */
187 #define PASELC                                   (HWREG16(0x40004C16))           /*!< Port A Complement Select */
188 #define PAIES                                    (HWREG16(0x40004C18))           /*!< Port A Interrupt Edge Select */
189 #define PAIE                                     (HWREG16(0x40004C1A))           /*!< Port A Interrupt Enable */
190 #define PAIFG                                    (HWREG16(0x40004C1C))           /*!< Port A Interrupt Flag */
191 #define P2IV                                     (HWREG16(0x40004C1E))           /*!< Port 2 Interrupt Vector Register */
192 #define PBIN                                     (HWREG16(0x40004C20))           /*!< Port B Input */
193 #define PBOUT                                    (HWREG16(0x40004C22))           /*!< Port B Output */
194 #define PBDIR                                    (HWREG16(0x40004C24))           /*!< Port B Direction */
195 #define PBREN                                    (HWREG16(0x40004C26))           /*!< Port B Resistor Enable */
196 #define PBDS                                     (HWREG16(0x40004C28))           /*!< Port B Drive Strength */
197 #define PBSEL0                                   (HWREG16(0x40004C2A))           /*!< Port B Select 0 */
198 #define PBSEL1                                   (HWREG16(0x40004C2C))           /*!< Port B Select 1 */
199 #define P3IV                                     (HWREG16(0x40004C2E))           /*!< Port 3 Interrupt Vector Register */
200 #define PBSELC                                   (HWREG16(0x40004C36))           /*!< Port B Complement Select */
201 #define PBIES                                    (HWREG16(0x40004C38))           /*!< Port B Interrupt Edge Select */
202 #define PBIE                                     (HWREG16(0x40004C3A))           /*!< Port B Interrupt Enable */
203 #define PBIFG                                    (HWREG16(0x40004C3C))           /*!< Port B Interrupt Flag */
204 #define P4IV                                     (HWREG16(0x40004C3E))           /*!< Port 4 Interrupt Vector Register */
205 #define PCIN                                     (HWREG16(0x40004C40))           /*!< Port C Input */
206 #define PCOUT                                    (HWREG16(0x40004C42))           /*!< Port C Output */
207 #define PCDIR                                    (HWREG16(0x40004C44))           /*!< Port C Direction */
208 #define PCREN                                    (HWREG16(0x40004C46))           /*!< Port C Resistor Enable */
209 #define PCDS                                     (HWREG16(0x40004C48))           /*!< Port C Drive Strength */
210 #define PCSEL0                                   (HWREG16(0x40004C4A))           /*!< Port C Select 0 */
211 #define PCSEL1                                   (HWREG16(0x40004C4C))           /*!< Port C Select 1 */
212 #define P5IV                                     (HWREG16(0x40004C4E))           /*!< Port 5 Interrupt Vector Register */
213 #define PCSELC                                   (HWREG16(0x40004C56))           /*!< Port C Complement Select */
214 #define PCIES                                    (HWREG16(0x40004C58))           /*!< Port C Interrupt Edge Select */
215 #define PCIE                                     (HWREG16(0x40004C5A))           /*!< Port C Interrupt Enable */
216 #define PCIFG                                    (HWREG16(0x40004C5C))           /*!< Port C Interrupt Flag */
217 #define P6IV                                     (HWREG16(0x40004C5E))           /*!< Port 6 Interrupt Vector Register */
218 #define PDIN                                     (HWREG16(0x40004C60))           /*!< Port D Input */
219 #define PDOUT                                    (HWREG16(0x40004C62))           /*!< Port D Output */
220 #define PDDIR                                    (HWREG16(0x40004C64))           /*!< Port D Direction */
221 #define PDREN                                    (HWREG16(0x40004C66))           /*!< Port D Resistor Enable */
222 #define PDDS                                     (HWREG16(0x40004C68))           /*!< Port D Drive Strength */
223 #define PDSEL0                                   (HWREG16(0x40004C6A))           /*!< Port D Select 0 */
224 #define PDSEL1                                   (HWREG16(0x40004C6C))           /*!< Port D Select 1 */
225 #define P7IV                                     (HWREG16(0x40004C6E))           /*!< Port 7 Interrupt Vector Register */
226 #define PDSELC                                   (HWREG16(0x40004C76))           /*!< Port D Complement Select */
227 #define PDIES                                    (HWREG16(0x40004C78))           /*!< Port D Interrupt Edge Select */
228 #define PDIE                                     (HWREG16(0x40004C7A))           /*!< Port D Interrupt Enable */
229 #define PDIFG                                    (HWREG16(0x40004C7C))           /*!< Port D Interrupt Flag */
230 #define P8IV                                     (HWREG16(0x40004C7E))           /*!< Port 8 Interrupt Vector Register */
231 #define PEIN                                     (HWREG16(0x40004C80))           /*!< Port E Input */
232 #define PEOUT                                    (HWREG16(0x40004C82))           /*!< Port E Output */
233 #define PEDIR                                    (HWREG16(0x40004C84))           /*!< Port E Direction */
234 #define PEREN                                    (HWREG16(0x40004C86))           /*!< Port E Resistor Enable */
235 #define PEDS                                     (HWREG16(0x40004C88))           /*!< Port E Drive Strength */
236 #define PESEL0                                   (HWREG16(0x40004C8A))           /*!< Port E Select 0 */
237 #define PESEL1                                   (HWREG16(0x40004C8C))           /*!< Port E Select 1 */
238 #define P9IV                                     (HWREG16(0x40004C8E))           /*!< Port 9 Interrupt Vector Register */
239 #define PESELC                                   (HWREG16(0x40004C96))           /*!< Port E Complement Select */
240 #define PEIES                                    (HWREG16(0x40004C98))           /*!< Port E Interrupt Edge Select */
241 #define PEIE                                     (HWREG16(0x40004C9A))           /*!< Port E Interrupt Enable */
242 #define PEIFG                                    (HWREG16(0x40004C9C))           /*!< Port E Interrupt Flag */
243 #define P10IV                                    (HWREG16(0x40004C9E))           /*!< Port 10 Interrupt Vector Register */
244 #define PJIN                                     (HWREG16(0x40004D20))           /*!< Port J Input */
245 #define PJOUT                                    (HWREG16(0x40004D22))           /*!< Port J Output */
246 #define PJDIR                                    (HWREG16(0x40004D24))           /*!< Port J Direction */
247 #define PJREN                                    (HWREG16(0x40004D26))           /*!< Port J Resistor Enable */
248 #define PJDS                                     (HWREG16(0x40004D28))           /*!< Port J Drive Strength */
249 #define PJSEL0                                   (HWREG16(0x40004D2A))           /*!< Port J Select 0 */
250 #define PJSEL1                                   (HWREG16(0x40004D2C))           /*!< Port J Select 1 */
251 #define PJSELC                                   (HWREG16(0x40004D36))           /*!< Port J Complement Select */
252 #define P1IN                                     (HWREG8(0x40004C00))            /*!< Port 1 Input */
253 #define P2IN                                     (HWREG8(0x40004C01))            /*!< Port 2 Input */
254 #define P2OUT                                    (HWREG8(0x40004C03))            /*!< Port 2 Output */
255 #define P1OUT                                    (HWREG8(0x40004C02))            /*!< Port 1 Output */
256 #define P1DIR                                    (HWREG8(0x40004C04))            /*!< Port 1 Direction */
257 #define P2DIR                                    (HWREG8(0x40004C05))            /*!< Port 2 Direction */
258 #define P1REN                                    (HWREG8(0x40004C06))            /*!< Port 1 Resistor Enable */
259 #define P2REN                                    (HWREG8(0x40004C07))            /*!< Port 2 Resistor Enable */
260 #define P1DS                                     (HWREG8(0x40004C08))            /*!< Port 1 Drive Strength */
261 #define P2DS                                     (HWREG8(0x40004C09))            /*!< Port 2 Drive Strength */
262 #define P1SEL0                                   (HWREG8(0x40004C0A))            /*!< Port 1 Select 0 */
263 #define P2SEL0                                   (HWREG8(0x40004C0B))            /*!< Port 2 Select 0 */
264 #define P1SEL1                                   (HWREG8(0x40004C0C))            /*!< Port 1 Select 1 */
265 #define P2SEL1                                   (HWREG8(0x40004C0D))            /*!< Port 2 Select 1 */
266 #define P1SELC                                   (HWREG8(0x40004C16))            /*!< Port 1 Complement Select */
267 #define P2SELC                                   (HWREG8(0x40004C17))            /*!< Port 2 Complement Select */
268 #define P1IES                                    (HWREG8(0x40004C18))            /*!< Port 1 Interrupt Edge Select */
269 #define P2IES                                    (HWREG8(0x40004C19))            /*!< Port 2 Interrupt Edge Select */
270 #define P1IE                                     (HWREG8(0x40004C1A))            /*!< Port 1 Interrupt Enable */
271 #define P2IE                                     (HWREG8(0x40004C1B))            /*!< Port 2 Interrupt Enable */
272 #define P1IFG                                    (HWREG8(0x40004C1C))            /*!< Port 1 Interrupt Flag */
273 #define P2IFG                                    (HWREG8(0x40004C1D))            /*!< Port 2 Interrupt Flag */
274 #define P3IN                                     (HWREG8(0x40004C20))            /*!< Port 3 Input */
275 #define P4IN                                     (HWREG8(0x40004C21))            /*!< Port 4 Input */
276 #define P3OUT                                    (HWREG8(0x40004C22))            /*!< Port 3 Output */
277 #define P4OUT                                    (HWREG8(0x40004C23))            /*!< Port 4 Output */
278 #define P3DIR                                    (HWREG8(0x40004C24))            /*!< Port 3 Direction */
279 #define P4DIR                                    (HWREG8(0x40004C25))            /*!< Port 4 Direction */
280 #define P3REN                                    (HWREG8(0x40004C26))            /*!< Port 3 Resistor Enable */
281 #define P4REN                                    (HWREG8(0x40004C27))            /*!< Port 4 Resistor Enable */
282 #define P3DS                                     (HWREG8(0x40004C28))            /*!< Port 3 Drive Strength */
283 #define P4DS                                     (HWREG8(0x40004C29))            /*!< Port 4 Drive Strength */
284 #define P4SEL0                                   (HWREG8(0x40004C2B))            /*!< Port 4 Select 0 */
285 #define P3SEL0                                   (HWREG8(0x40004C2A))            /*!< Port 3 Select 0 */
286 #define P3SEL1                                   (HWREG8(0x40004C2C))            /*!< Port 3 Select 1 */
287 #define P4SEL1                                   (HWREG8(0x40004C2D))            /*!< Port 4 Select 1 */
288 #define P3SELC                                   (HWREG8(0x40004C36))            /*!< Port 3 Complement Select */
289 #define P4SELC                                   (HWREG8(0x40004C37))            /*!< Port 4 Complement Select */
290 #define P3IES                                    (HWREG8(0x40004C38))            /*!< Port 3 Interrupt Edge Select */
291 #define P4IES                                    (HWREG8(0x40004C39))            /*!< Port 4 Interrupt Edge Select */
292 #define P3IE                                     (HWREG8(0x40004C3A))            /*!< Port 3 Interrupt Enable */
293 #define P4IE                                     (HWREG8(0x40004C3B))            /*!< Port 4 Interrupt Enable */
294 #define P3IFG                                    (HWREG8(0x40004C3C))            /*!< Port 3 Interrupt Flag */
295 #define P4IFG                                    (HWREG8(0x40004C3D))            /*!< Port 4 Interrupt Flag */
296 #define P5IN                                     (HWREG8(0x40004C40))            /*!< Port 5 Input */
297 #define P6IN                                     (HWREG8(0x40004C41))            /*!< Port 6 Input */
298 #define P5OUT                                    (HWREG8(0x40004C42))            /*!< Port 5 Output */
299 #define P6OUT                                    (HWREG8(0x40004C43))            /*!< Port 6 Output */
300 #define P5DIR                                    (HWREG8(0x40004C44))            /*!< Port 5 Direction */
301 #define P6DIR                                    (HWREG8(0x40004C45))            /*!< Port 6 Direction */
302 #define P5REN                                    (HWREG8(0x40004C46))            /*!< Port 5 Resistor Enable */
303 #define P6REN                                    (HWREG8(0x40004C47))            /*!< Port 6 Resistor Enable */
304 #define P5DS                                     (HWREG8(0x40004C48))            /*!< Port 5 Drive Strength */
305 #define P6DS                                     (HWREG8(0x40004C49))            /*!< Port 6 Drive Strength */
306 #define P5SEL0                                   (HWREG8(0x40004C4A))            /*!< Port 5 Select 0 */
307 #define P6SEL0                                   (HWREG8(0x40004C4B))            /*!< Port 6 Select 0 */
308 #define P5SEL1                                   (HWREG8(0x40004C4C))            /*!< Port 5 Select 1 */
309 #define P6SEL1                                   (HWREG8(0x40004C4D))            /*!< Port 6 Select 1 */
310 #define P5SELC                                   (HWREG8(0x40004C56))            /*!< Port 5 Complement Select */
311 #define P6SELC                                   (HWREG8(0x40004C57))            /*!< Port 6 Complement Select */
312 #define P5IES                                    (HWREG8(0x40004C58))            /*!< Port 5 Interrupt Edge Select */
313 #define P6IES                                    (HWREG8(0x40004C59))            /*!< Port 6 Interrupt Edge Select */
314 #define P5IE                                     (HWREG8(0x40004C5A))            /*!< Port 5 Interrupt Enable */
315 #define P6IE                                     (HWREG8(0x40004C5B))            /*!< Port 6 Interrupt Enable */
316 #define P5IFG                                    (HWREG8(0x40004C5C))            /*!< Port 5 Interrupt Flag */
317 #define P6IFG                                    (HWREG8(0x40004C5D))            /*!< Port 6 Interrupt Flag */
318 #define P7IN                                     (HWREG8(0x40004C60))            /*!< Port 7 Input */
319 #define P8IN                                     (HWREG8(0x40004C61))            /*!< Port 8 Input */
320 #define P7OUT                                    (HWREG8(0x40004C62))            /*!< Port 7 Output */
321 #define P8OUT                                    (HWREG8(0x40004C63))            /*!< Port 8 Output */
322 #define P7DIR                                    (HWREG8(0x40004C64))            /*!< Port 7 Direction */
323 #define P8DIR                                    (HWREG8(0x40004C65))            /*!< Port 8 Direction */
324 #define P7REN                                    (HWREG8(0x40004C66))            /*!< Port 7 Resistor Enable */
325 #define P8REN                                    (HWREG8(0x40004C67))            /*!< Port 8 Resistor Enable */
326 #define P7DS                                     (HWREG8(0x40004C68))            /*!< Port 7 Drive Strength */
327 #define P8DS                                     (HWREG8(0x40004C69))            /*!< Port 8 Drive Strength */
328 #define P7SEL0                                   (HWREG8(0x40004C6A))            /*!< Port 7 Select 0 */
329 #define P8SEL0                                   (HWREG8(0x40004C6B))            /*!< Port 8 Select 0 */
330 #define P7SEL1                                   (HWREG8(0x40004C6C))            /*!< Port 7 Select 1 */
331 #define P8SEL1                                   (HWREG8(0x40004C6D))            /*!< Port 8 Select 1 */
332 #define P7SELC                                   (HWREG8(0x40004C76))            /*!< Port 7 Complement Select */
333 #define P8SELC                                   (HWREG8(0x40004C77))            /*!< Port 8 Complement Select */
334 #define P7IES                                    (HWREG8(0x40004C78))            /*!< Port 7 Interrupt Edge Select */
335 #define P8IES                                    (HWREG8(0x40004C79))            /*!< Port 8 Interrupt Edge Select */
336 #define P7IE                                     (HWREG8(0x40004C7A))            /*!< Port 7 Interrupt Enable */
337 #define P8IE                                     (HWREG8(0x40004C7B))            /*!< Port 8 Interrupt Enable */
338 #define P7IFG                                    (HWREG8(0x40004C7C))            /*!< Port 7 Interrupt Flag */
339 #define P8IFG                                    (HWREG8(0x40004C7D))            /*!< Port 8 Interrupt Flag */
340 #define P9IN                                     (HWREG8(0x40004C80))            /*!< Port 9 Input */
341 #define P10IN                                    (HWREG8(0x40004C81))            /*!< Port 10 Input */
342 #define P9OUT                                    (HWREG8(0x40004C82))            /*!< Port 9 Output */
343 #define P10OUT                                   (HWREG8(0x40004C83))            /*!< Port 10 Output */
344 #define P9DIR                                    (HWREG8(0x40004C84))            /*!< Port 9 Direction */
345 #define P10DIR                                   (HWREG8(0x40004C85))            /*!< Port 10 Direction */
346 #define P9REN                                    (HWREG8(0x40004C86))            /*!< Port 9 Resistor Enable */
347 #define P10REN                                   (HWREG8(0x40004C87))            /*!< Port 10 Resistor Enable */
348 #define P9DS                                     (HWREG8(0x40004C88))            /*!< Port 9 Drive Strength */
349 #define P10DS                                    (HWREG8(0x40004C89))            /*!< Port 10 Drive Strength */
350 #define P9SEL0                                   (HWREG8(0x40004C8A))            /*!< Port 9 Select 0 */
351 #define P10SEL0                                  (HWREG8(0x40004C8B))            /*!< Port 10 Select 0 */
352 #define P9SEL1                                   (HWREG8(0x40004C8C))            /*!< Port 9 Select 1 */
353 #define P10SEL1                                  (HWREG8(0x40004C8D))            /*!< Port 10 Select 1 */
354 #define P9SELC                                   (HWREG8(0x40004C96))            /*!< Port 9 Complement Select */
355 #define P10SELC                                  (HWREG8(0x40004C97))            /*!< Port 10 Complement Select */
356 #define P9IES                                    (HWREG8(0x40004C98))            /*!< Port 9 Interrupt Edge Select */
357 #define P10IES                                   (HWREG8(0x40004C99))            /*!< Port 10 Interrupt Edge Select */
358 #define P9IE                                     (HWREG8(0x40004C9A))            /*!< Port 9 Interrupt Enable */
359 #define P10IE                                    (HWREG8(0x40004C9B))            /*!< Port 10 Interrupt Enable */
360 #define P9IFG                                    (HWREG8(0x40004C9C))            /*!< Port 9 Interrupt Flag */
361 #define P10IFG                                   (HWREG8(0x40004C9D))            /*!< Port 10 Interrupt Flag */
362 
363 /* Register offsets from DIO_BASE address */
364 #define OFS_PAIN                                           (0x0000)              /*!< Port A Input */
365 #define OFS_PAOUT                                          (0x0002)              /*!< Port A Output */
366 #define OFS_PADIR                                          (0x0004)              /*!< Port A Direction */
367 #define OFS_PAREN                                          (0x0006)              /*!< Port A Resistor Enable */
368 #define OFS_PADS                                           (0x0008)              /*!< Port A Drive Strength */
369 #define OFS_PASEL0                                         (0x000A)              /*!< Port A Select 0 */
370 #define OFS_PASEL1                                         (0x000C)              /*!< Port A Select 1 */
371 #define OFS_P1IV                                           (0x000E)              /*!< Port 1 Interrupt Vector Register */
372 #define OFS_PASELC                                         (0x0016)              /*!< Port A Complement Select */
373 #define OFS_PAIES                                          (0x0018)              /*!< Port A Interrupt Edge Select */
374 #define OFS_PAIE                                           (0x001A)              /*!< Port A Interrupt Enable */
375 #define OFS_PAIFG                                          (0x001C)              /*!< Port A Interrupt Flag */
376 #define OFS_P2IV                                           (0x001E)              /*!< Port 2 Interrupt Vector Register */
377 #define OFS_PBIN                                           (0x0020)              /*!< Port B Input */
378 #define OFS_PBOUT                                          (0x0022)              /*!< Port B Output */
379 #define OFS_PBDIR                                          (0x0024)              /*!< Port B Direction */
380 #define OFS_PBREN                                          (0x0026)              /*!< Port B Resistor Enable */
381 #define OFS_PBDS                                           (0x0028)              /*!< Port B Drive Strength */
382 #define OFS_PBSEL0                                         (0x002A)              /*!< Port B Select 0 */
383 #define OFS_PBSEL1                                         (0x002C)              /*!< Port B Select 1 */
384 #define OFS_P3IV                                           (0x002E)              /*!< Port 3 Interrupt Vector Register */
385 #define OFS_PBSELC                                         (0x0036)              /*!< Port B Complement Select */
386 #define OFS_PBIES                                          (0x0038)              /*!< Port B Interrupt Edge Select */
387 #define OFS_PBIE                                           (0x003A)              /*!< Port B Interrupt Enable */
388 #define OFS_PBIFG                                          (0x003C)              /*!< Port B Interrupt Flag */
389 #define OFS_P4IV                                           (0x003E)              /*!< Port 4 Interrupt Vector Register */
390 #define OFS_PCIN                                           (0x0040)              /*!< Port C Input */
391 #define OFS_PCOUT                                          (0x0042)              /*!< Port C Output */
392 #define OFS_PCDIR                                          (0x0044)              /*!< Port C Direction */
393 #define OFS_PCREN                                          (0x0046)              /*!< Port C Resistor Enable */
394 #define OFS_PCDS                                           (0x0048)              /*!< Port C Drive Strength */
395 #define OFS_PCSEL0                                         (0x004A)              /*!< Port C Select 0 */
396 #define OFS_PCSEL1                                         (0x004C)              /*!< Port C Select 1 */
397 #define OFS_P5IV                                           (0x004E)              /*!< Port 5 Interrupt Vector Register */
398 #define OFS_PCSELC                                         (0x0056)              /*!< Port C Complement Select */
399 #define OFS_PCIES                                          (0x0058)              /*!< Port C Interrupt Edge Select */
400 #define OFS_PCIE                                           (0x005A)              /*!< Port C Interrupt Enable */
401 #define OFS_PCIFG                                          (0x005C)              /*!< Port C Interrupt Flag */
402 #define OFS_P6IV                                           (0x005E)              /*!< Port 6 Interrupt Vector Register */
403 #define OFS_PDIN                                           (0x0060)              /*!< Port D Input */
404 #define OFS_PDOUT                                          (0x0062)              /*!< Port D Output */
405 #define OFS_PDDIR                                          (0x0064)              /*!< Port D Direction */
406 #define OFS_PDREN                                          (0x0066)              /*!< Port D Resistor Enable */
407 #define OFS_PDDS                                           (0x0068)              /*!< Port D Drive Strength */
408 #define OFS_PDSEL0                                         (0x006A)              /*!< Port D Select 0 */
409 #define OFS_PDSEL1                                         (0x006C)              /*!< Port D Select 1 */
410 #define OFS_P7IV                                           (0x006E)              /*!< Port 7 Interrupt Vector Register */
411 #define OFS_PDSELC                                         (0x0076)              /*!< Port D Complement Select */
412 #define OFS_PDIES                                          (0x0078)              /*!< Port D Interrupt Edge Select */
413 #define OFS_PDIE                                           (0x007A)              /*!< Port D Interrupt Enable */
414 #define OFS_PDIFG                                          (0x007C)              /*!< Port D Interrupt Flag */
415 #define OFS_P8IV                                           (0x007E)              /*!< Port 8 Interrupt Vector Register */
416 #define OFS_PEIN                                           (0x0080)              /*!< Port E Input */
417 #define OFS_PEOUT                                          (0x0082)              /*!< Port E Output */
418 #define OFS_PEDIR                                          (0x0084)              /*!< Port E Direction */
419 #define OFS_PEREN                                          (0x0086)              /*!< Port E Resistor Enable */
420 #define OFS_PEDS                                           (0x0088)              /*!< Port E Drive Strength */
421 #define OFS_PESEL0                                         (0x008A)              /*!< Port E Select 0 */
422 #define OFS_PESEL1                                         (0x008C)              /*!< Port E Select 1 */
423 #define OFS_P9IV                                           (0x008E)              /*!< Port 9 Interrupt Vector Register */
424 #define OFS_PESELC                                         (0x0096)              /*!< Port E Complement Select */
425 #define OFS_PEIES                                          (0x0098)              /*!< Port E Interrupt Edge Select */
426 #define OFS_PEIE                                           (0x009A)              /*!< Port E Interrupt Enable */
427 #define OFS_PEIFG                                          (0x009C)              /*!< Port E Interrupt Flag */
428 #define OFS_P10IV                                          (0x009E)              /*!< Port 10 Interrupt Vector Register */
429 #define OFS_PJIN                                           (0x0120)              /*!< Port J Input */
430 #define OFS_PJOUT                                          (0x0122)              /*!< Port J Output */
431 #define OFS_PJDIR                                          (0x0124)              /*!< Port J Direction */
432 #define OFS_PJREN                                          (0x0126)              /*!< Port J Resistor Enable */
433 #define OFS_PJDS                                           (0x0128)              /*!< Port J Drive Strength */
434 #define OFS_PJSEL0                                         (0x012A)              /*!< Port J Select 0 */
435 #define OFS_PJSEL1                                         (0x012C)              /*!< Port J Select 1 */
436 #define OFS_PJSELC                                         (0x0136)              /*!< Port J Complement Select */
437 #define OFS_P1IN                                           (0x0000)              /*!< Port 1 Input */
438 #define OFS_P2IN                                           (0x0001)              /*!< Port 2 Input */
439 #define OFS_P2OUT                                          (0x0003)              /*!< Port 2 Output */
440 #define OFS_P1OUT                                          (0x0002)              /*!< Port 1 Output */
441 #define OFS_P1DIR                                          (0x0004)              /*!< Port 1 Direction */
442 #define OFS_P2DIR                                          (0x0005)              /*!< Port 2 Direction */
443 #define OFS_P1REN                                          (0x0006)              /*!< Port 1 Resistor Enable */
444 #define OFS_P2REN                                          (0x0007)              /*!< Port 2 Resistor Enable */
445 #define OFS_P1DS                                           (0x0008)              /*!< Port 1 Drive Strength */
446 #define OFS_P2DS                                           (0x0009)              /*!< Port 2 Drive Strength */
447 #define OFS_P1SEL0                                         (0x000A)              /*!< Port 1 Select 0 */
448 #define OFS_P2SEL0                                         (0x000B)              /*!< Port 2 Select 0 */
449 #define OFS_P1SEL1                                         (0x000C)              /*!< Port 1 Select 1 */
450 #define OFS_P2SEL1                                         (0x000D)              /*!< Port 2 Select 1 */
451 #define OFS_P1SELC                                         (0x0016)              /*!< Port 1 Complement Select */
452 #define OFS_P2SELC                                         (0x0017)              /*!< Port 2 Complement Select */
453 #define OFS_P1IES                                          (0x0018)              /*!< Port 1 Interrupt Edge Select */
454 #define OFS_P2IES                                          (0x0019)              /*!< Port 2 Interrupt Edge Select */
455 #define OFS_P1IE                                           (0x001A)              /*!< Port 1 Interrupt Enable */
456 #define OFS_P2IE                                           (0x001B)              /*!< Port 2 Interrupt Enable */
457 #define OFS_P1IFG                                          (0x001C)              /*!< Port 1 Interrupt Flag */
458 #define OFS_P2IFG                                          (0x001D)              /*!< Port 2 Interrupt Flag */
459 #define OFS_P3IN                                           (0x0020)              /*!< Port 3 Input */
460 #define OFS_P4IN                                           (0x0021)              /*!< Port 4 Input */
461 #define OFS_P3OUT                                          (0x0022)              /*!< Port 3 Output */
462 #define OFS_P4OUT                                          (0x0023)              /*!< Port 4 Output */
463 #define OFS_P3DIR                                          (0x0024)              /*!< Port 3 Direction */
464 #define OFS_P4DIR                                          (0x0025)              /*!< Port 4 Direction */
465 #define OFS_P3REN                                          (0x0026)              /*!< Port 3 Resistor Enable */
466 #define OFS_P4REN                                          (0x0027)              /*!< Port 4 Resistor Enable */
467 #define OFS_P3DS                                           (0x0028)              /*!< Port 3 Drive Strength */
468 #define OFS_P4DS                                           (0x0029)              /*!< Port 4 Drive Strength */
469 #define OFS_P4SEL0                                         (0x002B)              /*!< Port 4 Select 0 */
470 #define OFS_P3SEL0                                         (0x002A)              /*!< Port 3 Select 0 */
471 #define OFS_P3SEL1                                         (0x002C)              /*!< Port 3 Select 1 */
472 #define OFS_P4SEL1                                         (0x002D)              /*!< Port 4 Select 1 */
473 #define OFS_P3SELC                                         (0x0036)              /*!< Port 3 Complement Select */
474 #define OFS_P4SELC                                         (0x0037)              /*!< Port 4 Complement Select */
475 #define OFS_P3IES                                          (0x0038)              /*!< Port 3 Interrupt Edge Select */
476 #define OFS_P4IES                                          (0x0039)              /*!< Port 4 Interrupt Edge Select */
477 #define OFS_P3IE                                           (0x003A)              /*!< Port 3 Interrupt Enable */
478 #define OFS_P4IE                                           (0x003B)              /*!< Port 4 Interrupt Enable */
479 #define OFS_P3IFG                                          (0x003C)              /*!< Port 3 Interrupt Flag */
480 #define OFS_P4IFG                                          (0x003D)              /*!< Port 4 Interrupt Flag */
481 #define OFS_P5IN                                           (0x0040)              /*!< Port 5 Input */
482 #define OFS_P6IN                                           (0x0041)              /*!< Port 6 Input */
483 #define OFS_P5OUT                                          (0x0042)              /*!< Port 5 Output */
484 #define OFS_P6OUT                                          (0x0043)              /*!< Port 6 Output */
485 #define OFS_P5DIR                                          (0x0044)              /*!< Port 5 Direction */
486 #define OFS_P6DIR                                          (0x0045)              /*!< Port 6 Direction */
487 #define OFS_P5REN                                          (0x0046)              /*!< Port 5 Resistor Enable */
488 #define OFS_P6REN                                          (0x0047)              /*!< Port 6 Resistor Enable */
489 #define OFS_P5DS                                           (0x0048)              /*!< Port 5 Drive Strength */
490 #define OFS_P6DS                                           (0x0049)              /*!< Port 6 Drive Strength */
491 #define OFS_P5SEL0                                         (0x004A)              /*!< Port 5 Select 0 */
492 #define OFS_P6SEL0                                         (0x004B)              /*!< Port 6 Select 0 */
493 #define OFS_P5SEL1                                         (0x004C)              /*!< Port 5 Select 1 */
494 #define OFS_P6SEL1                                         (0x004D)              /*!< Port 6 Select 1 */
495 #define OFS_P5SELC                                         (0x0056)              /*!< Port 5 Complement Select */
496 #define OFS_P6SELC                                         (0x0057)              /*!< Port 6 Complement Select */
497 #define OFS_P5IES                                          (0x0058)              /*!< Port 5 Interrupt Edge Select */
498 #define OFS_P6IES                                          (0x0059)              /*!< Port 6 Interrupt Edge Select */
499 #define OFS_P5IE                                           (0x005A)              /*!< Port 5 Interrupt Enable */
500 #define OFS_P6IE                                           (0x005B)              /*!< Port 6 Interrupt Enable */
501 #define OFS_P5IFG                                          (0x005C)              /*!< Port 5 Interrupt Flag */
502 #define OFS_P6IFG                                          (0x005D)              /*!< Port 6 Interrupt Flag */
503 #define OFS_P7IN                                           (0x0060)              /*!< Port 7 Input */
504 #define OFS_P8IN                                           (0x0061)              /*!< Port 8 Input */
505 #define OFS_P7OUT                                          (0x0062)              /*!< Port 7 Output */
506 #define OFS_P8OUT                                          (0x0063)              /*!< Port 8 Output */
507 #define OFS_P7DIR                                          (0x0064)              /*!< Port 7 Direction */
508 #define OFS_P8DIR                                          (0x0065)              /*!< Port 8 Direction */
509 #define OFS_P7REN                                          (0x0066)              /*!< Port 7 Resistor Enable */
510 #define OFS_P8REN                                          (0x0067)              /*!< Port 8 Resistor Enable */
511 #define OFS_P7DS                                           (0x0068)              /*!< Port 7 Drive Strength */
512 #define OFS_P8DS                                           (0x0069)              /*!< Port 8 Drive Strength */
513 #define OFS_P7SEL0                                         (0x006A)              /*!< Port 7 Select 0 */
514 #define OFS_P8SEL0                                         (0x006B)              /*!< Port 8 Select 0 */
515 #define OFS_P7SEL1                                         (0x006C)              /*!< Port 7 Select 1 */
516 #define OFS_P8SEL1                                         (0x006D)              /*!< Port 8 Select 1 */
517 #define OFS_P7SELC                                         (0x0076)              /*!< Port 7 Complement Select */
518 #define OFS_P8SELC                                         (0x0077)              /*!< Port 8 Complement Select */
519 #define OFS_P7IES                                          (0x0078)              /*!< Port 7 Interrupt Edge Select */
520 #define OFS_P8IES                                          (0x0079)              /*!< Port 8 Interrupt Edge Select */
521 #define OFS_P7IE                                           (0x007A)              /*!< Port 7 Interrupt Enable */
522 #define OFS_P8IE                                           (0x007B)              /*!< Port 8 Interrupt Enable */
523 #define OFS_P7IFG                                          (0x007C)              /*!< Port 7 Interrupt Flag */
524 #define OFS_P8IFG                                          (0x007D)              /*!< Port 8 Interrupt Flag */
525 #define OFS_P9IN                                           (0x0080)              /*!< Port 9 Input */
526 #define OFS_P10IN                                          (0x0081)              /*!< Port 10 Input */
527 #define OFS_P9OUT                                          (0x0082)              /*!< Port 9 Output */
528 #define OFS_P10OUT                                         (0x0083)              /*!< Port 10 Output */
529 #define OFS_P9DIR                                          (0x0084)              /*!< Port 9 Direction */
530 #define OFS_P10DIR                                         (0x0085)              /*!< Port 10 Direction */
531 #define OFS_P9REN                                          (0x0086)              /*!< Port 9 Resistor Enable */
532 #define OFS_P10REN                                         (0x0087)              /*!< Port 10 Resistor Enable */
533 #define OFS_P9DS                                           (0x0088)              /*!< Port 9 Drive Strength */
534 #define OFS_P10DS                                          (0x0089)              /*!< Port 10 Drive Strength */
535 #define OFS_P9SEL0                                         (0x008A)              /*!< Port 9 Select 0 */
536 #define OFS_P10SEL0                                        (0x008B)              /*!< Port 10 Select 0 */
537 #define OFS_P9SEL1                                         (0x008C)              /*!< Port 9 Select 1 */
538 #define OFS_P10SEL1                                        (0x008D)              /*!< Port 10 Select 1 */
539 #define OFS_P9SELC                                         (0x0096)              /*!< Port 9 Complement Select */
540 #define OFS_P10SELC                                        (0x0097)              /*!< Port 10 Complement Select */
541 #define OFS_P9IES                                          (0x0098)              /*!< Port 9 Interrupt Edge Select */
542 #define OFS_P10IES                                         (0x0099)              /*!< Port 10 Interrupt Edge Select */
543 #define OFS_P9IE                                           (0x009A)              /*!< Port 9 Interrupt Enable */
544 #define OFS_P10IE                                          (0x009B)              /*!< Port 10 Interrupt Enable */
545 #define OFS_P9IFG                                          (0x009C)              /*!< Port 9 Interrupt Flag */
546 #define OFS_P10IFG                                         (0x009D)              /*!< Port 10 Interrupt Flag */
547 
548 
549 /******************************************************************************
550 * EUSCI_A0 Registers
551 ******************************************************************************/
552 #define UCA0CTLW0                                (HWREG16(0x40001000))           /*!< eUSCI_Ax Control Word Register 0 */
553 #define UCA0CTLW0_SPI                            (HWREG16(0x40001000))
554 #define UCA0CTLW1                                (HWREG16(0x40001002))           /*!< eUSCI_Ax Control Word Register 1 */
555 #define UCA0BRW                                  (HWREG16(0x40001006))           /*!< eUSCI_Ax Baud Rate Control Word Register */
556 #define UCA0BRW_SPI                              (HWREG16(0x40001006))
557 #define UCA0MCTLW                                (HWREG16(0x40001008))           /*!< eUSCI_Ax Modulation Control Word Register */
558 #define UCA0STATW                                (HWREG16(0x4000100A))           /*!< eUSCI_Ax Status Register */
559 #define UCA0STATW_SPI                            (HWREG16(0x4000100A))
560 #define UCA0RXBUF                                (HWREG16(0x4000100C))           /*!< eUSCI_Ax Receive Buffer Register */
561 #define UCA0RXBUF_SPI                            (HWREG16(0x4000100C))
562 #define UCA0TXBUF                                (HWREG16(0x4000100E))           /*!< eUSCI_Ax Transmit Buffer Register */
563 #define UCA0TXBUF_SPI                            (HWREG16(0x4000100E))
564 #define UCA0ABCTL                                (HWREG16(0x40001010))           /*!< eUSCI_Ax Auto Baud Rate Control Register */
565 #define UCA0IRCTL                                (HWREG16(0x40001012))           /*!< eUSCI_Ax IrDA Control Word Register */
566 #define UCA0IE                                   (HWREG16(0x4000101A))           /*!< eUSCI_Ax Interrupt Enable Register */
567 #define UCA0IE_SPI                               (HWREG16(0x4000101A))
568 #define UCA0IFG                                  (HWREG16(0x4000101C))           /*!< eUSCI_Ax Interrupt Flag Register */
569 #define UCA0IFG_SPI                              (HWREG16(0x4000101C))
570 #define UCA0IV                                   (HWREG16(0x4000101E))           /*!< eUSCI_Ax Interrupt Vector Register */
571 #define UCA0IV_SPI                               (HWREG16(0x4000101E))
572 
573 /* Register offsets from EUSCI_A0_BASE address */
574 #define OFS_UCA0CTLW0                                      (0x0000)              /*!< eUSCI_Ax Control Word Register 0 */
575 #define OFS_UCA0CTLW0_SPI                                  (0x0000)
576 #define OFS_UCA0CTLW1                                      (0x0002)              /*!< eUSCI_Ax Control Word Register 1 */
577 #define OFS_UCA0BRW                                        (0x0006)              /*!< eUSCI_Ax Baud Rate Control Word Register */
578 #define OFS_UCA0BRW_SPI                                    (0x0006)
579 #define OFS_UCA0MCTLW                                      (0x0008)              /*!< eUSCI_Ax Modulation Control Word Register */
580 #define OFS_UCA0STATW                                      (0x000A)              /*!< eUSCI_Ax Status Register */
581 #define OFS_UCA0STATW_SPI                                  (0x000A)
582 #define OFS_UCA0RXBUF                                      (0x000C)              /*!< eUSCI_Ax Receive Buffer Register */
583 #define OFS_UCA0RXBUF_SPI                                  (0x000C)
584 #define OFS_UCA0TXBUF                                      (0x000E)              /*!< eUSCI_Ax Transmit Buffer Register */
585 #define OFS_UCA0TXBUF_SPI                                  (0x000E)
586 #define OFS_UCA0ABCTL                                      (0x0010)              /*!< eUSCI_Ax Auto Baud Rate Control Register */
587 #define OFS_UCA0IRCTL                                      (0x0012)              /*!< eUSCI_Ax IrDA Control Word Register */
588 #define OFS_UCA0IE                                         (0x001A)              /*!< eUSCI_Ax Interrupt Enable Register */
589 #define OFS_UCA0IE_SPI                                     (0x001A)
590 #define OFS_UCA0IFG                                        (0x001C)              /*!< eUSCI_Ax Interrupt Flag Register */
591 #define OFS_UCA0IFG_SPI                                    (0x001C)
592 #define OFS_UCA0IV                                         (0x001E)              /*!< eUSCI_Ax Interrupt Vector Register */
593 #define OFS_UCA0IV_SPI                                     (0x001E)
594 
595 #define UCA0CTL0                                           (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */
596 #define UCA0CTL1                                           (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */
597 #define UCA0BR0                                            (HWREG8_L(UCA0BRW))   /* eUSCI_Ax Baud Rate Control 0 */
598 #define UCA0BR1                                            (HWREG8_H(UCA0BRW))   /* eUSCI_Ax Baud Rate Control 1 */
599 #define UCA0IRTCTL                                         (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
600 #define UCA0IRRCTL                                         (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */
601 
602 /******************************************************************************
603 * EUSCI_A1 Registers
604 ******************************************************************************/
605 #define UCA1CTLW0                                (HWREG16(0x40001400))           /*!< eUSCI_Ax Control Word Register 0 */
606 #define UCA1CTLW0_SPI                            (HWREG16(0x40001400))
607 #define UCA1CTLW1                                (HWREG16(0x40001402))           /*!< eUSCI_Ax Control Word Register 1 */
608 #define UCA1BRW                                  (HWREG16(0x40001406))           /*!< eUSCI_Ax Baud Rate Control Word Register */
609 #define UCA1BRW_SPI                              (HWREG16(0x40001406))
610 #define UCA1MCTLW                                (HWREG16(0x40001408))           /*!< eUSCI_Ax Modulation Control Word Register */
611 #define UCA1STATW                                (HWREG16(0x4000140A))           /*!< eUSCI_Ax Status Register */
612 #define UCA1STATW_SPI                            (HWREG16(0x4000140A))
613 #define UCA1RXBUF                                (HWREG16(0x4000140C))           /*!< eUSCI_Ax Receive Buffer Register */
614 #define UCA1RXBUF_SPI                            (HWREG16(0x4000140C))
615 #define UCA1TXBUF                                (HWREG16(0x4000140E))           /*!< eUSCI_Ax Transmit Buffer Register */
616 #define UCA1TXBUF_SPI                            (HWREG16(0x4000140E))
617 #define UCA1ABCTL                                (HWREG16(0x40001410))           /*!< eUSCI_Ax Auto Baud Rate Control Register */
618 #define UCA1IRCTL                                (HWREG16(0x40001412))           /*!< eUSCI_Ax IrDA Control Word Register */
619 #define UCA1IE                                   (HWREG16(0x4000141A))           /*!< eUSCI_Ax Interrupt Enable Register */
620 #define UCA1IE_SPI                               (HWREG16(0x4000141A))
621 #define UCA1IFG                                  (HWREG16(0x4000141C))           /*!< eUSCI_Ax Interrupt Flag Register */
622 #define UCA1IFG_SPI                              (HWREG16(0x4000141C))
623 #define UCA1IV                                   (HWREG16(0x4000141E))           /*!< eUSCI_Ax Interrupt Vector Register */
624 #define UCA1IV_SPI                               (HWREG16(0x4000141E))
625 
626 /* Register offsets from EUSCI_A1_BASE address */
627 #define OFS_UCA1CTLW0                                      (0x0000)              /*!< eUSCI_Ax Control Word Register 0 */
628 #define OFS_UCA1CTLW0_SPI                                  (0x0000)
629 #define OFS_UCA1CTLW1                                      (0x0002)              /*!< eUSCI_Ax Control Word Register 1 */
630 #define OFS_UCA1BRW                                        (0x0006)              /*!< eUSCI_Ax Baud Rate Control Word Register */
631 #define OFS_UCA1BRW_SPI                                    (0x0006)
632 #define OFS_UCA1MCTLW                                      (0x0008)              /*!< eUSCI_Ax Modulation Control Word Register */
633 #define OFS_UCA1STATW                                      (0x000A)              /*!< eUSCI_Ax Status Register */
634 #define OFS_UCA1STATW_SPI                                  (0x000A)
635 #define OFS_UCA1RXBUF                                      (0x000C)              /*!< eUSCI_Ax Receive Buffer Register */
636 #define OFS_UCA1RXBUF_SPI                                  (0x000C)
637 #define OFS_UCA1TXBUF                                      (0x000E)              /*!< eUSCI_Ax Transmit Buffer Register */
638 #define OFS_UCA1TXBUF_SPI                                  (0x000E)
639 #define OFS_UCA1ABCTL                                      (0x0010)              /*!< eUSCI_Ax Auto Baud Rate Control Register */
640 #define OFS_UCA1IRCTL                                      (0x0012)              /*!< eUSCI_Ax IrDA Control Word Register */
641 #define OFS_UCA1IE                                         (0x001A)              /*!< eUSCI_Ax Interrupt Enable Register */
642 #define OFS_UCA1IE_SPI                                     (0x001A)
643 #define OFS_UCA1IFG                                        (0x001C)              /*!< eUSCI_Ax Interrupt Flag Register */
644 #define OFS_UCA1IFG_SPI                                    (0x001C)
645 #define OFS_UCA1IV                                         (0x001E)              /*!< eUSCI_Ax Interrupt Vector Register */
646 #define OFS_UCA1IV_SPI                                     (0x001E)
647 
648 #define UCA1CTL0                                           (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */
649 #define UCA1CTL1                                           (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */
650 #define UCA1BR0                                            (HWREG8_L(UCA1BRW))   /* eUSCI_Ax Baud Rate Control 0 */
651 #define UCA1BR1                                            (HWREG8_H(UCA1BRW))   /* eUSCI_Ax Baud Rate Control 1 */
652 #define UCA1IRTCTL                                         (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
653 #define UCA1IRRCTL                                         (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */
654 
655 /******************************************************************************
656 * EUSCI_A2 Registers
657 ******************************************************************************/
658 #define UCA2CTLW0                                (HWREG16(0x40001800))           /*!< eUSCI_Ax Control Word Register 0 */
659 #define UCA2CTLW0_SPI                            (HWREG16(0x40001800))
660 #define UCA2CTLW1                                (HWREG16(0x40001802))           /*!< eUSCI_Ax Control Word Register 1 */
661 #define UCA2BRW                                  (HWREG16(0x40001806))           /*!< eUSCI_Ax Baud Rate Control Word Register */
662 #define UCA2BRW_SPI                              (HWREG16(0x40001806))
663 #define UCA2MCTLW                                (HWREG16(0x40001808))           /*!< eUSCI_Ax Modulation Control Word Register */
664 #define UCA2STATW                                (HWREG16(0x4000180A))           /*!< eUSCI_Ax Status Register */
665 #define UCA2STATW_SPI                            (HWREG16(0x4000180A))
666 #define UCA2RXBUF                                (HWREG16(0x4000180C))           /*!< eUSCI_Ax Receive Buffer Register */
667 #define UCA2RXBUF_SPI                            (HWREG16(0x4000180C))
668 #define UCA2TXBUF                                (HWREG16(0x4000180E))           /*!< eUSCI_Ax Transmit Buffer Register */
669 #define UCA2TXBUF_SPI                            (HWREG16(0x4000180E))
670 #define UCA2ABCTL                                (HWREG16(0x40001810))           /*!< eUSCI_Ax Auto Baud Rate Control Register */
671 #define UCA2IRCTL                                (HWREG16(0x40001812))           /*!< eUSCI_Ax IrDA Control Word Register */
672 #define UCA2IE                                   (HWREG16(0x4000181A))           /*!< eUSCI_Ax Interrupt Enable Register */
673 #define UCA2IE_SPI                               (HWREG16(0x4000181A))
674 #define UCA2IFG                                  (HWREG16(0x4000181C))           /*!< eUSCI_Ax Interrupt Flag Register */
675 #define UCA2IFG_SPI                              (HWREG16(0x4000181C))
676 #define UCA2IV                                   (HWREG16(0x4000181E))           /*!< eUSCI_Ax Interrupt Vector Register */
677 #define UCA2IV_SPI                               (HWREG16(0x4000181E))
678 
679 /* Register offsets from EUSCI_A2_BASE address */
680 #define OFS_UCA2CTLW0                                      (0x0000)              /*!< eUSCI_Ax Control Word Register 0 */
681 #define OFS_UCA2CTLW0_SPI                                  (0x0000)
682 #define OFS_UCA2CTLW1                                      (0x0002)              /*!< eUSCI_Ax Control Word Register 1 */
683 #define OFS_UCA2BRW                                        (0x0006)              /*!< eUSCI_Ax Baud Rate Control Word Register */
684 #define OFS_UCA2BRW_SPI                                    (0x0006)
685 #define OFS_UCA2MCTLW                                      (0x0008)              /*!< eUSCI_Ax Modulation Control Word Register */
686 #define OFS_UCA2STATW                                      (0x000A)              /*!< eUSCI_Ax Status Register */
687 #define OFS_UCA2STATW_SPI                                  (0x000A)
688 #define OFS_UCA2RXBUF                                      (0x000C)              /*!< eUSCI_Ax Receive Buffer Register */
689 #define OFS_UCA2RXBUF_SPI                                  (0x000C)
690 #define OFS_UCA2TXBUF                                      (0x000E)              /*!< eUSCI_Ax Transmit Buffer Register */
691 #define OFS_UCA2TXBUF_SPI                                  (0x000E)
692 #define OFS_UCA2ABCTL                                      (0x0010)              /*!< eUSCI_Ax Auto Baud Rate Control Register */
693 #define OFS_UCA2IRCTL                                      (0x0012)              /*!< eUSCI_Ax IrDA Control Word Register */
694 #define OFS_UCA2IE                                         (0x001A)              /*!< eUSCI_Ax Interrupt Enable Register */
695 #define OFS_UCA2IE_SPI                                     (0x001A)
696 #define OFS_UCA2IFG                                        (0x001C)              /*!< eUSCI_Ax Interrupt Flag Register */
697 #define OFS_UCA2IFG_SPI                                    (0x001C)
698 #define OFS_UCA2IV                                         (0x001E)              /*!< eUSCI_Ax Interrupt Vector Register */
699 #define OFS_UCA2IV_SPI                                     (0x001E)
700 
701 #define UCA2CTL0                                           (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */
702 #define UCA2CTL1                                           (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */
703 #define UCA2BR0                                            (HWREG8_L(UCA2BRW))   /* eUSCI_Ax Baud Rate Control 0 */
704 #define UCA2BR1                                            (HWREG8_H(UCA2BRW))   /* eUSCI_Ax Baud Rate Control 1 */
705 #define UCA2IRTCTL                                         (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
706 #define UCA2IRRCTL                                         (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */
707 
708 /******************************************************************************
709 * EUSCI_A3 Registers
710 ******************************************************************************/
711 #define UCA3CTLW0                                (HWREG16(0x40001C00))           /*!< eUSCI_Ax Control Word Register 0 */
712 #define UCA3CTLW0_SPI                            (HWREG16(0x40001C00))
713 #define UCA3CTLW1                                (HWREG16(0x40001C02))           /*!< eUSCI_Ax Control Word Register 1 */
714 #define UCA3BRW                                  (HWREG16(0x40001C06))           /*!< eUSCI_Ax Baud Rate Control Word Register */
715 #define UCA3BRW_SPI                              (HWREG16(0x40001C06))
716 #define UCA3MCTLW                                (HWREG16(0x40001C08))           /*!< eUSCI_Ax Modulation Control Word Register */
717 #define UCA3STATW                                (HWREG16(0x40001C0A))           /*!< eUSCI_Ax Status Register */
718 #define UCA3STATW_SPI                            (HWREG16(0x40001C0A))
719 #define UCA3RXBUF                                (HWREG16(0x40001C0C))           /*!< eUSCI_Ax Receive Buffer Register */
720 #define UCA3RXBUF_SPI                            (HWREG16(0x40001C0C))
721 #define UCA3TXBUF                                (HWREG16(0x40001C0E))           /*!< eUSCI_Ax Transmit Buffer Register */
722 #define UCA3TXBUF_SPI                            (HWREG16(0x40001C0E))
723 #define UCA3ABCTL                                (HWREG16(0x40001C10))           /*!< eUSCI_Ax Auto Baud Rate Control Register */
724 #define UCA3IRCTL                                (HWREG16(0x40001C12))           /*!< eUSCI_Ax IrDA Control Word Register */
725 #define UCA3IE                                   (HWREG16(0x40001C1A))           /*!< eUSCI_Ax Interrupt Enable Register */
726 #define UCA3IE_SPI                               (HWREG16(0x40001C1A))
727 #define UCA3IFG                                  (HWREG16(0x40001C1C))           /*!< eUSCI_Ax Interrupt Flag Register */
728 #define UCA3IFG_SPI                              (HWREG16(0x40001C1C))
729 #define UCA3IV                                   (HWREG16(0x40001C1E))           /*!< eUSCI_Ax Interrupt Vector Register */
730 #define UCA3IV_SPI                               (HWREG16(0x40001C1E))
731 
732 /* Register offsets from EUSCI_A3_BASE address */
733 #define OFS_UCA3CTLW0                                      (0x0000)              /*!< eUSCI_Ax Control Word Register 0 */
734 #define OFS_UCA3CTLW0_SPI                                  (0x0000)
735 #define OFS_UCA3CTLW1                                      (0x0002)              /*!< eUSCI_Ax Control Word Register 1 */
736 #define OFS_UCA3BRW                                        (0x0006)              /*!< eUSCI_Ax Baud Rate Control Word Register */
737 #define OFS_UCA3BRW_SPI                                    (0x0006)
738 #define OFS_UCA3MCTLW                                      (0x0008)              /*!< eUSCI_Ax Modulation Control Word Register */
739 #define OFS_UCA3STATW                                      (0x000A)              /*!< eUSCI_Ax Status Register */
740 #define OFS_UCA3STATW_SPI                                  (0x000A)
741 #define OFS_UCA3RXBUF                                      (0x000C)              /*!< eUSCI_Ax Receive Buffer Register */
742 #define OFS_UCA3RXBUF_SPI                                  (0x000C)
743 #define OFS_UCA3TXBUF                                      (0x000E)              /*!< eUSCI_Ax Transmit Buffer Register */
744 #define OFS_UCA3TXBUF_SPI                                  (0x000E)
745 #define OFS_UCA3ABCTL                                      (0x0010)              /*!< eUSCI_Ax Auto Baud Rate Control Register */
746 #define OFS_UCA3IRCTL                                      (0x0012)              /*!< eUSCI_Ax IrDA Control Word Register */
747 #define OFS_UCA3IE                                         (0x001A)              /*!< eUSCI_Ax Interrupt Enable Register */
748 #define OFS_UCA3IE_SPI                                     (0x001A)
749 #define OFS_UCA3IFG                                        (0x001C)              /*!< eUSCI_Ax Interrupt Flag Register */
750 #define OFS_UCA3IFG_SPI                                    (0x001C)
751 #define OFS_UCA3IV                                         (0x001E)              /*!< eUSCI_Ax Interrupt Vector Register */
752 #define OFS_UCA3IV_SPI                                     (0x001E)
753 
754 #define UCA3CTL0                                           (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */
755 #define UCA3CTL1                                           (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */
756 #define UCA3BR0                                            (HWREG8_L(UCA3BRW))   /* eUSCI_Ax Baud Rate Control 0 */
757 #define UCA3BR1                                            (HWREG8_H(UCA3BRW))   /* eUSCI_Ax Baud Rate Control 1 */
758 #define UCA3IRTCTL                                         (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
759 #define UCA3IRRCTL                                         (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */
760 
761 /******************************************************************************
762 * EUSCI_B0 Registers
763 ******************************************************************************/
764 #define UCB0CTLW0                                (HWREG16(0x40002000))           /*!< eUSCI_Bx Control Word Register 0 */
765 #define UCB0CTLW0_SPI                            (HWREG16(0x40002000))
766 #define UCB0CTLW1                                (HWREG16(0x40002002))           /*!< eUSCI_Bx Control Word Register 1 */
767 #define UCB0BRW                                  (HWREG16(0x40002006))           /*!< eUSCI_Bx Baud Rate Control Word Register */
768 #define UCB0BRW_SPI                              (HWREG16(0x40002006))
769 #define UCB0STATW                                (HWREG16(0x40002008))           /*!< eUSCI_Bx Status Register */
770 #define UCB0STATW_SPI                            (HWREG16(0x40002008))
771 #define UCB0TBCNT                                (HWREG16(0x4000200A))           /*!< eUSCI_Bx Byte Counter Threshold Register */
772 #define UCB0RXBUF                                (HWREG16(0x4000200C))           /*!< eUSCI_Bx Receive Buffer Register */
773 #define UCB0RXBUF_SPI                            (HWREG16(0x4000200C))
774 #define UCB0TXBUF                                (HWREG16(0x4000200E))           /*!< eUSCI_Bx Transmit Buffer Register */
775 #define UCB0TXBUF_SPI                            (HWREG16(0x4000200E))
776 #define UCB0I2COA0                               (HWREG16(0x40002014))           /*!< eUSCI_Bx I2C Own Address 0 Register */
777 #define UCB0I2COA1                               (HWREG16(0x40002016))           /*!< eUSCI_Bx I2C Own Address 1 Register */
778 #define UCB0I2COA2                               (HWREG16(0x40002018))           /*!< eUSCI_Bx I2C Own Address 2 Register */
779 #define UCB0I2COA3                               (HWREG16(0x4000201A))           /*!< eUSCI_Bx I2C Own Address 3 Register */
780 #define UCB0ADDRX                                (HWREG16(0x4000201C))           /*!< eUSCI_Bx I2C Received Address Register */
781 #define UCB0ADDMASK                              (HWREG16(0x4000201E))           /*!< eUSCI_Bx I2C Address Mask Register */
782 #define UCB0I2CSA                                (HWREG16(0x40002020))           /*!< eUSCI_Bx I2C Slave Address Register */
783 #define UCB0IE                                   (HWREG16(0x4000202A))           /*!< eUSCI_Bx Interrupt Enable Register */
784 #define UCB0IE_SPI                               (HWREG16(0x4000202A))
785 #define UCB0IFG                                  (HWREG16(0x4000202C))           /*!< eUSCI_Bx Interrupt Flag Register */
786 #define UCB0IFG_SPI                              (HWREG16(0x4000202C))
787 #define UCB0IV                                   (HWREG16(0x4000202E))           /*!< eUSCI_Bx Interrupt Vector Register */
788 #define UCB0IV_SPI                               (HWREG16(0x4000202E))
789 
790 /* Register offsets from EUSCI_B0_BASE address */
791 #define OFS_UCB0CTLW0                                      (0x0000)              /*!< eUSCI_Bx Control Word Register 0 */
792 #define OFS_UCB0CTLW0_SPI                                  (0x0000)
793 #define OFS_UCB0CTLW1                                      (0x0002)              /*!< eUSCI_Bx Control Word Register 1 */
794 #define OFS_UCB0BRW                                        (0x0006)              /*!< eUSCI_Bx Baud Rate Control Word Register */
795 #define OFS_UCB0BRW_SPI                                    (0x0006)
796 #define OFS_UCB0STATW                                      (0x0008)              /*!< eUSCI_Bx Status Register */
797 #define OFS_UCB0STATW_SPI                                  (0x0008)
798 #define OFS_UCB0TBCNT                                      (0x000A)              /*!< eUSCI_Bx Byte Counter Threshold Register */
799 #define OFS_UCB0RXBUF                                      (0x000C)              /*!< eUSCI_Bx Receive Buffer Register */
800 #define OFS_UCB0RXBUF_SPI                                  (0x000C)
801 #define OFS_UCB0TXBUF                                      (0x000E)              /*!< eUSCI_Bx Transmit Buffer Register */
802 #define OFS_UCB0TXBUF_SPI                                  (0x000E)
803 #define OFS_UCB0I2COA0                                     (0x0014)              /*!< eUSCI_Bx I2C Own Address 0 Register */
804 #define OFS_UCB0I2COA1                                     (0x0016)              /*!< eUSCI_Bx I2C Own Address 1 Register */
805 #define OFS_UCB0I2COA2                                     (0x0018)              /*!< eUSCI_Bx I2C Own Address 2 Register */
806 #define OFS_UCB0I2COA3                                     (0x001A)              /*!< eUSCI_Bx I2C Own Address 3 Register */
807 #define OFS_UCB0ADDRX                                      (0x001C)              /*!< eUSCI_Bx I2C Received Address Register */
808 #define OFS_UCB0ADDMASK                                    (0x001E)              /*!< eUSCI_Bx I2C Address Mask Register */
809 #define OFS_UCB0I2CSA                                      (0x0020)              /*!< eUSCI_Bx I2C Slave Address Register */
810 #define OFS_UCB0IE                                         (0x002A)              /*!< eUSCI_Bx Interrupt Enable Register */
811 #define OFS_UCB0IE_SPI                                     (0x002A)
812 #define OFS_UCB0IFG                                        (0x002C)              /*!< eUSCI_Bx Interrupt Flag Register */
813 #define OFS_UCB0IFG_SPI                                    (0x002C)
814 #define OFS_UCB0IV                                         (0x002E)              /*!< eUSCI_Bx Interrupt Vector Register */
815 #define OFS_UCB0IV_SPI                                     (0x002E)
816 
817 #define UCB0CTL0                                           (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */
818 #define UCB0CTL1                                           (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */
819 #define UCB0BR0                                            (HWREG8_L(UCB0BRW))   /* eUSCI_Bx Bit Rate Control 0 */
820 #define UCB0BR1                                            (HWREG8_H(UCB0BRW))   /* eUSCI_Bx Bit Rate Control 1 */
821 #define UCB0STAT                                           (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */
822 #define UCB0BCNT                                           (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */
823 
824 /******************************************************************************
825 * EUSCI_B1 Registers
826 ******************************************************************************/
827 #define UCB1CTLW0                                (HWREG16(0x40002400))           /*!< eUSCI_Bx Control Word Register 0 */
828 #define UCB1CTLW0_SPI                            (HWREG16(0x40002400))
829 #define UCB1CTLW1                                (HWREG16(0x40002402))           /*!< eUSCI_Bx Control Word Register 1 */
830 #define UCB1BRW                                  (HWREG16(0x40002406))           /*!< eUSCI_Bx Baud Rate Control Word Register */
831 #define UCB1BRW_SPI                              (HWREG16(0x40002406))
832 #define UCB1STATW                                (HWREG16(0x40002408))           /*!< eUSCI_Bx Status Register */
833 #define UCB1STATW_SPI                            (HWREG16(0x40002408))
834 #define UCB1TBCNT                                (HWREG16(0x4000240A))           /*!< eUSCI_Bx Byte Counter Threshold Register */
835 #define UCB1RXBUF                                (HWREG16(0x4000240C))           /*!< eUSCI_Bx Receive Buffer Register */
836 #define UCB1RXBUF_SPI                            (HWREG16(0x4000240C))
837 #define UCB1TXBUF                                (HWREG16(0x4000240E))           /*!< eUSCI_Bx Transmit Buffer Register */
838 #define UCB1TXBUF_SPI                            (HWREG16(0x4000240E))
839 #define UCB1I2COA0                               (HWREG16(0x40002414))           /*!< eUSCI_Bx I2C Own Address 0 Register */
840 #define UCB1I2COA1                               (HWREG16(0x40002416))           /*!< eUSCI_Bx I2C Own Address 1 Register */
841 #define UCB1I2COA2                               (HWREG16(0x40002418))           /*!< eUSCI_Bx I2C Own Address 2 Register */
842 #define UCB1I2COA3                               (HWREG16(0x4000241A))           /*!< eUSCI_Bx I2C Own Address 3 Register */
843 #define UCB1ADDRX                                (HWREG16(0x4000241C))           /*!< eUSCI_Bx I2C Received Address Register */
844 #define UCB1ADDMASK                              (HWREG16(0x4000241E))           /*!< eUSCI_Bx I2C Address Mask Register */
845 #define UCB1I2CSA                                (HWREG16(0x40002420))           /*!< eUSCI_Bx I2C Slave Address Register */
846 #define UCB1IE                                   (HWREG16(0x4000242A))           /*!< eUSCI_Bx Interrupt Enable Register */
847 #define UCB1IE_SPI                               (HWREG16(0x4000242A))
848 #define UCB1IFG                                  (HWREG16(0x4000242C))           /*!< eUSCI_Bx Interrupt Flag Register */
849 #define UCB1IFG_SPI                              (HWREG16(0x4000242C))
850 #define UCB1IV                                   (HWREG16(0x4000242E))           /*!< eUSCI_Bx Interrupt Vector Register */
851 #define UCB1IV_SPI                               (HWREG16(0x4000242E))
852 
853 /* Register offsets from EUSCI_B1_BASE address */
854 #define OFS_UCB1CTLW0                                      (0x0000)              /*!< eUSCI_Bx Control Word Register 0 */
855 #define OFS_UCB1CTLW0_SPI                                  (0x0000)
856 #define OFS_UCB1CTLW1                                      (0x0002)              /*!< eUSCI_Bx Control Word Register 1 */
857 #define OFS_UCB1BRW                                        (0x0006)              /*!< eUSCI_Bx Baud Rate Control Word Register */
858 #define OFS_UCB1BRW_SPI                                    (0x0006)
859 #define OFS_UCB1STATW                                      (0x0008)              /*!< eUSCI_Bx Status Register */
860 #define OFS_UCB1STATW_SPI                                  (0x0008)
861 #define OFS_UCB1TBCNT                                      (0x000A)              /*!< eUSCI_Bx Byte Counter Threshold Register */
862 #define OFS_UCB1RXBUF                                      (0x000C)              /*!< eUSCI_Bx Receive Buffer Register */
863 #define OFS_UCB1RXBUF_SPI                                  (0x000C)
864 #define OFS_UCB1TXBUF                                      (0x000E)              /*!< eUSCI_Bx Transmit Buffer Register */
865 #define OFS_UCB1TXBUF_SPI                                  (0x000E)
866 #define OFS_UCB1I2COA0                                     (0x0014)              /*!< eUSCI_Bx I2C Own Address 0 Register */
867 #define OFS_UCB1I2COA1                                     (0x0016)              /*!< eUSCI_Bx I2C Own Address 1 Register */
868 #define OFS_UCB1I2COA2                                     (0x0018)              /*!< eUSCI_Bx I2C Own Address 2 Register */
869 #define OFS_UCB1I2COA3                                     (0x001A)              /*!< eUSCI_Bx I2C Own Address 3 Register */
870 #define OFS_UCB1ADDRX                                      (0x001C)              /*!< eUSCI_Bx I2C Received Address Register */
871 #define OFS_UCB1ADDMASK                                    (0x001E)              /*!< eUSCI_Bx I2C Address Mask Register */
872 #define OFS_UCB1I2CSA                                      (0x0020)              /*!< eUSCI_Bx I2C Slave Address Register */
873 #define OFS_UCB1IE                                         (0x002A)              /*!< eUSCI_Bx Interrupt Enable Register */
874 #define OFS_UCB1IE_SPI                                     (0x002A)
875 #define OFS_UCB1IFG                                        (0x002C)              /*!< eUSCI_Bx Interrupt Flag Register */
876 #define OFS_UCB1IFG_SPI                                    (0x002C)
877 #define OFS_UCB1IV                                         (0x002E)              /*!< eUSCI_Bx Interrupt Vector Register */
878 #define OFS_UCB1IV_SPI                                     (0x002E)
879 
880 #define UCB1CTL0                                           (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */
881 #define UCB1CTL1                                           (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */
882 #define UCB1BR0                                            (HWREG8_L(UCB1BRW))   /* eUSCI_Bx Bit Rate Control 0 */
883 #define UCB1BR1                                            (HWREG8_H(UCB1BRW))   /* eUSCI_Bx Bit Rate Control 1 */
884 #define UCB1STAT                                           (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */
885 #define UCB1BCNT                                           (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */
886 
887 /******************************************************************************
888 * EUSCI_B2 Registers
889 ******************************************************************************/
890 #define UCB2CTLW0                                (HWREG16(0x40002800))           /*!< eUSCI_Bx Control Word Register 0 */
891 #define UCB2CTLW0_SPI                            (HWREG16(0x40002800))
892 #define UCB2CTLW1                                (HWREG16(0x40002802))           /*!< eUSCI_Bx Control Word Register 1 */
893 #define UCB2BRW                                  (HWREG16(0x40002806))           /*!< eUSCI_Bx Baud Rate Control Word Register */
894 #define UCB2BRW_SPI                              (HWREG16(0x40002806))
895 #define UCB2STATW                                (HWREG16(0x40002808))           /*!< eUSCI_Bx Status Register */
896 #define UCB2STATW_SPI                            (HWREG16(0x40002808))
897 #define UCB2TBCNT                                (HWREG16(0x4000280A))           /*!< eUSCI_Bx Byte Counter Threshold Register */
898 #define UCB2RXBUF                                (HWREG16(0x4000280C))           /*!< eUSCI_Bx Receive Buffer Register */
899 #define UCB2RXBUF_SPI                            (HWREG16(0x4000280C))
900 #define UCB2TXBUF                                (HWREG16(0x4000280E))           /*!< eUSCI_Bx Transmit Buffer Register */
901 #define UCB2TXBUF_SPI                            (HWREG16(0x4000280E))
902 #define UCB2I2COA0                               (HWREG16(0x40002814))           /*!< eUSCI_Bx I2C Own Address 0 Register */
903 #define UCB2I2COA1                               (HWREG16(0x40002816))           /*!< eUSCI_Bx I2C Own Address 1 Register */
904 #define UCB2I2COA2                               (HWREG16(0x40002818))           /*!< eUSCI_Bx I2C Own Address 2 Register */
905 #define UCB2I2COA3                               (HWREG16(0x4000281A))           /*!< eUSCI_Bx I2C Own Address 3 Register */
906 #define UCB2ADDRX                                (HWREG16(0x4000281C))           /*!< eUSCI_Bx I2C Received Address Register */
907 #define UCB2ADDMASK                              (HWREG16(0x4000281E))           /*!< eUSCI_Bx I2C Address Mask Register */
908 #define UCB2I2CSA                                (HWREG16(0x40002820))           /*!< eUSCI_Bx I2C Slave Address Register */
909 #define UCB2IE                                   (HWREG16(0x4000282A))           /*!< eUSCI_Bx Interrupt Enable Register */
910 #define UCB2IE_SPI                               (HWREG16(0x4000282A))
911 #define UCB2IFG                                  (HWREG16(0x4000282C))           /*!< eUSCI_Bx Interrupt Flag Register */
912 #define UCB2IFG_SPI                              (HWREG16(0x4000282C))
913 #define UCB2IV                                   (HWREG16(0x4000282E))           /*!< eUSCI_Bx Interrupt Vector Register */
914 #define UCB2IV_SPI                               (HWREG16(0x4000282E))
915 
916 /* Register offsets from EUSCI_B2_BASE address */
917 #define OFS_UCB2CTLW0                                      (0x0000)              /*!< eUSCI_Bx Control Word Register 0 */
918 #define OFS_UCB2CTLW0_SPI                                  (0x0000)
919 #define OFS_UCB2CTLW1                                      (0x0002)              /*!< eUSCI_Bx Control Word Register 1 */
920 #define OFS_UCB2BRW                                        (0x0006)              /*!< eUSCI_Bx Baud Rate Control Word Register */
921 #define OFS_UCB2BRW_SPI                                    (0x0006)
922 #define OFS_UCB2STATW                                      (0x0008)              /*!< eUSCI_Bx Status Register */
923 #define OFS_UCB2STATW_SPI                                  (0x0008)
924 #define OFS_UCB2TBCNT                                      (0x000A)              /*!< eUSCI_Bx Byte Counter Threshold Register */
925 #define OFS_UCB2RXBUF                                      (0x000C)              /*!< eUSCI_Bx Receive Buffer Register */
926 #define OFS_UCB2RXBUF_SPI                                  (0x000C)
927 #define OFS_UCB2TXBUF                                      (0x000E)              /*!< eUSCI_Bx Transmit Buffer Register */
928 #define OFS_UCB2TXBUF_SPI                                  (0x000E)
929 #define OFS_UCB2I2COA0                                     (0x0014)              /*!< eUSCI_Bx I2C Own Address 0 Register */
930 #define OFS_UCB2I2COA1                                     (0x0016)              /*!< eUSCI_Bx I2C Own Address 1 Register */
931 #define OFS_UCB2I2COA2                                     (0x0018)              /*!< eUSCI_Bx I2C Own Address 2 Register */
932 #define OFS_UCB2I2COA3                                     (0x001A)              /*!< eUSCI_Bx I2C Own Address 3 Register */
933 #define OFS_UCB2ADDRX                                      (0x001C)              /*!< eUSCI_Bx I2C Received Address Register */
934 #define OFS_UCB2ADDMASK                                    (0x001E)              /*!< eUSCI_Bx I2C Address Mask Register */
935 #define OFS_UCB2I2CSA                                      (0x0020)              /*!< eUSCI_Bx I2C Slave Address Register */
936 #define OFS_UCB2IE                                         (0x002A)              /*!< eUSCI_Bx Interrupt Enable Register */
937 #define OFS_UCB2IE_SPI                                     (0x002A)
938 #define OFS_UCB2IFG                                        (0x002C)              /*!< eUSCI_Bx Interrupt Flag Register */
939 #define OFS_UCB2IFG_SPI                                    (0x002C)
940 #define OFS_UCB2IV                                         (0x002E)              /*!< eUSCI_Bx Interrupt Vector Register */
941 #define OFS_UCB2IV_SPI                                     (0x002E)
942 
943 #define UCB2CTL0                                           (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */
944 #define UCB2CTL1                                           (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */
945 #define UCB2BR0                                            (HWREG8_L(UCB2BRW))   /* eUSCI_Bx Bit Rate Control 0 */
946 #define UCB2BR1                                            (HWREG8_H(UCB2BRW))   /* eUSCI_Bx Bit Rate Control 1 */
947 #define UCB2STAT                                           (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */
948 #define UCB2BCNT                                           (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */
949 
950 /******************************************************************************
951 * EUSCI_B3 Registers
952 ******************************************************************************/
953 #define UCB3CTLW0                                (HWREG16(0x40002C00))           /*!< eUSCI_Bx Control Word Register 0 */
954 #define UCB3CTLW0_SPI                            (HWREG16(0x40002C00))
955 #define UCB3CTLW1                                (HWREG16(0x40002C02))           /*!< eUSCI_Bx Control Word Register 1 */
956 #define UCB3BRW                                  (HWREG16(0x40002C06))           /*!< eUSCI_Bx Baud Rate Control Word Register */
957 #define UCB3BRW_SPI                              (HWREG16(0x40002C06))
958 #define UCB3STATW                                (HWREG16(0x40002C08))           /*!< eUSCI_Bx Status Register */
959 #define UCB3STATW_SPI                            (HWREG16(0x40002C08))
960 #define UCB3TBCNT                                (HWREG16(0x40002C0A))           /*!< eUSCI_Bx Byte Counter Threshold Register */
961 #define UCB3RXBUF                                (HWREG16(0x40002C0C))           /*!< eUSCI_Bx Receive Buffer Register */
962 #define UCB3RXBUF_SPI                            (HWREG16(0x40002C0C))
963 #define UCB3TXBUF                                (HWREG16(0x40002C0E))           /*!< eUSCI_Bx Transmit Buffer Register */
964 #define UCB3TXBUF_SPI                            (HWREG16(0x40002C0E))
965 #define UCB3I2COA0                               (HWREG16(0x40002C14))           /*!< eUSCI_Bx I2C Own Address 0 Register */
966 #define UCB3I2COA1                               (HWREG16(0x40002C16))           /*!< eUSCI_Bx I2C Own Address 1 Register */
967 #define UCB3I2COA2                               (HWREG16(0x40002C18))           /*!< eUSCI_Bx I2C Own Address 2 Register */
968 #define UCB3I2COA3                               (HWREG16(0x40002C1A))           /*!< eUSCI_Bx I2C Own Address 3 Register */
969 #define UCB3ADDRX                                (HWREG16(0x40002C1C))           /*!< eUSCI_Bx I2C Received Address Register */
970 #define UCB3ADDMASK                              (HWREG16(0x40002C1E))           /*!< eUSCI_Bx I2C Address Mask Register */
971 #define UCB3I2CSA                                (HWREG16(0x40002C20))           /*!< eUSCI_Bx I2C Slave Address Register */
972 #define UCB3IE                                   (HWREG16(0x40002C2A))           /*!< eUSCI_Bx Interrupt Enable Register */
973 #define UCB3IE_SPI                               (HWREG16(0x40002C2A))
974 #define UCB3IFG                                  (HWREG16(0x40002C2C))           /*!< eUSCI_Bx Interrupt Flag Register */
975 #define UCB3IFG_SPI                              (HWREG16(0x40002C2C))
976 #define UCB3IV                                   (HWREG16(0x40002C2E))           /*!< eUSCI_Bx Interrupt Vector Register */
977 #define UCB3IV_SPI                               (HWREG16(0x40002C2E))
978 
979 /* Register offsets from EUSCI_B3_BASE address */
980 #define OFS_UCB3CTLW0                                      (0x0000)              /*!< eUSCI_Bx Control Word Register 0 */
981 #define OFS_UCB3CTLW0_SPI                                  (0x0000)
982 #define OFS_UCB3CTLW1                                      (0x0002)              /*!< eUSCI_Bx Control Word Register 1 */
983 #define OFS_UCB3BRW                                        (0x0006)              /*!< eUSCI_Bx Baud Rate Control Word Register */
984 #define OFS_UCB3BRW_SPI                                    (0x0006)
985 #define OFS_UCB3STATW                                      (0x0008)              /*!< eUSCI_Bx Status Register */
986 #define OFS_UCB3STATW_SPI                                  (0x0008)
987 #define OFS_UCB3TBCNT                                      (0x000A)              /*!< eUSCI_Bx Byte Counter Threshold Register */
988 #define OFS_UCB3RXBUF                                      (0x000C)              /*!< eUSCI_Bx Receive Buffer Register */
989 #define OFS_UCB3RXBUF_SPI                                  (0x000C)
990 #define OFS_UCB3TXBUF                                      (0x000E)              /*!< eUSCI_Bx Transmit Buffer Register */
991 #define OFS_UCB3TXBUF_SPI                                  (0x000E)
992 #define OFS_UCB3I2COA0                                     (0x0014)              /*!< eUSCI_Bx I2C Own Address 0 Register */
993 #define OFS_UCB3I2COA1                                     (0x0016)              /*!< eUSCI_Bx I2C Own Address 1 Register */
994 #define OFS_UCB3I2COA2                                     (0x0018)              /*!< eUSCI_Bx I2C Own Address 2 Register */
995 #define OFS_UCB3I2COA3                                     (0x001A)              /*!< eUSCI_Bx I2C Own Address 3 Register */
996 #define OFS_UCB3ADDRX                                      (0x001C)              /*!< eUSCI_Bx I2C Received Address Register */
997 #define OFS_UCB3ADDMASK                                    (0x001E)              /*!< eUSCI_Bx I2C Address Mask Register */
998 #define OFS_UCB3I2CSA                                      (0x0020)              /*!< eUSCI_Bx I2C Slave Address Register */
999 #define OFS_UCB3IE                                         (0x002A)              /*!< eUSCI_Bx Interrupt Enable Register */
1000 #define OFS_UCB3IE_SPI                                     (0x002A)
1001 #define OFS_UCB3IFG                                        (0x002C)              /*!< eUSCI_Bx Interrupt Flag Register */
1002 #define OFS_UCB3IFG_SPI                                    (0x002C)
1003 #define OFS_UCB3IV                                         (0x002E)              /*!< eUSCI_Bx Interrupt Vector Register */
1004 #define OFS_UCB3IV_SPI                                     (0x002E)
1005 
1006 #define UCB3CTL0                                           (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */
1007 #define UCB3CTL1                                           (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */
1008 #define UCB3BR0                                            (HWREG8_L(UCB3BRW))   /* eUSCI_Bx Bit Rate Control 0 */
1009 #define UCB3BR1                                            (HWREG8_H(UCB3BRW))   /* eUSCI_Bx Bit Rate Control 1 */
1010 #define UCB3STAT                                           (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */
1011 #define UCB3BCNT                                           (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */
1012 
1013 /******************************************************************************
1014 * PMAP Registers
1015 ******************************************************************************/
1016 #define PMAPKEYID                                (HWREG16(0x40005000))           /*!< Port Mapping Key Register */
1017 #define PMAPCTL                                  (HWREG16(0x40005002))           /*!< Port Mapping Control Register */
1018 #define P1MAP01                                  (HWREG16(0x40005008))           /*!< Port mapping register, P1.0 and P1.1 */
1019 #define P1MAP23                                  (HWREG16(0x4000500A))           /*!< Port mapping register, P1.2 and P1.3 */
1020 #define P1MAP45                                  (HWREG16(0x4000500C))           /*!< Port mapping register, P1.4 and P1.5 */
1021 #define P1MAP67                                  (HWREG16(0x4000500E))           /*!< Port mapping register, P1.6 and P1.7 */
1022 #define P2MAP01                                  (HWREG16(0x40005010))           /*!< Port mapping register, P2.0 and P2.1 */
1023 #define P2MAP23                                  (HWREG16(0x40005012))           /*!< Port mapping register, P2.2 and P2.3 */
1024 #define P2MAP45                                  (HWREG16(0x40005014))           /*!< Port mapping register, P2.4 and P2.5 */
1025 #define P2MAP67                                  (HWREG16(0x40005016))           /*!< Port mapping register, P2.6 and P2.7 */
1026 #define P3MAP01                                  (HWREG16(0x40005018))           /*!< Port mapping register, P3.0 and P3.1 */
1027 #define P3MAP23                                  (HWREG16(0x4000501A))           /*!< Port mapping register, P3.2 and P3.3 */
1028 #define P3MAP45                                  (HWREG16(0x4000501C))           /*!< Port mapping register, P3.4 and P3.5 */
1029 #define P3MAP67                                  (HWREG16(0x4000501E))           /*!< Port mapping register, P3.6 and P3.7 */
1030 #define P4MAP01                                  (HWREG16(0x40005020))           /*!< Port mapping register, P4.0 and P4.1 */
1031 #define P4MAP23                                  (HWREG16(0x40005022))           /*!< Port mapping register, P4.2 and P4.3 */
1032 #define P4MAP45                                  (HWREG16(0x40005024))           /*!< Port mapping register, P4.4 and P4.5 */
1033 #define P4MAP67                                  (HWREG16(0x40005026))           /*!< Port mapping register, P4.6 and P4.7 */
1034 #define P5MAP01                                  (HWREG16(0x40005028))           /*!< Port mapping register, P5.0 and P5.1 */
1035 #define P5MAP23                                  (HWREG16(0x4000502A))           /*!< Port mapping register, P5.2 and P5.3 */
1036 #define P5MAP45                                  (HWREG16(0x4000502C))           /*!< Port mapping register, P5.4 and P5.5 */
1037 #define P5MAP67                                  (HWREG16(0x4000502E))           /*!< Port mapping register, P5.6 and P5.7 */
1038 #define P6MAP01                                  (HWREG16(0x40005030))           /*!< Port mapping register, P6.0 and P6.1 */
1039 #define P6MAP23                                  (HWREG16(0x40005032))           /*!< Port mapping register, P6.2 and P6.3 */
1040 #define P6MAP45                                  (HWREG16(0x40005034))           /*!< Port mapping register, P6.4 and P6.5 */
1041 #define P6MAP67                                  (HWREG16(0x40005036))           /*!< Port mapping register, P6.6 and P6.7 */
1042 #define P7MAP01                                  (HWREG16(0x40005038))           /*!< Port mapping register, P7.0 and P7.1 */
1043 #define P7MAP23                                  (HWREG16(0x4000503A))           /*!< Port mapping register, P7.2 and P7.3 */
1044 #define P7MAP45                                  (HWREG16(0x4000503C))           /*!< Port mapping register, P7.4 and P7.5 */
1045 #define P7MAP67                                  (HWREG16(0x4000503E))           /*!< Port mapping register, P7.6 and P7.7 */
1046 
1047 /* Register offsets from PMAP_BASE address */
1048 #define OFS_PMAPKEYID                                      (0x0000)              /*!< Port Mapping Key Register */
1049 #define OFS_PMAPCTL                                        (0x0002)              /*!< Port Mapping Control Register */
1050 #define OFS_P1MAP01                                        (0x0008)              /*!< Port mapping register, P1.0 and P1.1 */
1051 #define OFS_P1MAP23                                        (0x000A)              /*!< Port mapping register, P1.2 and P1.3 */
1052 #define OFS_P1MAP45                                        (0x000C)              /*!< Port mapping register, P1.4 and P1.5 */
1053 #define OFS_P1MAP67                                        (0x000E)              /*!< Port mapping register, P1.6 and P1.7 */
1054 #define OFS_P2MAP01                                        (0x0010)              /*!< Port mapping register, P2.0 and P2.1 */
1055 #define OFS_P2MAP23                                        (0x0012)              /*!< Port mapping register, P2.2 and P2.3 */
1056 #define OFS_P2MAP45                                        (0x0014)              /*!< Port mapping register, P2.4 and P2.5 */
1057 #define OFS_P2MAP67                                        (0x0016)              /*!< Port mapping register, P2.6 and P2.7 */
1058 #define OFS_P3MAP01                                        (0x0018)              /*!< Port mapping register, P3.0 and P3.1 */
1059 #define OFS_P3MAP23                                        (0x001A)              /*!< Port mapping register, P3.2 and P3.3 */
1060 #define OFS_P3MAP45                                        (0x001C)              /*!< Port mapping register, P3.4 and P3.5 */
1061 #define OFS_P3MAP67                                        (0x001E)              /*!< Port mapping register, P3.6 and P3.7 */
1062 #define OFS_P4MAP01                                        (0x0020)              /*!< Port mapping register, P4.0 and P4.1 */
1063 #define OFS_P4MAP23                                        (0x0022)              /*!< Port mapping register, P4.2 and P4.3 */
1064 #define OFS_P4MAP45                                        (0x0024)              /*!< Port mapping register, P4.4 and P4.5 */
1065 #define OFS_P4MAP67                                        (0x0026)              /*!< Port mapping register, P4.6 and P4.7 */
1066 #define OFS_P5MAP01                                        (0x0028)              /*!< Port mapping register, P5.0 and P5.1 */
1067 #define OFS_P5MAP23                                        (0x002A)              /*!< Port mapping register, P5.2 and P5.3 */
1068 #define OFS_P5MAP45                                        (0x002C)              /*!< Port mapping register, P5.4 and P5.5 */
1069 #define OFS_P5MAP67                                        (0x002E)              /*!< Port mapping register, P5.6 and P5.7 */
1070 #define OFS_P6MAP01                                        (0x0030)              /*!< Port mapping register, P6.0 and P6.1 */
1071 #define OFS_P6MAP23                                        (0x0032)              /*!< Port mapping register, P6.2 and P6.3 */
1072 #define OFS_P6MAP45                                        (0x0034)              /*!< Port mapping register, P6.4 and P6.5 */
1073 #define OFS_P6MAP67                                        (0x0036)              /*!< Port mapping register, P6.6 and P6.7 */
1074 #define OFS_P7MAP01                                        (0x0038)              /*!< Port mapping register, P7.0 and P7.1 */
1075 #define OFS_P7MAP23                                        (0x003A)              /*!< Port mapping register, P7.2 and P7.3 */
1076 #define OFS_P7MAP45                                        (0x003C)              /*!< Port mapping register, P7.4 and P7.5 */
1077 #define OFS_P7MAP67                                        (0x003E)              /*!< Port mapping register, P7.6 and P7.7 */
1078 
1079 
1080 /******************************************************************************
1081 * REF_A Registers
1082 ******************************************************************************/
1083 #define REFCTL0                                  (HWREG16(0x40003000))           /*!< REF Control Register 0 */
1084 
1085 /* Register offsets from REF_A_BASE address */
1086 #define OFS_REFCTL0                                        (0x0000)              /*!< REF Control Register 0 */
1087 
1088 #define REFCTL0_L                                          (HWREG8_L(REFCTL0))   /* REF Control Register 0 */
1089 #define REFCTL0_H                                          (HWREG8_H(REFCTL0))   /* REF Control Register 0 */
1090 
1091 /******************************************************************************
1092 * RTC_C Registers
1093 ******************************************************************************/
1094 #define RTCCTL0                                  (HWREG16(0x40004400))           /*!< RTCCTL0 Register */
1095 #define RTCCTL13                                 (HWREG16(0x40004402))           /*!< RTCCTL13 Register */
1096 #define RTCOCAL                                  (HWREG16(0x40004404))           /*!< RTCOCAL Register */
1097 #define RTCTCMP                                  (HWREG16(0x40004406))           /*!< RTCTCMP Register */
1098 #define RTCPS0CTL                                (HWREG16(0x40004408))           /*!< Real-Time Clock Prescale Timer 0 Control Register */
1099 #define RTCPS1CTL                                (HWREG16(0x4000440A))           /*!< Real-Time Clock Prescale Timer 1 Control Register */
1100 #define RTCPS                                    (HWREG16(0x4000440C))           /*!< Real-Time Clock Prescale Timer Counter Register */
1101 #define RTCIV                                    (HWREG16(0x4000440E))           /*!< Real-Time Clock Interrupt Vector Register */
1102 #define RTCTIM0                                  (HWREG16(0x40004410))           /*!< RTCTIM0 Register  Hexadecimal Format */
1103 #define RTCTIM0_BCD                              (HWREG16(0x40004410))
1104 #define RTCTIM1                                  (HWREG16(0x40004412))           /*!< Real-Time Clock Hour, Day of Week */
1105 #define RTCTIM1_BCD                              (HWREG16(0x40004412))
1106 #define RTCDATE                                  (HWREG16(0x40004414))           /*!< RTCDATE - Hexadecimal Format */
1107 #define RTCDATE_BCD                              (HWREG16(0x40004414))
1108 #define RTCYEAR                                  (HWREG16(0x40004416))           /*!< RTCYEAR Register  Hexadecimal Format */
1109 #define RTCYEAR_BCD                              (HWREG16(0x40004416))
1110 #define RTCAMINHR                                (HWREG16(0x40004418))           /*!< RTCMINHR - Hexadecimal Format */
1111 #define RTCAMINHR_BCD                            (HWREG16(0x40004418))
1112 #define RTCADOWDAY                               (HWREG16(0x4000441A))           /*!< RTCADOWDAY - Hexadecimal Format */
1113 #define RTCADOWDAY_BCD                           (HWREG16(0x4000441A))
1114 #define RTCBIN2BCD                               (HWREG16(0x4000441C))           /*!< Binary-to-BCD Conversion Register */
1115 #define RTCBCD2BIN                               (HWREG16(0x4000441E))           /*!< BCD-to-Binary Conversion Register */
1116 
1117 /* Register offsets from RTC_C_BASE address */
1118 #define OFS_RTCCTL0                                        (0x0000)              /*!< RTCCTL0 Register */
1119 #define OFS_RTCCTL13                                       (0x0002)              /*!< RTCCTL13 Register */
1120 #define OFS_RTCOCAL                                        (0x0004)              /*!< RTCOCAL Register */
1121 #define OFS_RTCTCMP                                        (0x0006)              /*!< RTCTCMP Register */
1122 #define OFS_RTCPS0CTL                                      (0x0008)              /*!< Real-Time Clock Prescale Timer 0 Control Register */
1123 #define OFS_RTCPS1CTL                                      (0x000A)              /*!< Real-Time Clock Prescale Timer 1 Control Register */
1124 #define OFS_RTCPS                                          (0x000C)              /*!< Real-Time Clock Prescale Timer Counter Register */
1125 #define OFS_RTCIV                                          (0x000E)              /*!< Real-Time Clock Interrupt Vector Register */
1126 #define OFS_RTCTIM0                                        (0x0010)              /*!< RTCTIM0 Register  Hexadecimal Format */
1127 #define OFS_RTCTIM0_BCD                                    (0x0010)
1128 #define OFS_RTCTIM1                                        (0x0012)              /*!< Real-Time Clock Hour, Day of Week */
1129 #define OFS_RTCTIM1_BCD                                    (0x0012)
1130 #define OFS_RTCDATE                                        (0x0014)              /*!< RTCDATE - Hexadecimal Format */
1131 #define OFS_RTCDATE_BCD                                    (0x0014)
1132 #define OFS_RTCYEAR                                        (0x0016)              /*!< RTCYEAR Register  Hexadecimal Format */
1133 #define OFS_RTCYEAR_BCD                                    (0x0016)
1134 #define OFS_RTCAMINHR                                      (0x0018)              /*!< RTCMINHR - Hexadecimal Format */
1135 #define OFS_RTCAMINHR_BCD                                  (0x0018)
1136 #define OFS_RTCADOWDAY                                     (0x001A)              /*!< RTCADOWDAY - Hexadecimal Format */
1137 #define OFS_RTCADOWDAY_BCD                                 (0x001A)
1138 #define OFS_RTCBIN2BCD                                     (0x001C)              /*!< Binary-to-BCD Conversion Register */
1139 #define OFS_RTCBCD2BIN                                     (0x001E)              /*!< BCD-to-Binary Conversion Register */
1140 
1141 #define RTCCTL0_L                                          (HWREG8_L(RTCCTL0))   /* RTCCTL0 Register */
1142 #define RTCCTL0_H                                          (HWREG8_H(RTCCTL0))   /* RTCCTL0 Register */
1143 #define RTCCTL1                                            (HWREG8_L(RTCCTL13))  /* RTCCTL13 Register */
1144 #define RTCCTL13_L                                         (HWREG8_L(RTCCTL13))  /* RTCCTL13 Register */
1145 #define RTCCTL3                                            (HWREG8_H(RTCCTL13))  /* RTCCTL13 Register */
1146 #define RTCCTL13_H                                         (HWREG8_H(RTCCTL13))  /* RTCCTL13 Register */
1147 #define RTCOCAL_L                                          (HWREG8_L(RTCOCAL))   /* RTCOCAL Register */
1148 #define RTCOCAL_H                                          (HWREG8_H(RTCOCAL))   /* RTCOCAL Register */
1149 #define RTCTCMP_L                                          (HWREG8_L(RTCTCMP))   /* RTCTCMP Register */
1150 #define RTCTCMP_H                                          (HWREG8_H(RTCTCMP))   /* RTCTCMP Register */
1151 #define RTCPS0CTL_L                                        (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
1152 #define RTCPS0CTL_H                                        (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
1153 #define RTCPS1CTL_L                                        (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
1154 #define RTCPS1CTL_H                                        (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
1155 #define RTCPS0                                             (HWREG8_L(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */
1156 #define RTCPS_L                                            (HWREG8_L(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */
1157 #define RTCPS1                                             (HWREG8_H(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */
1158 #define RTCPS_H                                            (HWREG8_H(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */
1159 #define RTCSEC                                             (HWREG8_L(RTCTIM0))   /* Real-Time Clock Seconds */
1160 #define RTCTIM0_L                                          (HWREG8_L(RTCTIM0))   /* Real-Time Clock Seconds */
1161 #define RTCMIN                                             (HWREG8_H(RTCTIM0))   /* Real-Time Clock Minutes */
1162 #define RTCTIM0_H                                          (HWREG8_H(RTCTIM0))   /* Real-Time Clock Minutes */
1163 #define RTCHOUR                                            (HWREG8_L(RTCTIM1))   /* Real-Time Clock Hour */
1164 #define RTCTIM1_L                                          (HWREG8_L(RTCTIM1))   /* Real-Time Clock Hour */
1165 #define RTCDOW                                             (HWREG8_H(RTCTIM1))   /* Real-Time Clock Day of Week */
1166 #define RTCTIM1_H                                          (HWREG8_H(RTCTIM1))   /* Real-Time Clock Day of Week */
1167 #define RTCDAY                                             (HWREG8_L(RTCDATE))   /* Real-Time Clock Day of Month */
1168 #define RTCDATE_L                                          (HWREG8_L(RTCDATE))   /* Real-Time Clock Day of Month */
1169 #define RTCMON                                             (HWREG8_H(RTCDATE))   /* Real-Time Clock Month */
1170 #define RTCDATE_H                                          (HWREG8_H(RTCDATE))   /* Real-Time Clock Month */
1171 #define RTCAMIN                                            (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
1172 #define RTCAMINHR_L                                        (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
1173 #define RTCAHOUR                                           (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
1174 #define RTCAMINHR_H                                        (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
1175 #define RTCADOW                                            (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
1176 #define RTCADOWDAY_L                                       (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
1177 #define RTCADAY                                            (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
1178 #define RTCADOWDAY_H                                       (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
1179 
1180 /******************************************************************************
1181 * TIMER_A0 Registers
1182 ******************************************************************************/
1183 #define TA0CTL                                   (HWREG16(0x40000000))           /*!< TimerAx Control Register */
1184 #define TA0CCTL0                                 (HWREG16(0x40000002))           /*!< Timer_A Capture/Compare Control Register */
1185 #define TA0CCTL1                                 (HWREG16(0x40000004))           /*!< Timer_A Capture/Compare Control Register */
1186 #define TA0CCTL2                                 (HWREG16(0x40000006))           /*!< Timer_A Capture/Compare Control Register */
1187 #define TA0CCTL3                                 (HWREG16(0x40000008))           /*!< Timer_A Capture/Compare Control Register */
1188 #define TA0CCTL4                                 (HWREG16(0x4000000A))           /*!< Timer_A Capture/Compare Control Register */
1189 #define TA0R                                     (HWREG16(0x40000010))           /*!< TimerA register */
1190 #define TA0CCR0                                  (HWREG16(0x40000012))           /*!< Timer_A Capture/Compare  Register */
1191 #define TA0CCR1                                  (HWREG16(0x40000014))           /*!< Timer_A Capture/Compare  Register */
1192 #define TA0CCR2                                  (HWREG16(0x40000016))           /*!< Timer_A Capture/Compare  Register */
1193 #define TA0CCR3                                  (HWREG16(0x40000018))           /*!< Timer_A Capture/Compare  Register */
1194 #define TA0CCR4                                  (HWREG16(0x4000001A))           /*!< Timer_A Capture/Compare  Register */
1195 #define TA0EX0                                   (HWREG16(0x40000020))           /*!< TimerAx Expansion 0 Register */
1196 #define TA0IV                                    (HWREG16(0x4000002E))           /*!< TimerAx Interrupt Vector Register */
1197 
1198 /* Register offsets from TIMER_A0_BASE address */
1199 #define OFS_TA0CTL                                         (0x0000)              /*!< TimerAx Control Register */
1200 #define OFS_TA0CCTL0                                       (0x0002)              /*!< Timer_A Capture/Compare Control Register */
1201 #define OFS_TA0CCTL1                                       (0x0004)              /*!< Timer_A Capture/Compare Control Register */
1202 #define OFS_TA0CCTL2                                       (0x0006)              /*!< Timer_A Capture/Compare Control Register */
1203 #define OFS_TA0CCTL3                                       (0x0008)              /*!< Timer_A Capture/Compare Control Register */
1204 #define OFS_TA0CCTL4                                       (0x000A)              /*!< Timer_A Capture/Compare Control Register */
1205 #define OFS_TA0R                                           (0x0010)              /*!< TimerA register */
1206 #define OFS_TA0CCR0                                        (0x0012)              /*!< Timer_A Capture/Compare  Register */
1207 #define OFS_TA0CCR1                                        (0x0014)              /*!< Timer_A Capture/Compare  Register */
1208 #define OFS_TA0CCR2                                        (0x0016)              /*!< Timer_A Capture/Compare  Register */
1209 #define OFS_TA0CCR3                                        (0x0018)              /*!< Timer_A Capture/Compare  Register */
1210 #define OFS_TA0CCR4                                        (0x001A)              /*!< Timer_A Capture/Compare  Register */
1211 #define OFS_TA0EX0                                         (0x0020)              /*!< TimerAx Expansion 0 Register */
1212 #define OFS_TA0IV                                          (0x002E)              /*!< TimerAx Interrupt Vector Register */
1213 
1214 
1215 /******************************************************************************
1216 * TIMER_A1 Registers
1217 ******************************************************************************/
1218 #define TA1CTL                                   (HWREG16(0x40000400))           /*!< TimerAx Control Register */
1219 #define TA1CCTL0                                 (HWREG16(0x40000402))           /*!< Timer_A Capture/Compare Control Register */
1220 #define TA1CCTL1                                 (HWREG16(0x40000404))           /*!< Timer_A Capture/Compare Control Register */
1221 #define TA1CCTL2                                 (HWREG16(0x40000406))           /*!< Timer_A Capture/Compare Control Register */
1222 #define TA1CCTL3                                 (HWREG16(0x40000408))           /*!< Timer_A Capture/Compare Control Register */
1223 #define TA1CCTL4                                 (HWREG16(0x4000040A))           /*!< Timer_A Capture/Compare Control Register */
1224 #define TA1R                                     (HWREG16(0x40000410))           /*!< TimerA register */
1225 #define TA1CCR0                                  (HWREG16(0x40000412))           /*!< Timer_A Capture/Compare  Register */
1226 #define TA1CCR1                                  (HWREG16(0x40000414))           /*!< Timer_A Capture/Compare  Register */
1227 #define TA1CCR2                                  (HWREG16(0x40000416))           /*!< Timer_A Capture/Compare  Register */
1228 #define TA1CCR3                                  (HWREG16(0x40000418))           /*!< Timer_A Capture/Compare  Register */
1229 #define TA1CCR4                                  (HWREG16(0x4000041A))           /*!< Timer_A Capture/Compare  Register */
1230 #define TA1EX0                                   (HWREG16(0x40000420))           /*!< TimerAx Expansion 0 Register */
1231 #define TA1IV                                    (HWREG16(0x4000042E))           /*!< TimerAx Interrupt Vector Register */
1232 
1233 /* Register offsets from TIMER_A1_BASE address */
1234 #define OFS_TA1CTL                                         (0x0000)              /*!< TimerAx Control Register */
1235 #define OFS_TA1CCTL0                                       (0x0002)              /*!< Timer_A Capture/Compare Control Register */
1236 #define OFS_TA1CCTL1                                       (0x0004)              /*!< Timer_A Capture/Compare Control Register */
1237 #define OFS_TA1CCTL2                                       (0x0006)              /*!< Timer_A Capture/Compare Control Register */
1238 #define OFS_TA1CCTL3                                       (0x0008)              /*!< Timer_A Capture/Compare Control Register */
1239 #define OFS_TA1CCTL4                                       (0x000A)              /*!< Timer_A Capture/Compare Control Register */
1240 #define OFS_TA1R                                           (0x0010)              /*!< TimerA register */
1241 #define OFS_TA1CCR0                                        (0x0012)              /*!< Timer_A Capture/Compare  Register */
1242 #define OFS_TA1CCR1                                        (0x0014)              /*!< Timer_A Capture/Compare  Register */
1243 #define OFS_TA1CCR2                                        (0x0016)              /*!< Timer_A Capture/Compare  Register */
1244 #define OFS_TA1CCR3                                        (0x0018)              /*!< Timer_A Capture/Compare  Register */
1245 #define OFS_TA1CCR4                                        (0x001A)              /*!< Timer_A Capture/Compare  Register */
1246 #define OFS_TA1EX0                                         (0x0020)              /*!< TimerAx Expansion 0 Register */
1247 #define OFS_TA1IV                                          (0x002E)              /*!< TimerAx Interrupt Vector Register */
1248 
1249 
1250 /******************************************************************************
1251 * TIMER_A2 Registers
1252 ******************************************************************************/
1253 #define TA2CTL                                   (HWREG16(0x40000800))           /*!< TimerAx Control Register */
1254 #define TA2CCTL0                                 (HWREG16(0x40000802))           /*!< Timer_A Capture/Compare Control Register */
1255 #define TA2CCTL1                                 (HWREG16(0x40000804))           /*!< Timer_A Capture/Compare Control Register */
1256 #define TA2CCTL2                                 (HWREG16(0x40000806))           /*!< Timer_A Capture/Compare Control Register */
1257 #define TA2CCTL3                                 (HWREG16(0x40000808))           /*!< Timer_A Capture/Compare Control Register */
1258 #define TA2CCTL4                                 (HWREG16(0x4000080A))           /*!< Timer_A Capture/Compare Control Register */
1259 #define TA2R                                     (HWREG16(0x40000810))           /*!< TimerA register */
1260 #define TA2CCR0                                  (HWREG16(0x40000812))           /*!< Timer_A Capture/Compare  Register */
1261 #define TA2CCR1                                  (HWREG16(0x40000814))           /*!< Timer_A Capture/Compare  Register */
1262 #define TA2CCR2                                  (HWREG16(0x40000816))           /*!< Timer_A Capture/Compare  Register */
1263 #define TA2CCR3                                  (HWREG16(0x40000818))           /*!< Timer_A Capture/Compare  Register */
1264 #define TA2CCR4                                  (HWREG16(0x4000081A))           /*!< Timer_A Capture/Compare  Register */
1265 #define TA2EX0                                   (HWREG16(0x40000820))           /*!< TimerAx Expansion 0 Register */
1266 #define TA2IV                                    (HWREG16(0x4000082E))           /*!< TimerAx Interrupt Vector Register */
1267 
1268 /* Register offsets from TIMER_A2_BASE address */
1269 #define OFS_TA2CTL                                         (0x0000)              /*!< TimerAx Control Register */
1270 #define OFS_TA2CCTL0                                       (0x0002)              /*!< Timer_A Capture/Compare Control Register */
1271 #define OFS_TA2CCTL1                                       (0x0004)              /*!< Timer_A Capture/Compare Control Register */
1272 #define OFS_TA2CCTL2                                       (0x0006)              /*!< Timer_A Capture/Compare Control Register */
1273 #define OFS_TA2CCTL3                                       (0x0008)              /*!< Timer_A Capture/Compare Control Register */
1274 #define OFS_TA2CCTL4                                       (0x000A)              /*!< Timer_A Capture/Compare Control Register */
1275 #define OFS_TA2R                                           (0x0010)              /*!< TimerA register */
1276 #define OFS_TA2CCR0                                        (0x0012)              /*!< Timer_A Capture/Compare  Register */
1277 #define OFS_TA2CCR1                                        (0x0014)              /*!< Timer_A Capture/Compare  Register */
1278 #define OFS_TA2CCR2                                        (0x0016)              /*!< Timer_A Capture/Compare  Register */
1279 #define OFS_TA2CCR3                                        (0x0018)              /*!< Timer_A Capture/Compare  Register */
1280 #define OFS_TA2CCR4                                        (0x001A)              /*!< Timer_A Capture/Compare  Register */
1281 #define OFS_TA2EX0                                         (0x0020)              /*!< TimerAx Expansion 0 Register */
1282 #define OFS_TA2IV                                          (0x002E)              /*!< TimerAx Interrupt Vector Register */
1283 
1284 
1285 /******************************************************************************
1286 * TIMER_A3 Registers
1287 ******************************************************************************/
1288 #define TA3CTL                                   (HWREG16(0x40000C00))           /*!< TimerAx Control Register */
1289 #define TA3CCTL0                                 (HWREG16(0x40000C02))           /*!< Timer_A Capture/Compare Control Register */
1290 #define TA3CCTL1                                 (HWREG16(0x40000C04))           /*!< Timer_A Capture/Compare Control Register */
1291 #define TA3CCTL2                                 (HWREG16(0x40000C06))           /*!< Timer_A Capture/Compare Control Register */
1292 #define TA3CCTL3                                 (HWREG16(0x40000C08))           /*!< Timer_A Capture/Compare Control Register */
1293 #define TA3CCTL4                                 (HWREG16(0x40000C0A))           /*!< Timer_A Capture/Compare Control Register */
1294 #define TA3R                                     (HWREG16(0x40000C10))           /*!< TimerA register */
1295 #define TA3CCR0                                  (HWREG16(0x40000C12))           /*!< Timer_A Capture/Compare  Register */
1296 #define TA3CCR1                                  (HWREG16(0x40000C14))           /*!< Timer_A Capture/Compare  Register */
1297 #define TA3CCR2                                  (HWREG16(0x40000C16))           /*!< Timer_A Capture/Compare  Register */
1298 #define TA3CCR3                                  (HWREG16(0x40000C18))           /*!< Timer_A Capture/Compare  Register */
1299 #define TA3CCR4                                  (HWREG16(0x40000C1A))           /*!< Timer_A Capture/Compare  Register */
1300 #define TA3EX0                                   (HWREG16(0x40000C20))           /*!< TimerAx Expansion 0 Register */
1301 #define TA3IV                                    (HWREG16(0x40000C2E))           /*!< TimerAx Interrupt Vector Register */
1302 
1303 /* Register offsets from TIMER_A3_BASE address */
1304 #define OFS_TA3CTL                                         (0x0000)              /*!< TimerAx Control Register */
1305 #define OFS_TA3CCTL0                                       (0x0002)              /*!< Timer_A Capture/Compare Control Register */
1306 #define OFS_TA3CCTL1                                       (0x0004)              /*!< Timer_A Capture/Compare Control Register */
1307 #define OFS_TA3CCTL2                                       (0x0006)              /*!< Timer_A Capture/Compare Control Register */
1308 #define OFS_TA3CCTL3                                       (0x0008)              /*!< Timer_A Capture/Compare Control Register */
1309 #define OFS_TA3CCTL4                                       (0x000A)              /*!< Timer_A Capture/Compare Control Register */
1310 #define OFS_TA3R                                           (0x0010)              /*!< TimerA register */
1311 #define OFS_TA3CCR0                                        (0x0012)              /*!< Timer_A Capture/Compare  Register */
1312 #define OFS_TA3CCR1                                        (0x0014)              /*!< Timer_A Capture/Compare  Register */
1313 #define OFS_TA3CCR2                                        (0x0016)              /*!< Timer_A Capture/Compare  Register */
1314 #define OFS_TA3CCR3                                        (0x0018)              /*!< Timer_A Capture/Compare  Register */
1315 #define OFS_TA3CCR4                                        (0x001A)              /*!< Timer_A Capture/Compare  Register */
1316 #define OFS_TA3EX0                                         (0x0020)              /*!< TimerAx Expansion 0 Register */
1317 #define OFS_TA3IV                                          (0x002E)              /*!< TimerAx Interrupt Vector Register */
1318 
1319 
1320 /******************************************************************************
1321 * WDT_A Registers
1322 ******************************************************************************/
1323 #define WDTCTL                                   (HWREG16(0x4000480C))           /*!< Watchdog Timer Control Register */
1324 
1325 /* Register offsets from WDT_A_BASE address */
1326 #define OFS_WDTCTL                                         (0x000C)              /*!< Watchdog Timer Control Register */
1327 
1328 
1329 /******************************************************************************
1330 * Peripheral register control bits (legacy section)                           *
1331 ******************************************************************************/
1332 
1333 /******************************************************************************
1334 * AES256 Bits (legacy section)
1335 ******************************************************************************/
1336 /* AESACTL0[AESOP] Bits */
1337 #define AESOP_OFS                                AES256_CTL0_OP_OFS              /*!< AESOP Offset */
1338 #define AESOP_M                                  AES256_CTL0_OP_MASK             /*!< AES operation */
1339 #define AESOP0                                   AES256_CTL0_OP0                 /*!< AESOP Bit 0 */
1340 #define AESOP1                                   AES256_CTL0_OP1                 /*!< AESOP Bit 1 */
1341 #define AESOP_0                                  AES256_CTL0_OP_0                /*!< Encryption */
1342 #define AESOP_1                                  AES256_CTL0_OP_1                /*!< Decryption. The provided key is the same key used for encryption */
1343 #define AESOP_2                                  AES256_CTL0_OP_2                /*!< Generate first round key required for decryption */
1344 #define AESOP_3                                  AES256_CTL0_OP_3                /*!< Decryption. The provided key is the first round key required for decryption */
1345 /* AESACTL0[AESKL] Bits */
1346 #define AESKL_OFS                                AES256_CTL0_KL_OFS              /*!< AESKL Offset */
1347 #define AESKL_M                                  AES256_CTL0_KL_MASK             /*!< AES key length */
1348 #define AESKL0                                   AES256_CTL0_KL0                 /*!< AESKL Bit 0 */
1349 #define AESKL1                                   AES256_CTL0_KL1                 /*!< AESKL Bit 1 */
1350 #define AESKL_0                                  AES256_CTL0_KL_0                /*!< AES128. The key size is 128 bit */
1351 #define AESKL_1                                  AES256_CTL0_KL_1                /*!< AES192. The key size is 192 bit. */
1352 #define AESKL_2                                  AES256_CTL0_KL_2                /*!< AES256. The key size is 256 bit */
1353 #define AESKL__128BIT                            AES256_CTL0_KL__128BIT          /*!< AES128. The key size is 128 bit */
1354 #define AESKL__192BIT                            AES256_CTL0_KL__192BIT          /*!< AES192. The key size is 192 bit. */
1355 #define AESKL__256BIT                            AES256_CTL0_KL__256BIT          /*!< AES256. The key size is 256 bit */
1356 /* AESACTL0[AESCM] Bits */
1357 #define AESCM_OFS                                AES256_CTL0_CM_OFS              /*!< AESCM Offset */
1358 #define AESCM_M                                  AES256_CTL0_CM_MASK             /*!< AES cipher mode select */
1359 #define AESCM0                                   AES256_CTL0_CM0                 /*!< AESCM Bit 0 */
1360 #define AESCM1                                   AES256_CTL0_CM1                 /*!< AESCM Bit 1 */
1361 #define AESCM_0                                  AES256_CTL0_CM_0                /*!< ECB */
1362 #define AESCM_1                                  AES256_CTL0_CM_1                /*!< CBC */
1363 #define AESCM_2                                  AES256_CTL0_CM_2                /*!< OFB */
1364 #define AESCM_3                                  AES256_CTL0_CM_3                /*!< CFB */
1365 #define AESCM__ECB                               AES256_CTL0_CM__ECB             /*!< ECB */
1366 #define AESCM__CBC                               AES256_CTL0_CM__CBC             /*!< CBC */
1367 #define AESCM__OFB                               AES256_CTL0_CM__OFB             /*!< OFB */
1368 #define AESCM__CFB                               AES256_CTL0_CM__CFB             /*!< CFB */
1369 /* AESACTL0[AESSWRST] Bits */
1370 #define AESSWRST_OFS                             AES256_CTL0_SWRST_OFS           /*!< AESSWRST Offset */
1371 #define AESSWRST                                 AES256_CTL0_SWRST               /*!< AES software reset */
1372 /* AESACTL0[AESRDYIFG] Bits */
1373 #define AESRDYIFG_OFS                            AES256_CTL0_RDYIFG_OFS          /*!< AESRDYIFG Offset */
1374 #define AESRDYIFG                                AES256_CTL0_RDYIFG              /*!< AES ready interrupt flag */
1375 /* AESACTL0[AESERRFG] Bits */
1376 #define AESERRFG_OFS                             AES256_CTL0_ERRFG_OFS           /*!< AESERRFG Offset */
1377 #define AESERRFG                                 AES256_CTL0_ERRFG               /*!< AES error flag */
1378 /* AESACTL0[AESRDYIE] Bits */
1379 #define AESRDYIE_OFS                             AES256_CTL0_RDYIE_OFS           /*!< AESRDYIE Offset */
1380 #define AESRDYIE                                 AES256_CTL0_RDYIE               /*!< AES ready interrupt enable */
1381 /* AESACTL0[AESCMEN] Bits */
1382 #define AESCMEN_OFS                              AES256_CTL0_CMEN_OFS            /*!< AESCMEN Offset */
1383 #define AESCMEN                                  AES256_CTL0_CMEN                /*!< AES cipher mode enable */
1384 /* AESACTL1[AESBLKCNT] Bits */
1385 #define AESBLKCNT_OFS                            AES256_CTL1_BLKCNT_OFS          /*!< AESBLKCNT Offset */
1386 #define AESBLKCNT_M                              AES256_CTL1_BLKCNT_MASK         /*!< Cipher Block Counter */
1387 #define AESBLKCNT0                               AES256_CTL1_BLKCNT0             /*!< AESBLKCNT Bit 0 */
1388 #define AESBLKCNT1                               AES256_CTL1_BLKCNT1             /*!< AESBLKCNT Bit 1 */
1389 #define AESBLKCNT2                               AES256_CTL1_BLKCNT2             /*!< AESBLKCNT Bit 2 */
1390 #define AESBLKCNT3                               AES256_CTL1_BLKCNT3             /*!< AESBLKCNT Bit 3 */
1391 #define AESBLKCNT4                               AES256_CTL1_BLKCNT4             /*!< AESBLKCNT Bit 4 */
1392 #define AESBLKCNT5                               AES256_CTL1_BLKCNT5             /*!< AESBLKCNT Bit 5 */
1393 #define AESBLKCNT6                               AES256_CTL1_BLKCNT6             /*!< AESBLKCNT Bit 6 */
1394 #define AESBLKCNT7                               AES256_CTL1_BLKCNT7             /*!< AESBLKCNT Bit 7 */
1395 /* AESASTAT[AESBUSY] Bits */
1396 #define AESBUSY_OFS                              AES256_STAT_BUSY_OFS            /*!< AESBUSY Offset */
1397 #define AESBUSY                                  AES256_STAT_BUSY                /*!< AES accelerator module busy */
1398 /* AESASTAT[AESKEYWR] Bits */
1399 #define AESKEYWR_OFS                             AES256_STAT_KEYWR_OFS           /*!< AESKEYWR Offset */
1400 #define AESKEYWR                                 AES256_STAT_KEYWR               /*!< All 16 bytes written to AESAKEY */
1401 /* AESASTAT[AESDINWR] Bits */
1402 #define AESDINWR_OFS                             AES256_STAT_DINWR_OFS           /*!< AESDINWR Offset */
1403 #define AESDINWR                                 AES256_STAT_DINWR               /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
1404 /* AESASTAT[AESDOUTRD] Bits */
1405 #define AESDOUTRD_OFS                            AES256_STAT_DOUTRD_OFS          /*!< AESDOUTRD Offset */
1406 #define AESDOUTRD                                AES256_STAT_DOUTRD              /*!< All 16 bytes read from AESADOUT */
1407 /* AESASTAT[AESKEYCNT] Bits */
1408 #define AESKEYCNT_OFS                            AES256_STAT_KEYCNT_OFS          /*!< AESKEYCNT Offset */
1409 #define AESKEYCNT_M                              AES256_STAT_KEYCNT_MASK         /*!< Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */
1410 #define AESKEYCNT0                               AES256_STAT_KEYCNT0             /*!< AESKEYCNT Bit 0 */
1411 #define AESKEYCNT1                               AES256_STAT_KEYCNT1             /*!< AESKEYCNT Bit 1 */
1412 #define AESKEYCNT2                               AES256_STAT_KEYCNT2             /*!< AESKEYCNT Bit 2 */
1413 #define AESKEYCNT3                               AES256_STAT_KEYCNT3             /*!< AESKEYCNT Bit 3 */
1414 /* AESASTAT[AESDINCNT] Bits */
1415 #define AESDINCNT_OFS                            AES256_STAT_DINCNT_OFS          /*!< AESDINCNT Offset */
1416 #define AESDINCNT_M                              AES256_STAT_DINCNT_MASK         /*!< Bytes written via AESADIN, AESAXDIN or AESAXIN */
1417 #define AESDINCNT0                               AES256_STAT_DINCNT0             /*!< AESDINCNT Bit 0 */
1418 #define AESDINCNT1                               AES256_STAT_DINCNT1             /*!< AESDINCNT Bit 1 */
1419 #define AESDINCNT2                               AES256_STAT_DINCNT2             /*!< AESDINCNT Bit 2 */
1420 #define AESDINCNT3                               AES256_STAT_DINCNT3             /*!< AESDINCNT Bit 3 */
1421 /* AESASTAT[AESDOUTCNT] Bits */
1422 #define AESDOUTCNT_OFS                           AES256_STAT_DOUTCNT_OFS         /*!< AESDOUTCNT Offset */
1423 #define AESDOUTCNT_M                             AES256_STAT_DOUTCNT_MASK        /*!< Bytes read via AESADOUT */
1424 #define AESDOUTCNT0                              AES256_STAT_DOUTCNT0            /*!< AESDOUTCNT Bit 0 */
1425 #define AESDOUTCNT1                              AES256_STAT_DOUTCNT1            /*!< AESDOUTCNT Bit 1 */
1426 #define AESDOUTCNT2                              AES256_STAT_DOUTCNT2            /*!< AESDOUTCNT Bit 2 */
1427 #define AESDOUTCNT3                              AES256_STAT_DOUTCNT3            /*!< AESDOUTCNT Bit 3 */
1428 /* AESAKEY[AESKEY0] Bits */
1429 #define AESKEY0_OFS                              AES256_KEY_KEY0_OFS             /*!< AESKEY0 Offset */
1430 #define AESKEY0_M                                AES256_KEY_KEY0_MASK            /*!< AES key byte n when AESAKEY is written as half-word */
1431 #define AESKEY00                                 AES256_KEY_KEY00                /*!< AESKEY0 Bit 0 */
1432 #define AESKEY01                                 AES256_KEY_KEY01                /*!< AESKEY0 Bit 1 */
1433 #define AESKEY02                                 AES256_KEY_KEY02                /*!< AESKEY0 Bit 2 */
1434 #define AESKEY03                                 AES256_KEY_KEY03                /*!< AESKEY0 Bit 3 */
1435 #define AESKEY04                                 AES256_KEY_KEY04                /*!< AESKEY0 Bit 4 */
1436 #define AESKEY05                                 AES256_KEY_KEY05                /*!< AESKEY0 Bit 5 */
1437 #define AESKEY06                                 AES256_KEY_KEY06                /*!< AESKEY0 Bit 6 */
1438 #define AESKEY07                                 AES256_KEY_KEY07                /*!< AESKEY0 Bit 7 */
1439 /* AESAKEY[AESKEY1] Bits */
1440 #define AESKEY1_OFS                              AES256_KEY_KEY1_OFS             /*!< AESKEY1 Offset */
1441 #define AESKEY1_M                                AES256_KEY_KEY1_MASK            /*!< AES key byte n+1 when AESAKEY is written as half-word */
1442 #define AESKEY10                                 AES256_KEY_KEY10                /*!< AESKEY1 Bit 0 */
1443 #define AESKEY11                                 AES256_KEY_KEY11                /*!< AESKEY1 Bit 1 */
1444 #define AESKEY12                                 AES256_KEY_KEY12                /*!< AESKEY1 Bit 2 */
1445 #define AESKEY13                                 AES256_KEY_KEY13                /*!< AESKEY1 Bit 3 */
1446 #define AESKEY14                                 AES256_KEY_KEY14                /*!< AESKEY1 Bit 4 */
1447 #define AESKEY15                                 AES256_KEY_KEY15                /*!< AESKEY1 Bit 5 */
1448 #define AESKEY16                                 AES256_KEY_KEY16                /*!< AESKEY1 Bit 6 */
1449 #define AESKEY17                                 AES256_KEY_KEY17                /*!< AESKEY1 Bit 7 */
1450 /* AESADIN[AESDIN0] Bits */
1451 #define AESDIN0_OFS                              AES256_DIN_DIN0_OFS             /*!< AESDIN0 Offset */
1452 #define AESDIN0_M                                AES256_DIN_DIN0_MASK            /*!< AES data in byte n when AESADIN is written as half-word */
1453 #define AESDIN00                                 AES256_DIN_DIN00                /*!< AESDIN0 Bit 0 */
1454 #define AESDIN01                                 AES256_DIN_DIN01                /*!< AESDIN0 Bit 1 */
1455 #define AESDIN02                                 AES256_DIN_DIN02                /*!< AESDIN0 Bit 2 */
1456 #define AESDIN03                                 AES256_DIN_DIN03                /*!< AESDIN0 Bit 3 */
1457 #define AESDIN04                                 AES256_DIN_DIN04                /*!< AESDIN0 Bit 4 */
1458 #define AESDIN05                                 AES256_DIN_DIN05                /*!< AESDIN0 Bit 5 */
1459 #define AESDIN06                                 AES256_DIN_DIN06                /*!< AESDIN0 Bit 6 */
1460 #define AESDIN07                                 AES256_DIN_DIN07                /*!< AESDIN0 Bit 7 */
1461 /* AESADIN[AESDIN1] Bits */
1462 #define AESDIN1_OFS                              AES256_DIN_DIN1_OFS             /*!< AESDIN1 Offset */
1463 #define AESDIN1_M                                AES256_DIN_DIN1_MASK            /*!< AES data in byte n+1 when AESADIN is written as half-word */
1464 #define AESDIN10                                 AES256_DIN_DIN10                /*!< AESDIN1 Bit 0 */
1465 #define AESDIN11                                 AES256_DIN_DIN11                /*!< AESDIN1 Bit 1 */
1466 #define AESDIN12                                 AES256_DIN_DIN12                /*!< AESDIN1 Bit 2 */
1467 #define AESDIN13                                 AES256_DIN_DIN13                /*!< AESDIN1 Bit 3 */
1468 #define AESDIN14                                 AES256_DIN_DIN14                /*!< AESDIN1 Bit 4 */
1469 #define AESDIN15                                 AES256_DIN_DIN15                /*!< AESDIN1 Bit 5 */
1470 #define AESDIN16                                 AES256_DIN_DIN16                /*!< AESDIN1 Bit 6 */
1471 #define AESDIN17                                 AES256_DIN_DIN17                /*!< AESDIN1 Bit 7 */
1472 /* AESADOUT[AESDOUT0] Bits */
1473 #define AESDOUT0_OFS                             AES256_DOUT_DOUT0_OFS           /*!< AESDOUT0 Offset */
1474 #define AESDOUT0_M                               AES256_DOUT_DOUT0_MASK          /*!< AES data out byte n when AESADOUT is read as half-word */
1475 #define AESDOUT00                                AES256_DOUT_DOUT00              /*!< AESDOUT0 Bit 0 */
1476 #define AESDOUT01                                AES256_DOUT_DOUT01              /*!< AESDOUT0 Bit 1 */
1477 #define AESDOUT02                                AES256_DOUT_DOUT02              /*!< AESDOUT0 Bit 2 */
1478 #define AESDOUT03                                AES256_DOUT_DOUT03              /*!< AESDOUT0 Bit 3 */
1479 #define AESDOUT04                                AES256_DOUT_DOUT04              /*!< AESDOUT0 Bit 4 */
1480 #define AESDOUT05                                AES256_DOUT_DOUT05              /*!< AESDOUT0 Bit 5 */
1481 #define AESDOUT06                                AES256_DOUT_DOUT06              /*!< AESDOUT0 Bit 6 */
1482 #define AESDOUT07                                AES256_DOUT_DOUT07              /*!< AESDOUT0 Bit 7 */
1483 /* AESADOUT[AESDOUT1] Bits */
1484 #define AESDOUT1_OFS                             AES256_DOUT_DOUT1_OFS           /*!< AESDOUT1 Offset */
1485 #define AESDOUT1_M                               AES256_DOUT_DOUT1_MASK          /*!< AES data out byte n+1 when AESADOUT is read as half-word */
1486 #define AESDOUT10                                AES256_DOUT_DOUT10              /*!< AESDOUT1 Bit 0 */
1487 #define AESDOUT11                                AES256_DOUT_DOUT11              /*!< AESDOUT1 Bit 1 */
1488 #define AESDOUT12                                AES256_DOUT_DOUT12              /*!< AESDOUT1 Bit 2 */
1489 #define AESDOUT13                                AES256_DOUT_DOUT13              /*!< AESDOUT1 Bit 3 */
1490 #define AESDOUT14                                AES256_DOUT_DOUT14              /*!< AESDOUT1 Bit 4 */
1491 #define AESDOUT15                                AES256_DOUT_DOUT15              /*!< AESDOUT1 Bit 5 */
1492 #define AESDOUT16                                AES256_DOUT_DOUT16              /*!< AESDOUT1 Bit 6 */
1493 #define AESDOUT17                                AES256_DOUT_DOUT17              /*!< AESDOUT1 Bit 7 */
1494 /* AESAXDIN[AESXDIN0] Bits */
1495 #define AESXDIN0_OFS                             AES256_XDIN_XDIN0_OFS           /*!< AESXDIN0 Offset */
1496 #define AESXDIN0_M                               AES256_XDIN_XDIN0_MASK          /*!< AES data in byte n when AESAXDIN is written as half-word */
1497 #define AESXDIN00                                AES256_XDIN_XDIN00              /*!< AESXDIN0 Bit 0 */
1498 #define AESXDIN01                                AES256_XDIN_XDIN01              /*!< AESXDIN0 Bit 1 */
1499 #define AESXDIN02                                AES256_XDIN_XDIN02              /*!< AESXDIN0 Bit 2 */
1500 #define AESXDIN03                                AES256_XDIN_XDIN03              /*!< AESXDIN0 Bit 3 */
1501 #define AESXDIN04                                AES256_XDIN_XDIN04              /*!< AESXDIN0 Bit 4 */
1502 #define AESXDIN05                                AES256_XDIN_XDIN05              /*!< AESXDIN0 Bit 5 */
1503 #define AESXDIN06                                AES256_XDIN_XDIN06              /*!< AESXDIN0 Bit 6 */
1504 #define AESXDIN07                                AES256_XDIN_XDIN07              /*!< AESXDIN0 Bit 7 */
1505 /* AESAXDIN[AESXDIN1] Bits */
1506 #define AESXDIN1_OFS                             AES256_XDIN_XDIN1_OFS           /*!< AESXDIN1 Offset */
1507 #define AESXDIN1_M                               AES256_XDIN_XDIN1_MASK          /*!< AES data in byte n+1 when AESAXDIN is written as half-word */
1508 #define AESXDIN10                                AES256_XDIN_XDIN10              /*!< AESXDIN1 Bit 0 */
1509 #define AESXDIN11                                AES256_XDIN_XDIN11              /*!< AESXDIN1 Bit 1 */
1510 #define AESXDIN12                                AES256_XDIN_XDIN12              /*!< AESXDIN1 Bit 2 */
1511 #define AESXDIN13                                AES256_XDIN_XDIN13              /*!< AESXDIN1 Bit 3 */
1512 #define AESXDIN14                                AES256_XDIN_XDIN14              /*!< AESXDIN1 Bit 4 */
1513 #define AESXDIN15                                AES256_XDIN_XDIN15              /*!< AESXDIN1 Bit 5 */
1514 #define AESXDIN16                                AES256_XDIN_XDIN16              /*!< AESXDIN1 Bit 6 */
1515 #define AESXDIN17                                AES256_XDIN_XDIN17              /*!< AESXDIN1 Bit 7 */
1516 /* AESAXIN[AESXIN0] Bits */
1517 #define AESXIN0_OFS                              AES256_XIN_XIN0_OFS             /*!< AESXIN0 Offset */
1518 #define AESXIN0_M                                AES256_XIN_XIN0_MASK            /*!< AES data in byte n when AESAXIN is written as half-word */
1519 #define AESXIN00                                 AES256_XIN_XIN00                /*!< AESXIN0 Bit 0 */
1520 #define AESXIN01                                 AES256_XIN_XIN01                /*!< AESXIN0 Bit 1 */
1521 #define AESXIN02                                 AES256_XIN_XIN02                /*!< AESXIN0 Bit 2 */
1522 #define AESXIN03                                 AES256_XIN_XIN03                /*!< AESXIN0 Bit 3 */
1523 #define AESXIN04                                 AES256_XIN_XIN04                /*!< AESXIN0 Bit 4 */
1524 #define AESXIN05                                 AES256_XIN_XIN05                /*!< AESXIN0 Bit 5 */
1525 #define AESXIN06                                 AES256_XIN_XIN06                /*!< AESXIN0 Bit 6 */
1526 #define AESXIN07                                 AES256_XIN_XIN07                /*!< AESXIN0 Bit 7 */
1527 /* AESAXIN[AESXIN1] Bits */
1528 #define AESXIN1_OFS                              AES256_XIN_XIN1_OFS             /*!< AESXIN1 Offset */
1529 #define AESXIN1_M                                AES256_XIN_XIN1_MASK            /*!< AES data in byte n+1 when AESAXIN is written as half-word */
1530 #define AESXIN10                                 AES256_XIN_XIN10                /*!< AESXIN1 Bit 0 */
1531 #define AESXIN11                                 AES256_XIN_XIN11                /*!< AESXIN1 Bit 1 */
1532 #define AESXIN12                                 AES256_XIN_XIN12                /*!< AESXIN1 Bit 2 */
1533 #define AESXIN13                                 AES256_XIN_XIN13                /*!< AESXIN1 Bit 3 */
1534 #define AESXIN14                                 AES256_XIN_XIN14                /*!< AESXIN1 Bit 4 */
1535 #define AESXIN15                                 AES256_XIN_XIN15                /*!< AESXIN1 Bit 5 */
1536 #define AESXIN16                                 AES256_XIN_XIN16                /*!< AESXIN1 Bit 6 */
1537 #define AESXIN17                                 AES256_XIN_XIN17                /*!< AESXIN1 Bit 7 */
1538 
1539 /******************************************************************************
1540 * CAPTIO Bits (legacy section)
1541 ******************************************************************************/
1542 /* CAPTIO0CTL[CAPTIOPISEL] Bits */
1543 #define CAPTIOPISEL_OFS                          CAPTIO_CTL_PISEL_OFS            /*!< CAPTIOPISEL Offset */
1544 #define CAPTIOPISEL_M                            CAPTIO_CTL_PISEL_MASK           /*!< Capacitive Touch IO pin select */
1545 #define CAPTIOPISEL0                             CAPTIO_CTL_PISEL0               /*!< CAPTIOPISEL Bit 0 */
1546 #define CAPTIOPISEL1                             CAPTIO_CTL_PISEL1               /*!< CAPTIOPISEL Bit 1 */
1547 #define CAPTIOPISEL2                             CAPTIO_CTL_PISEL2               /*!< CAPTIOPISEL Bit 2 */
1548 #define CAPTIOPISEL_0                            CAPTIO_CTL_PISEL_0              /*!< Px.0 */
1549 #define CAPTIOPISEL_1                            CAPTIO_CTL_PISEL_1              /*!< Px.1 */
1550 #define CAPTIOPISEL_2                            CAPTIO_CTL_PISEL_2              /*!< Px.2 */
1551 #define CAPTIOPISEL_3                            CAPTIO_CTL_PISEL_3              /*!< Px.3 */
1552 #define CAPTIOPISEL_4                            CAPTIO_CTL_PISEL_4              /*!< Px.4 */
1553 #define CAPTIOPISEL_5                            CAPTIO_CTL_PISEL_5              /*!< Px.5 */
1554 #define CAPTIOPISEL_6                            CAPTIO_CTL_PISEL_6              /*!< Px.6 */
1555 #define CAPTIOPISEL_7                            CAPTIO_CTL_PISEL_7              /*!< Px.7 */
1556 /* CAPTIO0CTL[CAPTIOPOSEL] Bits */
1557 #define CAPTIOPOSEL_OFS                          CAPTIO_CTL_POSEL_OFS            /*!< CAPTIOPOSEL Offset */
1558 #define CAPTIOPOSEL_M                            CAPTIO_CTL_POSEL_MASK           /*!< Capacitive Touch IO port select */
1559 #define CAPTIOPOSEL0                             CAPTIO_CTL_POSEL0               /*!< CAPTIOPOSEL Bit 0 */
1560 #define CAPTIOPOSEL1                             CAPTIO_CTL_POSEL1               /*!< CAPTIOPOSEL Bit 1 */
1561 #define CAPTIOPOSEL2                             CAPTIO_CTL_POSEL2               /*!< CAPTIOPOSEL Bit 2 */
1562 #define CAPTIOPOSEL3                             CAPTIO_CTL_POSEL3               /*!< CAPTIOPOSEL Bit 3 */
1563 #define CAPTIOPOSEL_0                            CAPTIO_CTL_POSEL_0              /*!< Px = PJ */
1564 #define CAPTIOPOSEL_1                            CAPTIO_CTL_POSEL_1              /*!< Px = P1 */
1565 #define CAPTIOPOSEL_2                            CAPTIO_CTL_POSEL_2              /*!< Px = P2 */
1566 #define CAPTIOPOSEL_3                            CAPTIO_CTL_POSEL_3              /*!< Px = P3 */
1567 #define CAPTIOPOSEL_4                            CAPTIO_CTL_POSEL_4              /*!< Px = P4 */
1568 #define CAPTIOPOSEL_5                            CAPTIO_CTL_POSEL_5              /*!< Px = P5 */
1569 #define CAPTIOPOSEL_6                            CAPTIO_CTL_POSEL_6              /*!< Px = P6 */
1570 #define CAPTIOPOSEL_7                            CAPTIO_CTL_POSEL_7              /*!< Px = P7 */
1571 #define CAPTIOPOSEL_8                            CAPTIO_CTL_POSEL_8              /*!< Px = P8 */
1572 #define CAPTIOPOSEL_9                            CAPTIO_CTL_POSEL_9              /*!< Px = P9 */
1573 #define CAPTIOPOSEL_10                           CAPTIO_CTL_POSEL_10             /*!< Px = P10 */
1574 #define CAPTIOPOSEL_11                           CAPTIO_CTL_POSEL_11             /*!< Px = P11 */
1575 #define CAPTIOPOSEL_12                           CAPTIO_CTL_POSEL_12             /*!< Px = P12 */
1576 #define CAPTIOPOSEL_13                           CAPTIO_CTL_POSEL_13             /*!< Px = P13 */
1577 #define CAPTIOPOSEL_14                           CAPTIO_CTL_POSEL_14             /*!< Px = P14 */
1578 #define CAPTIOPOSEL_15                           CAPTIO_CTL_POSEL_15             /*!< Px = P15 */
1579 #define CAPTIOPOSEL__PJ                          CAPTIO_CTL_POSEL__PJ            /*!< Px = PJ */
1580 #define CAPTIOPOSEL__P1                          CAPTIO_CTL_POSEL__P1            /*!< Px = P1 */
1581 #define CAPTIOPOSEL__P2                          CAPTIO_CTL_POSEL__P2            /*!< Px = P2 */
1582 #define CAPTIOPOSEL__P3                          CAPTIO_CTL_POSEL__P3            /*!< Px = P3 */
1583 #define CAPTIOPOSEL__P4                          CAPTIO_CTL_POSEL__P4            /*!< Px = P4 */
1584 #define CAPTIOPOSEL__P5                          CAPTIO_CTL_POSEL__P5            /*!< Px = P5 */
1585 #define CAPTIOPOSEL__P6                          CAPTIO_CTL_POSEL__P6            /*!< Px = P6 */
1586 #define CAPTIOPOSEL__P7                          CAPTIO_CTL_POSEL__P7            /*!< Px = P7 */
1587 #define CAPTIOPOSEL__P8                          CAPTIO_CTL_POSEL__P8            /*!< Px = P8 */
1588 #define CAPTIOPOSEL__P9                          CAPTIO_CTL_POSEL__P9            /*!< Px = P9 */
1589 #define CAPTIOPOSEL__P10                         CAPTIO_CTL_POSEL__P10           /*!< Px = P10 */
1590 #define CAPTIOPOSEL__P11                         CAPTIO_CTL_POSEL__P11           /*!< Px = P11 */
1591 #define CAPTIOPOSEL__P12                         CAPTIO_CTL_POSEL__P12           /*!< Px = P12 */
1592 #define CAPTIOPOSEL__P13                         CAPTIO_CTL_POSEL__P13           /*!< Px = P13 */
1593 #define CAPTIOPOSEL__P14                         CAPTIO_CTL_POSEL__P14           /*!< Px = P14 */
1594 #define CAPTIOPOSEL__P15                         CAPTIO_CTL_POSEL__P15           /*!< Px = P15 */
1595 /* CAPTIO0CTL[CAPTIOEN] Bits */
1596 #define CAPTIOEN_OFS                             CAPTIO_CTL_EN_OFS               /*!< CAPTIOEN Offset */
1597 #define CAPTIOEN                                 CAPTIO_CTL_EN                   /*!< Capacitive Touch IO enable */
1598 /* CAPTIO0CTL[CAPTIOSTATE] Bits */
1599 #define CAPTIOSTATE_OFS                          CAPTIO_CTL_STATE_OFS            /*!< CAPTIOSTATE Offset */
1600 #define CAPTIOSTATE                              CAPTIO_CTL_STATE                /*!< Capacitive Touch IO state */
1601 
1602 /******************************************************************************
1603 * COMP_E Bits (legacy section)
1604 ******************************************************************************/
1605 /* CE0CTL0[CEIPSEL] Bits */
1606 #define CEIPSEL_OFS                              COMP_E_CTL0_IPSEL_OFS           /*!< CEIPSEL Offset */
1607 #define CEIPSEL_M                                COMP_E_CTL0_IPSEL_MASK          /*!< Channel input selected for the V+ terminal */
1608 #define CEIPSEL0                                 COMP_E_CTL0_IPSEL0              /*!< CEIPSEL Bit 0 */
1609 #define CEIPSEL1                                 COMP_E_CTL0_IPSEL1              /*!< CEIPSEL Bit 1 */
1610 #define CEIPSEL2                                 COMP_E_CTL0_IPSEL2              /*!< CEIPSEL Bit 2 */
1611 #define CEIPSEL3                                 COMP_E_CTL0_IPSEL3              /*!< CEIPSEL Bit 3 */
1612 #define CEIPSEL_0                                COMP_E_CTL0_IPSEL_0             /*!< Channel 0 selected */
1613 #define CEIPSEL_1                                COMP_E_CTL0_IPSEL_1             /*!< Channel 1 selected */
1614 #define CEIPSEL_2                                COMP_E_CTL0_IPSEL_2             /*!< Channel 2 selected */
1615 #define CEIPSEL_3                                COMP_E_CTL0_IPSEL_3             /*!< Channel 3 selected */
1616 #define CEIPSEL_4                                COMP_E_CTL0_IPSEL_4             /*!< Channel 4 selected */
1617 #define CEIPSEL_5                                COMP_E_CTL0_IPSEL_5             /*!< Channel 5 selected */
1618 #define CEIPSEL_6                                COMP_E_CTL0_IPSEL_6             /*!< Channel 6 selected */
1619 #define CEIPSEL_7                                COMP_E_CTL0_IPSEL_7             /*!< Channel 7 selected */
1620 #define CEIPSEL_8                                COMP_E_CTL0_IPSEL_8             /*!< Channel 8 selected */
1621 #define CEIPSEL_9                                COMP_E_CTL0_IPSEL_9             /*!< Channel 9 selected */
1622 #define CEIPSEL_10                               COMP_E_CTL0_IPSEL_10            /*!< Channel 10 selected */
1623 #define CEIPSEL_11                               COMP_E_CTL0_IPSEL_11            /*!< Channel 11 selected */
1624 #define CEIPSEL_12                               COMP_E_CTL0_IPSEL_12            /*!< Channel 12 selected */
1625 #define CEIPSEL_13                               COMP_E_CTL0_IPSEL_13            /*!< Channel 13 selected */
1626 #define CEIPSEL_14                               COMP_E_CTL0_IPSEL_14            /*!< Channel 14 selected */
1627 #define CEIPSEL_15                               COMP_E_CTL0_IPSEL_15            /*!< Channel 15 selected */
1628 /* CE0CTL0[CEIPEN] Bits */
1629 #define CEIPEN_OFS                               COMP_E_CTL0_IPEN_OFS            /*!< CEIPEN Offset */
1630 #define CEIPEN                                   COMP_E_CTL0_IPEN                /*!< Channel input enable for the V+ terminal */
1631 /* CE0CTL0[CEIMSEL] Bits */
1632 #define CEIMSEL_OFS                              COMP_E_CTL0_IMSEL_OFS           /*!< CEIMSEL Offset */
1633 #define CEIMSEL_M                                COMP_E_CTL0_IMSEL_MASK          /*!< Channel input selected for the - terminal */
1634 #define CEIMSEL0                                 COMP_E_CTL0_IMSEL0              /*!< CEIMSEL Bit 0 */
1635 #define CEIMSEL1                                 COMP_E_CTL0_IMSEL1              /*!< CEIMSEL Bit 1 */
1636 #define CEIMSEL2                                 COMP_E_CTL0_IMSEL2              /*!< CEIMSEL Bit 2 */
1637 #define CEIMSEL3                                 COMP_E_CTL0_IMSEL3              /*!< CEIMSEL Bit 3 */
1638 #define CEIMSEL_0                                COMP_E_CTL0_IMSEL_0             /*!< Channel 0 selected */
1639 #define CEIMSEL_1                                COMP_E_CTL0_IMSEL_1             /*!< Channel 1 selected */
1640 #define CEIMSEL_2                                COMP_E_CTL0_IMSEL_2             /*!< Channel 2 selected */
1641 #define CEIMSEL_3                                COMP_E_CTL0_IMSEL_3             /*!< Channel 3 selected */
1642 #define CEIMSEL_4                                COMP_E_CTL0_IMSEL_4             /*!< Channel 4 selected */
1643 #define CEIMSEL_5                                COMP_E_CTL0_IMSEL_5             /*!< Channel 5 selected */
1644 #define CEIMSEL_6                                COMP_E_CTL0_IMSEL_6             /*!< Channel 6 selected */
1645 #define CEIMSEL_7                                COMP_E_CTL0_IMSEL_7             /*!< Channel 7 selected */
1646 #define CEIMSEL_8                                COMP_E_CTL0_IMSEL_8             /*!< Channel 8 selected */
1647 #define CEIMSEL_9                                COMP_E_CTL0_IMSEL_9             /*!< Channel 9 selected */
1648 #define CEIMSEL_10                               COMP_E_CTL0_IMSEL_10            /*!< Channel 10 selected */
1649 #define CEIMSEL_11                               COMP_E_CTL0_IMSEL_11            /*!< Channel 11 selected */
1650 #define CEIMSEL_12                               COMP_E_CTL0_IMSEL_12            /*!< Channel 12 selected */
1651 #define CEIMSEL_13                               COMP_E_CTL0_IMSEL_13            /*!< Channel 13 selected */
1652 #define CEIMSEL_14                               COMP_E_CTL0_IMSEL_14            /*!< Channel 14 selected */
1653 #define CEIMSEL_15                               COMP_E_CTL0_IMSEL_15            /*!< Channel 15 selected */
1654 /* CE0CTL0[CEIMEN] Bits */
1655 #define CEIMEN_OFS                               COMP_E_CTL0_IMEN_OFS            /*!< CEIMEN Offset */
1656 #define CEIMEN                                   COMP_E_CTL0_IMEN                /*!< Channel input enable for the - terminal */
1657 /* CE0CTL1[CEOUT] Bits */
1658 #define CEOUT_OFS                                COMP_E_CTL1_OUT_OFS             /*!< CEOUT Offset */
1659 #define CEOUT                                    COMP_E_CTL1_OUT                 /*!< Comparator output value */
1660 /* CE0CTL1[CEOUTPOL] Bits */
1661 #define CEOUTPOL_OFS                             COMP_E_CTL1_OUTPOL_OFS          /*!< CEOUTPOL Offset */
1662 #define CEOUTPOL                                 COMP_E_CTL1_OUTPOL              /*!< Comparator output polarity */
1663 /* CE0CTL1[CEF] Bits */
1664 #define CEF_OFS                                  COMP_E_CTL1_F_OFS               /*!< CEF Offset */
1665 #define CEF                                      COMP_E_CTL1_F                   /*!< Comparator output filter */
1666 /* CE0CTL1[CEIES] Bits */
1667 #define CEIES_OFS                                COMP_E_CTL1_IES_OFS             /*!< CEIES Offset */
1668 #define CEIES                                    COMP_E_CTL1_IES                 /*!< Interrupt edge select for CEIIFG and CEIFG */
1669 /* CE0CTL1[CESHORT] Bits */
1670 #define CESHORT_OFS                              COMP_E_CTL1_SHORT_OFS           /*!< CESHORT Offset */
1671 #define CESHORT                                  COMP_E_CTL1_SHORT               /*!< Input short */
1672 /* CE0CTL1[CEEX] Bits */
1673 #define CEEX_OFS                                 COMP_E_CTL1_EX_OFS              /*!< CEEX Offset */
1674 #define CEEX                                     COMP_E_CTL1_EX                  /*!< Exchange */
1675 /* CE0CTL1[CEFDLY] Bits */
1676 #define CEFDLY_OFS                               COMP_E_CTL1_FDLY_OFS            /*!< CEFDLY Offset */
1677 #define CEFDLY_M                                 COMP_E_CTL1_FDLY_MASK           /*!< Filter delay */
1678 #define CEFDLY0                                  COMP_E_CTL1_FDLY0               /*!< CEFDLY Bit 0 */
1679 #define CEFDLY1                                  COMP_E_CTL1_FDLY1               /*!< CEFDLY Bit 1 */
1680 #define CEFDLY_0                                 COMP_E_CTL1_FDLY_0              /*!< Typical filter delay of TBD (450) ns */
1681 #define CEFDLY_1                                 COMP_E_CTL1_FDLY_1              /*!< Typical filter delay of TBD (900) ns */
1682 #define CEFDLY_2                                 COMP_E_CTL1_FDLY_2              /*!< Typical filter delay of TBD (1800) ns */
1683 #define CEFDLY_3                                 COMP_E_CTL1_FDLY_3              /*!< Typical filter delay of TBD (3600) ns */
1684 /* CE0CTL1[CEPWRMD] Bits */
1685 #define CEPWRMD_OFS                              COMP_E_CTL1_PWRMD_OFS           /*!< CEPWRMD Offset */
1686 #define CEPWRMD_M                                COMP_E_CTL1_PWRMD_MASK          /*!< Power Mode */
1687 #define CEPWRMD0                                 COMP_E_CTL1_PWRMD0              /*!< CEPWRMD Bit 0 */
1688 #define CEPWRMD1                                 COMP_E_CTL1_PWRMD1              /*!< CEPWRMD Bit 1 */
1689 #define CEPWRMD_0                                COMP_E_CTL1_PWRMD_0             /*!< High-speed mode */
1690 #define CEPWRMD_1                                COMP_E_CTL1_PWRMD_1             /*!< Normal mode */
1691 #define CEPWRMD_2                                COMP_E_CTL1_PWRMD_2             /*!< Ultra-low power mode */
1692 /* CE0CTL1[CEON] Bits */
1693 #define CEON_OFS                                 COMP_E_CTL1_ON_OFS              /*!< CEON Offset */
1694 #define CEON                                     COMP_E_CTL1_ON                  /*!< Comparator On */
1695 /* CE0CTL1[CEMRVL] Bits */
1696 #define CEMRVL_OFS                               COMP_E_CTL1_MRVL_OFS            /*!< CEMRVL Offset */
1697 #define CEMRVL                                   COMP_E_CTL1_MRVL                /*!< This bit is valid of CEMRVS is set to 1 */
1698 /* CE0CTL1[CEMRVS] Bits */
1699 #define CEMRVS_OFS                               COMP_E_CTL1_MRVS_OFS            /*!< CEMRVS Offset */
1700 #define CEMRVS                                   COMP_E_CTL1_MRVS
1701 /* CE0CTL2[CEREF0] Bits */
1702 #define CEREF0_OFS                               COMP_E_CTL2_REF0_OFS            /*!< CEREF0 Offset */
1703 #define CEREF0_M                                 COMP_E_CTL2_REF0_MASK           /*!< Reference resistor tap 0 */
1704 #define CEREF00                                  COMP_E_CTL2_REF00               /*!< CEREF0 Bit 0 */
1705 #define CEREF01                                  COMP_E_CTL2_REF01               /*!< CEREF0 Bit 1 */
1706 #define CEREF02                                  COMP_E_CTL2_REF02               /*!< CEREF0 Bit 2 */
1707 #define CEREF03                                  COMP_E_CTL2_REF03               /*!< CEREF0 Bit 3 */
1708 #define CEREF04                                  COMP_E_CTL2_REF04               /*!< CEREF0 Bit 4 */
1709 #define CEREF0_0                                 COMP_E_CTL2_REF0_0              /*!< Reference resistor tap for setting 0. */
1710 #define CEREF0_1                                 COMP_E_CTL2_REF0_1              /*!< Reference resistor tap for setting 1. */
1711 #define CEREF0_2                                 COMP_E_CTL2_REF0_2              /*!< Reference resistor tap for setting 2. */
1712 #define CEREF0_3                                 COMP_E_CTL2_REF0_3              /*!< Reference resistor tap for setting 3. */
1713 #define CEREF0_4                                 COMP_E_CTL2_REF0_4              /*!< Reference resistor tap for setting 4. */
1714 #define CEREF0_5                                 COMP_E_CTL2_REF0_5              /*!< Reference resistor tap for setting 5. */
1715 #define CEREF0_6                                 COMP_E_CTL2_REF0_6              /*!< Reference resistor tap for setting 6. */
1716 #define CEREF0_7                                 COMP_E_CTL2_REF0_7              /*!< Reference resistor tap for setting 7. */
1717 #define CEREF0_8                                 COMP_E_CTL2_REF0_8              /*!< Reference resistor tap for setting 8. */
1718 #define CEREF0_9                                 COMP_E_CTL2_REF0_9              /*!< Reference resistor tap for setting 9. */
1719 #define CEREF0_10                                COMP_E_CTL2_REF0_10             /*!< Reference resistor tap for setting 10. */
1720 #define CEREF0_11                                COMP_E_CTL2_REF0_11             /*!< Reference resistor tap for setting 11. */
1721 #define CEREF0_12                                COMP_E_CTL2_REF0_12             /*!< Reference resistor tap for setting 12. */
1722 #define CEREF0_13                                COMP_E_CTL2_REF0_13             /*!< Reference resistor tap for setting 13. */
1723 #define CEREF0_14                                COMP_E_CTL2_REF0_14             /*!< Reference resistor tap for setting 14. */
1724 #define CEREF0_15                                COMP_E_CTL2_REF0_15             /*!< Reference resistor tap for setting 15. */
1725 #define CEREF0_16                                COMP_E_CTL2_REF0_16             /*!< Reference resistor tap for setting 16. */
1726 #define CEREF0_17                                COMP_E_CTL2_REF0_17             /*!< Reference resistor tap for setting 17. */
1727 #define CEREF0_18                                COMP_E_CTL2_REF0_18             /*!< Reference resistor tap for setting 18. */
1728 #define CEREF0_19                                COMP_E_CTL2_REF0_19             /*!< Reference resistor tap for setting 19. */
1729 #define CEREF0_20                                COMP_E_CTL2_REF0_20             /*!< Reference resistor tap for setting 20. */
1730 #define CEREF0_21                                COMP_E_CTL2_REF0_21             /*!< Reference resistor tap for setting 21. */
1731 #define CEREF0_22                                COMP_E_CTL2_REF0_22             /*!< Reference resistor tap for setting 22. */
1732 #define CEREF0_23                                COMP_E_CTL2_REF0_23             /*!< Reference resistor tap for setting 23. */
1733 #define CEREF0_24                                COMP_E_CTL2_REF0_24             /*!< Reference resistor tap for setting 24. */
1734 #define CEREF0_25                                COMP_E_CTL2_REF0_25             /*!< Reference resistor tap for setting 25. */
1735 #define CEREF0_26                                COMP_E_CTL2_REF0_26             /*!< Reference resistor tap for setting 26. */
1736 #define CEREF0_27                                COMP_E_CTL2_REF0_27             /*!< Reference resistor tap for setting 27. */
1737 #define CEREF0_28                                COMP_E_CTL2_REF0_28             /*!< Reference resistor tap for setting 28. */
1738 #define CEREF0_29                                COMP_E_CTL2_REF0_29             /*!< Reference resistor tap for setting 29. */
1739 #define CEREF0_30                                COMP_E_CTL2_REF0_30             /*!< Reference resistor tap for setting 30. */
1740 #define CEREF0_31                                COMP_E_CTL2_REF0_31             /*!< Reference resistor tap for setting 31. */
1741 /* CE0CTL2[CERSEL] Bits */
1742 #define CERSEL_OFS                               COMP_E_CTL2_RSEL_OFS            /*!< CERSEL Offset */
1743 #define CERSEL                                   COMP_E_CTL2_RSEL                /*!< Reference select */
1744 /* CE0CTL2[CERS] Bits */
1745 #define CERS_OFS                                 COMP_E_CTL2_RS_OFS              /*!< CERS Offset */
1746 #define CERS_M                                   COMP_E_CTL2_RS_MASK             /*!< Reference source */
1747 #define CERS0                                    COMP_E_CTL2_RS0                 /*!< CERS Bit 0 */
1748 #define CERS1                                    COMP_E_CTL2_RS1                 /*!< CERS Bit 1 */
1749 #define CERS_0                                   COMP_E_CTL2_RS_0                /*!< No current is drawn by the reference circuitry */
1750 #define CERS_1                                   COMP_E_CTL2_RS_1                /*!< VCC applied to the resistor ladder */
1751 #define CERS_2                                   COMP_E_CTL2_RS_2                /*!< Shared reference voltage applied to the resistor ladder */
1752 #define CERS_3                                   COMP_E_CTL2_RS_3                /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */
1753 /* CE0CTL2[CEREF1] Bits */
1754 #define CEREF1_OFS                               COMP_E_CTL2_REF1_OFS            /*!< CEREF1 Offset */
1755 #define CEREF1_M                                 COMP_E_CTL2_REF1_MASK           /*!< Reference resistor tap 1 */
1756 #define CEREF10                                  COMP_E_CTL2_REF10               /*!< CEREF1 Bit 0 */
1757 #define CEREF11                                  COMP_E_CTL2_REF11               /*!< CEREF1 Bit 1 */
1758 #define CEREF12                                  COMP_E_CTL2_REF12               /*!< CEREF1 Bit 2 */
1759 #define CEREF13                                  COMP_E_CTL2_REF13               /*!< CEREF1 Bit 3 */
1760 #define CEREF14                                  COMP_E_CTL2_REF14               /*!< CEREF1 Bit 4 */
1761 #define CEREF1_0                                 COMP_E_CTL2_REF1_0              /*!< Reference resistor tap for setting 0. */
1762 #define CEREF1_1                                 COMP_E_CTL2_REF1_1              /*!< Reference resistor tap for setting 1. */
1763 #define CEREF1_2                                 COMP_E_CTL2_REF1_2              /*!< Reference resistor tap for setting 2. */
1764 #define CEREF1_3                                 COMP_E_CTL2_REF1_3              /*!< Reference resistor tap for setting 3. */
1765 #define CEREF1_4                                 COMP_E_CTL2_REF1_4              /*!< Reference resistor tap for setting 4. */
1766 #define CEREF1_5                                 COMP_E_CTL2_REF1_5              /*!< Reference resistor tap for setting 5. */
1767 #define CEREF1_6                                 COMP_E_CTL2_REF1_6              /*!< Reference resistor tap for setting 6. */
1768 #define CEREF1_7                                 COMP_E_CTL2_REF1_7              /*!< Reference resistor tap for setting 7. */
1769 #define CEREF1_8                                 COMP_E_CTL2_REF1_8              /*!< Reference resistor tap for setting 8. */
1770 #define CEREF1_9                                 COMP_E_CTL2_REF1_9              /*!< Reference resistor tap for setting 9. */
1771 #define CEREF1_10                                COMP_E_CTL2_REF1_10             /*!< Reference resistor tap for setting 10. */
1772 #define CEREF1_11                                COMP_E_CTL2_REF1_11             /*!< Reference resistor tap for setting 11. */
1773 #define CEREF1_12                                COMP_E_CTL2_REF1_12             /*!< Reference resistor tap for setting 12. */
1774 #define CEREF1_13                                COMP_E_CTL2_REF1_13             /*!< Reference resistor tap for setting 13. */
1775 #define CEREF1_14                                COMP_E_CTL2_REF1_14             /*!< Reference resistor tap for setting 14. */
1776 #define CEREF1_15                                COMP_E_CTL2_REF1_15             /*!< Reference resistor tap for setting 15. */
1777 #define CEREF1_16                                COMP_E_CTL2_REF1_16             /*!< Reference resistor tap for setting 16. */
1778 #define CEREF1_17                                COMP_E_CTL2_REF1_17             /*!< Reference resistor tap for setting 17. */
1779 #define CEREF1_18                                COMP_E_CTL2_REF1_18             /*!< Reference resistor tap for setting 18. */
1780 #define CEREF1_19                                COMP_E_CTL2_REF1_19             /*!< Reference resistor tap for setting 19. */
1781 #define CEREF1_20                                COMP_E_CTL2_REF1_20             /*!< Reference resistor tap for setting 20. */
1782 #define CEREF1_21                                COMP_E_CTL2_REF1_21             /*!< Reference resistor tap for setting 21. */
1783 #define CEREF1_22                                COMP_E_CTL2_REF1_22             /*!< Reference resistor tap for setting 22. */
1784 #define CEREF1_23                                COMP_E_CTL2_REF1_23             /*!< Reference resistor tap for setting 23. */
1785 #define CEREF1_24                                COMP_E_CTL2_REF1_24             /*!< Reference resistor tap for setting 24. */
1786 #define CEREF1_25                                COMP_E_CTL2_REF1_25             /*!< Reference resistor tap for setting 25. */
1787 #define CEREF1_26                                COMP_E_CTL2_REF1_26             /*!< Reference resistor tap for setting 26. */
1788 #define CEREF1_27                                COMP_E_CTL2_REF1_27             /*!< Reference resistor tap for setting 27. */
1789 #define CEREF1_28                                COMP_E_CTL2_REF1_28             /*!< Reference resistor tap for setting 28. */
1790 #define CEREF1_29                                COMP_E_CTL2_REF1_29             /*!< Reference resistor tap for setting 29. */
1791 #define CEREF1_30                                COMP_E_CTL2_REF1_30             /*!< Reference resistor tap for setting 30. */
1792 #define CEREF1_31                                COMP_E_CTL2_REF1_31             /*!< Reference resistor tap for setting 31. */
1793 /* CE0CTL2[CEREFL] Bits */
1794 #define CEREFL_OFS                               COMP_E_CTL2_REFL_OFS            /*!< CEREFL Offset */
1795 #define CEREFL_M                                 COMP_E_CTL2_REFL_MASK           /*!< Reference voltage level */
1796 #define CEREFL0                                  COMP_E_CTL2_REFL0               /*!< CEREFL Bit 0 */
1797 #define CEREFL1                                  COMP_E_CTL2_REFL1               /*!< CEREFL Bit 1 */
1798 #define CEREFL_0                                 COMP_E_CTL2_CEREFL_0            /*!< Reference amplifier is disabled. No reference voltage is requested */
1799 #define CEREFL_1                                 COMP_E_CTL2_CEREFL_1            /*!< 1.2 V is selected as shared reference voltage input */
1800 #define CEREFL_2                                 COMP_E_CTL2_CEREFL_2            /*!< 2.0 V is selected as shared reference voltage input */
1801 #define CEREFL_3                                 COMP_E_CTL2_CEREFL_3            /*!< 2.5 V is selected as shared reference voltage input */
1802 #define CEREFL__OFF                              COMP_E_CTL2_REFL__OFF           /*!< Reference amplifier is disabled. No reference voltage is requested */
1803 #define CEREFL__1P2V                             COMP_E_CTL2_REFL__1P2V          /*!< 1.2 V is selected as shared reference voltage input */
1804 #define CEREFL__2P0V                             COMP_E_CTL2_REFL__2P0V          /*!< 2.0 V is selected as shared reference voltage input */
1805 #define CEREFL__2P5V                             COMP_E_CTL2_REFL__2P5V          /*!< 2.5 V is selected as shared reference voltage input */
1806 /* CE0CTL2[CEREFACC] Bits */
1807 #define CEREFACC_OFS                             COMP_E_CTL2_REFACC_OFS          /*!< CEREFACC Offset */
1808 #define CEREFACC                                 COMP_E_CTL2_REFACC              /*!< Reference accuracy */
1809 /* CE0CTL3[CEPD0] Bits */
1810 #define CEPD0_OFS                                COMP_E_CTL3_PD0_OFS             /*!< CEPD0 Offset */
1811 #define CEPD0                                    COMP_E_CTL3_PD0                 /*!< Port disable */
1812 /* CE0CTL3[CEPD1] Bits */
1813 #define CEPD1_OFS                                COMP_E_CTL3_PD1_OFS             /*!< CEPD1 Offset */
1814 #define CEPD1                                    COMP_E_CTL3_PD1                 /*!< Port disable */
1815 /* CE0CTL3[CEPD2] Bits */
1816 #define CEPD2_OFS                                COMP_E_CTL3_PD2_OFS             /*!< CEPD2 Offset */
1817 #define CEPD2                                    COMP_E_CTL3_PD2                 /*!< Port disable */
1818 /* CE0CTL3[CEPD3] Bits */
1819 #define CEPD3_OFS                                COMP_E_CTL3_PD3_OFS             /*!< CEPD3 Offset */
1820 #define CEPD3                                    COMP_E_CTL3_PD3                 /*!< Port disable */
1821 /* CE0CTL3[CEPD4] Bits */
1822 #define CEPD4_OFS                                COMP_E_CTL3_PD4_OFS             /*!< CEPD4 Offset */
1823 #define CEPD4                                    COMP_E_CTL3_PD4                 /*!< Port disable */
1824 /* CE0CTL3[CEPD5] Bits */
1825 #define CEPD5_OFS                                COMP_E_CTL3_PD5_OFS             /*!< CEPD5 Offset */
1826 #define CEPD5                                    COMP_E_CTL3_PD5                 /*!< Port disable */
1827 /* CE0CTL3[CEPD6] Bits */
1828 #define CEPD6_OFS                                COMP_E_CTL3_PD6_OFS             /*!< CEPD6 Offset */
1829 #define CEPD6                                    COMP_E_CTL3_PD6                 /*!< Port disable */
1830 /* CE0CTL3[CEPD7] Bits */
1831 #define CEPD7_OFS                                COMP_E_CTL3_PD7_OFS             /*!< CEPD7 Offset */
1832 #define CEPD7                                    COMP_E_CTL3_PD7                 /*!< Port disable */
1833 /* CE0CTL3[CEPD8] Bits */
1834 #define CEPD8_OFS                                COMP_E_CTL3_PD8_OFS             /*!< CEPD8 Offset */
1835 #define CEPD8                                    COMP_E_CTL3_PD8                 /*!< Port disable */
1836 /* CE0CTL3[CEPD9] Bits */
1837 #define CEPD9_OFS                                COMP_E_CTL3_PD9_OFS             /*!< CEPD9 Offset */
1838 #define CEPD9                                    COMP_E_CTL3_PD9                 /*!< Port disable */
1839 /* CE0CTL3[CEPD10] Bits */
1840 #define CEPD10_OFS                               COMP_E_CTL3_PD10_OFS            /*!< CEPD10 Offset */
1841 #define CEPD10                                   COMP_E_CTL3_PD10                /*!< Port disable */
1842 /* CE0CTL3[CEPD11] Bits */
1843 #define CEPD11_OFS                               COMP_E_CTL3_PD11_OFS            /*!< CEPD11 Offset */
1844 #define CEPD11                                   COMP_E_CTL3_PD11                /*!< Port disable */
1845 /* CE0CTL3[CEPD12] Bits */
1846 #define CEPD12_OFS                               COMP_E_CTL3_PD12_OFS            /*!< CEPD12 Offset */
1847 #define CEPD12                                   COMP_E_CTL3_PD12                /*!< Port disable */
1848 /* CE0CTL3[CEPD13] Bits */
1849 #define CEPD13_OFS                               COMP_E_CTL3_PD13_OFS            /*!< CEPD13 Offset */
1850 #define CEPD13                                   COMP_E_CTL3_PD13                /*!< Port disable */
1851 /* CE0CTL3[CEPD14] Bits */
1852 #define CEPD14_OFS                               COMP_E_CTL3_PD14_OFS            /*!< CEPD14 Offset */
1853 #define CEPD14                                   COMP_E_CTL3_PD14                /*!< Port disable */
1854 /* CE0CTL3[CEPD15] Bits */
1855 #define CEPD15_OFS                               COMP_E_CTL3_PD15_OFS            /*!< CEPD15 Offset */
1856 #define CEPD15                                   COMP_E_CTL3_PD15                /*!< Port disable */
1857 /* CE0INT[CEIFG] Bits */
1858 #define CEIFG_OFS                                COMP_E_INT_IFG_OFS              /*!< CEIFG Offset */
1859 #define CEIFG                                    COMP_E_INT_IFG                  /*!< Comparator output interrupt flag */
1860 /* CE0INT[CEIIFG] Bits */
1861 #define CEIIFG_OFS                               COMP_E_INT_IIFG_OFS             /*!< CEIIFG Offset */
1862 #define CEIIFG                                   COMP_E_INT_IIFG                 /*!< Comparator output inverted interrupt flag */
1863 /* CE0INT[CERDYIFG] Bits */
1864 #define CERDYIFG_OFS                             COMP_E_INT_RDYIFG_OFS           /*!< CERDYIFG Offset */
1865 #define CERDYIFG                                 COMP_E_INT_RDYIFG               /*!< Comparator ready interrupt flag */
1866 /* CE0INT[CEIE] Bits */
1867 #define CEIE_OFS                                 COMP_E_INT_IE_OFS               /*!< CEIE Offset */
1868 #define CEIE                                     COMP_E_INT_IE                   /*!< Comparator output interrupt enable */
1869 /* CE0INT[CEIIE] Bits */
1870 #define CEIIE_OFS                                COMP_E_INT_IIE_OFS              /*!< CEIIE Offset */
1871 #define CEIIE                                    COMP_E_INT_IIE                  /*!< Comparator output interrupt enable inverted polarity */
1872 /* CE0INT[CERDYIE] Bits */
1873 #define CERDYIE_OFS                              COMP_E_INT_RDYIE_OFS            /*!< CERDYIE Offset */
1874 #define CERDYIE                                  COMP_E_INT_RDYIE                /*!< Comparator ready interrupt enable */
1875 
1876 /******************************************************************************
1877 * CRC32 Bits (legacy section)
1878 ******************************************************************************/
1879 /* DIO_PAIN[P1IN] Bits */
1880 #define P1IN_OFS                                           ( 0)                  /*!< P1IN Offset */
1881 #define P1IN_M                                             (0x00ff)              /*!< Port 1 Input */
1882 /* DIO_PAIN[P2IN] Bits */
1883 #define P2IN_OFS                                           ( 8)                  /*!< P2IN Offset */
1884 #define P2IN_M                                             (0xff00)              /*!< Port 2 Input */
1885 /* DIO_PAOUT[P2OUT] Bits */
1886 #define P2OUT_OFS                                          ( 8)                  /*!< P2OUT Offset */
1887 #define P2OUT_M                                            (0xff00)              /*!< Port 2 Output */
1888 /* DIO_PAOUT[P1OUT] Bits */
1889 #define P1OUT_OFS                                          ( 0)                  /*!< P1OUT Offset */
1890 #define P1OUT_M                                            (0x00ff)              /*!< Port 1 Output */
1891 /* DIO_PADIR[P1DIR] Bits */
1892 #define P1DIR_OFS                                          ( 0)                  /*!< P1DIR Offset */
1893 #define P1DIR_M                                            (0x00ff)              /*!< Port 1 Direction */
1894 /* DIO_PADIR[P2DIR] Bits */
1895 #define P2DIR_OFS                                          ( 8)                  /*!< P2DIR Offset */
1896 #define P2DIR_M                                            (0xff00)              /*!< Port 2 Direction */
1897 /* DIO_PAREN[P1REN] Bits */
1898 #define P1REN_OFS                                          ( 0)                  /*!< P1REN Offset */
1899 #define P1REN_M                                            (0x00ff)              /*!< Port 1 Resistor Enable */
1900 /* DIO_PAREN[P2REN] Bits */
1901 #define P2REN_OFS                                          ( 8)                  /*!< P2REN Offset */
1902 #define P2REN_M                                            (0xff00)              /*!< Port 2 Resistor Enable */
1903 /* DIO_PADS[P1DS] Bits */
1904 #define P1DS_OFS                                           ( 0)                  /*!< P1DS Offset */
1905 #define P1DS_M                                             (0x00ff)              /*!< Port 1 Drive Strength */
1906 /* DIO_PADS[P2DS] Bits */
1907 #define P2DS_OFS                                           ( 8)                  /*!< P2DS Offset */
1908 #define P2DS_M                                             (0xff00)              /*!< Port 2 Drive Strength */
1909 /* DIO_PASEL0[P1SEL0] Bits */
1910 #define P1SEL0_OFS                                         ( 0)                  /*!< P1SEL0 Offset */
1911 #define P1SEL0_M                                           (0x00ff)              /*!< Port 1 Select 0 */
1912 /* DIO_PASEL0[P2SEL0] Bits */
1913 #define P2SEL0_OFS                                         ( 8)                  /*!< P2SEL0 Offset */
1914 #define P2SEL0_M                                           (0xff00)              /*!< Port 2 Select 0 */
1915 /* DIO_PASEL1[P1SEL1] Bits */
1916 #define P1SEL1_OFS                                         ( 0)                  /*!< P1SEL1 Offset */
1917 #define P1SEL1_M                                           (0x00ff)              /*!< Port 1 Select 1 */
1918 /* DIO_PASEL1[P2SEL1] Bits */
1919 #define P2SEL1_OFS                                         ( 8)                  /*!< P2SEL1 Offset */
1920 #define P2SEL1_M                                           (0xff00)              /*!< Port 2 Select 1 */
1921 /* DIO_P1IV[P1IV] Bits */
1922 #define P1IV_OFS                                           ( 0)                  /*!< P1IV Offset */
1923 #define P1IV_M                                             (0x001f)              /*!< Port 1 interrupt vector value */
1924 #define P1IV0                                              (0x0001)              /*!< Port 1 interrupt vector value */
1925 #define P1IV1                                              (0x0002)              /*!< Port 1 interrupt vector value */
1926 #define P1IV2                                              (0x0004)              /*!< Port 1 interrupt vector value */
1927 #define P1IV3                                              (0x0008)              /*!< Port 1 interrupt vector value */
1928 #define P1IV4                                              (0x0010)              /*!< Port 1 interrupt vector value */
1929 #define P1IV_0                                             (0x0000)              /*!< No interrupt pending */
1930 #define P1IV_2                                             (0x0002)              /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
1931 #define P1IV_4                                             (0x0004)              /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
1932 #define P1IV_6                                             (0x0006)              /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
1933 #define P1IV_8                                             (0x0008)              /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
1934 #define P1IV_10                                            (0x000a)              /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
1935 #define P1IV_12                                            (0x000c)              /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
1936 #define P1IV_14                                            (0x000e)              /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
1937 #define P1IV_16                                            (0x0010)              /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
1938 #define P1IV__NONE                                         (0x0000)              /*!< No interrupt pending */
1939 #define P1IV__P1IFG0                                       (0x0002)              /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
1940 #define P1IV__P1IFG1                                       (0x0004)              /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
1941 #define P1IV__P1IFG2                                       (0x0006)              /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
1942 #define P1IV__P1IFG3                                       (0x0008)              /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
1943 #define P1IV__P1IFG4                                       (0x000a)              /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
1944 #define P1IV__P1IFG5                                       (0x000c)              /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
1945 #define P1IV__P1IFG6                                       (0x000e)              /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
1946 #define P1IV__P1IFG7                                       (0x0010)              /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
1947 /* DIO_PASELC[P1SELC] Bits */
1948 #define P1SELC_OFS                                         ( 0)                  /*!< P1SELC Offset */
1949 #define P1SELC_M                                           (0x00ff)              /*!< Port 1 Complement Select */
1950 /* DIO_PASELC[P2SELC] Bits */
1951 #define P2SELC_OFS                                         ( 8)                  /*!< P2SELC Offset */
1952 #define P2SELC_M                                           (0xff00)              /*!< Port 2 Complement Select */
1953 /* DIO_PAIES[P1IES] Bits */
1954 #define P1IES_OFS                                          ( 0)                  /*!< P1IES Offset */
1955 #define P1IES_M                                            (0x00ff)              /*!< Port 1 Interrupt Edge Select */
1956 /* DIO_PAIES[P2IES] Bits */
1957 #define P2IES_OFS                                          ( 8)                  /*!< P2IES Offset */
1958 #define P2IES_M                                            (0xff00)              /*!< Port 2 Interrupt Edge Select */
1959 /* DIO_PAIE[P1IE] Bits */
1960 #define P1IE_OFS                                           ( 0)                  /*!< P1IE Offset */
1961 #define P1IE_M                                             (0x00ff)              /*!< Port 1 Interrupt Enable */
1962 /* DIO_PAIE[P2IE] Bits */
1963 #define P2IE_OFS                                           ( 8)                  /*!< P2IE Offset */
1964 #define P2IE_M                                             (0xff00)              /*!< Port 2 Interrupt Enable */
1965 /* DIO_PAIFG[P1IFG] Bits */
1966 #define P1IFG_OFS                                          ( 0)                  /*!< P1IFG Offset */
1967 #define P1IFG_M                                            (0x00ff)              /*!< Port 1 Interrupt Flag */
1968 /* DIO_PAIFG[P2IFG] Bits */
1969 #define P2IFG_OFS                                          ( 8)                  /*!< P2IFG Offset */
1970 #define P2IFG_M                                            (0xff00)              /*!< Port 2 Interrupt Flag */
1971 /* DIO_P2IV[P2IV] Bits */
1972 #define P2IV_OFS                                           ( 0)                  /*!< P2IV Offset */
1973 #define P2IV_M                                             (0x001f)              /*!< Port 2 interrupt vector value */
1974 #define P2IV0                                              (0x0001)              /*!< Port 2 interrupt vector value */
1975 #define P2IV1                                              (0x0002)              /*!< Port 2 interrupt vector value */
1976 #define P2IV2                                              (0x0004)              /*!< Port 2 interrupt vector value */
1977 #define P2IV3                                              (0x0008)              /*!< Port 2 interrupt vector value */
1978 #define P2IV4                                              (0x0010)              /*!< Port 2 interrupt vector value */
1979 #define P2IV_0                                             (0x0000)              /*!< No interrupt pending */
1980 #define P2IV_2                                             (0x0002)              /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
1981 #define P2IV_4                                             (0x0004)              /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
1982 #define P2IV_6                                             (0x0006)              /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
1983 #define P2IV_8                                             (0x0008)              /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
1984 #define P2IV_10                                            (0x000a)              /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
1985 #define P2IV_12                                            (0x000c)              /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
1986 #define P2IV_14                                            (0x000e)              /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
1987 #define P2IV_16                                            (0x0010)              /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
1988 #define P2IV__NONE                                         (0x0000)              /*!< No interrupt pending */
1989 #define P2IV__P2IFG0                                       (0x0002)              /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
1990 #define P2IV__P2IFG1                                       (0x0004)              /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
1991 #define P2IV__P2IFG2                                       (0x0006)              /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
1992 #define P2IV__P2IFG3                                       (0x0008)              /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
1993 #define P2IV__P2IFG4                                       (0x000a)              /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
1994 #define P2IV__P2IFG5                                       (0x000c)              /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
1995 #define P2IV__P2IFG6                                       (0x000e)              /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
1996 #define P2IV__P2IFG7                                       (0x0010)              /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
1997 /* DIO_PBIN[P3IN] Bits */
1998 #define P3IN_OFS                                           ( 0)                  /*!< P3IN Offset */
1999 #define P3IN_M                                             (0x00ff)              /*!< Port 3 Input */
2000 /* DIO_PBIN[P4IN] Bits */
2001 #define P4IN_OFS                                           ( 8)                  /*!< P4IN Offset */
2002 #define P4IN_M                                             (0xff00)              /*!< Port 4 Input */
2003 /* DIO_PBOUT[P3OUT] Bits */
2004 #define P3OUT_OFS                                          ( 0)                  /*!< P3OUT Offset */
2005 #define P3OUT_M                                            (0x00ff)              /*!< Port 3 Output */
2006 /* DIO_PBOUT[P4OUT] Bits */
2007 #define P4OUT_OFS                                          ( 8)                  /*!< P4OUT Offset */
2008 #define P4OUT_M                                            (0xff00)              /*!< Port 4 Output */
2009 /* DIO_PBDIR[P3DIR] Bits */
2010 #define P3DIR_OFS                                          ( 0)                  /*!< P3DIR Offset */
2011 #define P3DIR_M                                            (0x00ff)              /*!< Port 3 Direction */
2012 /* DIO_PBDIR[P4DIR] Bits */
2013 #define P4DIR_OFS                                          ( 8)                  /*!< P4DIR Offset */
2014 #define P4DIR_M                                            (0xff00)              /*!< Port 4 Direction */
2015 /* DIO_PBREN[P3REN] Bits */
2016 #define P3REN_OFS                                          ( 0)                  /*!< P3REN Offset */
2017 #define P3REN_M                                            (0x00ff)              /*!< Port 3 Resistor Enable */
2018 /* DIO_PBREN[P4REN] Bits */
2019 #define P4REN_OFS                                          ( 8)                  /*!< P4REN Offset */
2020 #define P4REN_M                                            (0xff00)              /*!< Port 4 Resistor Enable */
2021 /* DIO_PBDS[P3DS] Bits */
2022 #define P3DS_OFS                                           ( 0)                  /*!< P3DS Offset */
2023 #define P3DS_M                                             (0x00ff)              /*!< Port 3 Drive Strength */
2024 /* DIO_PBDS[P4DS] Bits */
2025 #define P4DS_OFS                                           ( 8)                  /*!< P4DS Offset */
2026 #define P4DS_M                                             (0xff00)              /*!< Port 4 Drive Strength */
2027 /* DIO_PBSEL0[P4SEL0] Bits */
2028 #define P4SEL0_OFS                                         ( 8)                  /*!< P4SEL0 Offset */
2029 #define P4SEL0_M                                           (0xff00)              /*!< Port 4 Select 0 */
2030 /* DIO_PBSEL0[P3SEL0] Bits */
2031 #define P3SEL0_OFS                                         ( 0)                  /*!< P3SEL0 Offset */
2032 #define P3SEL0_M                                           (0x00ff)              /*!< Port 3 Select 0 */
2033 /* DIO_PBSEL1[P3SEL1] Bits */
2034 #define P3SEL1_OFS                                         ( 0)                  /*!< P3SEL1 Offset */
2035 #define P3SEL1_M                                           (0x00ff)              /*!< Port 3 Select 1 */
2036 /* DIO_PBSEL1[P4SEL1] Bits */
2037 #define P4SEL1_OFS                                         ( 8)                  /*!< P4SEL1 Offset */
2038 #define P4SEL1_M                                           (0xff00)              /*!< Port 4 Select 1 */
2039 /* DIO_P3IV[P3IV] Bits */
2040 #define P3IV_OFS                                           ( 0)                  /*!< P3IV Offset */
2041 #define P3IV_M                                             (0x001f)              /*!< Port 3 interrupt vector value */
2042 #define P3IV0                                              (0x0001)              /*!< Port 3 interrupt vector value */
2043 #define P3IV1                                              (0x0002)              /*!< Port 3 interrupt vector value */
2044 #define P3IV2                                              (0x0004)              /*!< Port 3 interrupt vector value */
2045 #define P3IV3                                              (0x0008)              /*!< Port 3 interrupt vector value */
2046 #define P3IV4                                              (0x0010)              /*!< Port 3 interrupt vector value */
2047 #define P3IV_0                                             (0x0000)              /*!< No interrupt pending */
2048 #define P3IV_2                                             (0x0002)              /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
2049 #define P3IV_4                                             (0x0004)              /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
2050 #define P3IV_6                                             (0x0006)              /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
2051 #define P3IV_8                                             (0x0008)              /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
2052 #define P3IV_10                                            (0x000a)              /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
2053 #define P3IV_12                                            (0x000c)              /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
2054 #define P3IV_14                                            (0x000e)              /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
2055 #define P3IV_16                                            (0x0010)              /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
2056 #define P3IV__NONE                                         (0x0000)              /*!< No interrupt pending */
2057 #define P3IV__P3IFG0                                       (0x0002)              /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
2058 #define P3IV__P3IFG1                                       (0x0004)              /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
2059 #define P3IV__P3IFG2                                       (0x0006)              /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
2060 #define P3IV__P3IFG3                                       (0x0008)              /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
2061 #define P3IV__P3IFG4                                       (0x000a)              /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
2062 #define P3IV__P3IFG5                                       (0x000c)              /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
2063 #define P3IV__P3IFG6                                       (0x000e)              /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
2064 #define P3IV__P3IFG7                                       (0x0010)              /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
2065 /* DIO_PBSELC[P3SELC] Bits */
2066 #define P3SELC_OFS                                         ( 0)                  /*!< P3SELC Offset */
2067 #define P3SELC_M                                           (0x00ff)              /*!< Port 3 Complement Select */
2068 /* DIO_PBSELC[P4SELC] Bits */
2069 #define P4SELC_OFS                                         ( 8)                  /*!< P4SELC Offset */
2070 #define P4SELC_M                                           (0xff00)              /*!< Port 4 Complement Select */
2071 /* DIO_PBIES[P3IES] Bits */
2072 #define P3IES_OFS                                          ( 0)                  /*!< P3IES Offset */
2073 #define P3IES_M                                            (0x00ff)              /*!< Port 3 Interrupt Edge Select */
2074 /* DIO_PBIES[P4IES] Bits */
2075 #define P4IES_OFS                                          ( 8)                  /*!< P4IES Offset */
2076 #define P4IES_M                                            (0xff00)              /*!< Port 4 Interrupt Edge Select */
2077 /* DIO_PBIE[P3IE] Bits */
2078 #define P3IE_OFS                                           ( 0)                  /*!< P3IE Offset */
2079 #define P3IE_M                                             (0x00ff)              /*!< Port 3 Interrupt Enable */
2080 /* DIO_PBIE[P4IE] Bits */
2081 #define P4IE_OFS                                           ( 8)                  /*!< P4IE Offset */
2082 #define P4IE_M                                             (0xff00)              /*!< Port 4 Interrupt Enable */
2083 /* DIO_PBIFG[P3IFG] Bits */
2084 #define P3IFG_OFS                                          ( 0)                  /*!< P3IFG Offset */
2085 #define P3IFG_M                                            (0x00ff)              /*!< Port 3 Interrupt Flag */
2086 /* DIO_PBIFG[P4IFG] Bits */
2087 #define P4IFG_OFS                                          ( 8)                  /*!< P4IFG Offset */
2088 #define P4IFG_M                                            (0xff00)              /*!< Port 4 Interrupt Flag */
2089 /* DIO_P4IV[P4IV] Bits */
2090 #define P4IV_OFS                                           ( 0)                  /*!< P4IV Offset */
2091 #define P4IV_M                                             (0x001f)              /*!< Port 4 interrupt vector value */
2092 #define P4IV0                                              (0x0001)              /*!< Port 4 interrupt vector value */
2093 #define P4IV1                                              (0x0002)              /*!< Port 4 interrupt vector value */
2094 #define P4IV2                                              (0x0004)              /*!< Port 4 interrupt vector value */
2095 #define P4IV3                                              (0x0008)              /*!< Port 4 interrupt vector value */
2096 #define P4IV4                                              (0x0010)              /*!< Port 4 interrupt vector value */
2097 #define P4IV_0                                             (0x0000)              /*!< No interrupt pending */
2098 #define P4IV_2                                             (0x0002)              /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
2099 #define P4IV_4                                             (0x0004)              /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
2100 #define P4IV_6                                             (0x0006)              /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
2101 #define P4IV_8                                             (0x0008)              /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
2102 #define P4IV_10                                            (0x000a)              /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
2103 #define P4IV_12                                            (0x000c)              /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
2104 #define P4IV_14                                            (0x000e)              /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
2105 #define P4IV_16                                            (0x0010)              /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
2106 #define P4IV__NONE                                         (0x0000)              /*!< No interrupt pending */
2107 #define P4IV__P4IFG0                                       (0x0002)              /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
2108 #define P4IV__P4IFG1                                       (0x0004)              /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
2109 #define P4IV__P4IFG2                                       (0x0006)              /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
2110 #define P4IV__P4IFG3                                       (0x0008)              /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
2111 #define P4IV__P4IFG4                                       (0x000a)              /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
2112 #define P4IV__P4IFG5                                       (0x000c)              /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
2113 #define P4IV__P4IFG6                                       (0x000e)              /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
2114 #define P4IV__P4IFG7                                       (0x0010)              /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
2115 /* DIO_PCIN[P5IN] Bits */
2116 #define P5IN_OFS                                           ( 0)                  /*!< P5IN Offset */
2117 #define P5IN_M                                             (0x00ff)              /*!< Port 5 Input */
2118 /* DIO_PCIN[P6IN] Bits */
2119 #define P6IN_OFS                                           ( 8)                  /*!< P6IN Offset */
2120 #define P6IN_M                                             (0xff00)              /*!< Port 6 Input */
2121 /* DIO_PCOUT[P5OUT] Bits */
2122 #define P5OUT_OFS                                          ( 0)                  /*!< P5OUT Offset */
2123 #define P5OUT_M                                            (0x00ff)              /*!< Port 5 Output */
2124 /* DIO_PCOUT[P6OUT] Bits */
2125 #define P6OUT_OFS                                          ( 8)                  /*!< P6OUT Offset */
2126 #define P6OUT_M                                            (0xff00)              /*!< Port 6 Output */
2127 /* DIO_PCDIR[P5DIR] Bits */
2128 #define P5DIR_OFS                                          ( 0)                  /*!< P5DIR Offset */
2129 #define P5DIR_M                                            (0x00ff)              /*!< Port 5 Direction */
2130 /* DIO_PCDIR[P6DIR] Bits */
2131 #define P6DIR_OFS                                          ( 8)                  /*!< P6DIR Offset */
2132 #define P6DIR_M                                            (0xff00)              /*!< Port 6 Direction */
2133 /* DIO_PCREN[P5REN] Bits */
2134 #define P5REN_OFS                                          ( 0)                  /*!< P5REN Offset */
2135 #define P5REN_M                                            (0x00ff)              /*!< Port 5 Resistor Enable */
2136 /* DIO_PCREN[P6REN] Bits */
2137 #define P6REN_OFS                                          ( 8)                  /*!< P6REN Offset */
2138 #define P6REN_M                                            (0xff00)              /*!< Port 6 Resistor Enable */
2139 /* DIO_PCDS[P5DS] Bits */
2140 #define P5DS_OFS                                           ( 0)                  /*!< P5DS Offset */
2141 #define P5DS_M                                             (0x00ff)              /*!< Port 5 Drive Strength */
2142 /* DIO_PCDS[P6DS] Bits */
2143 #define P6DS_OFS                                           ( 8)                  /*!< P6DS Offset */
2144 #define P6DS_M                                             (0xff00)              /*!< Port 6 Drive Strength */
2145 /* DIO_PCSEL0[P5SEL0] Bits */
2146 #define P5SEL0_OFS                                         ( 0)                  /*!< P5SEL0 Offset */
2147 #define P5SEL0_M                                           (0x00ff)              /*!< Port 5 Select 0 */
2148 /* DIO_PCSEL0[P6SEL0] Bits */
2149 #define P6SEL0_OFS                                         ( 8)                  /*!< P6SEL0 Offset */
2150 #define P6SEL0_M                                           (0xff00)              /*!< Port 6 Select 0 */
2151 /* DIO_PCSEL1[P5SEL1] Bits */
2152 #define P5SEL1_OFS                                         ( 0)                  /*!< P5SEL1 Offset */
2153 #define P5SEL1_M                                           (0x00ff)              /*!< Port 5 Select 1 */
2154 /* DIO_PCSEL1[P6SEL1] Bits */
2155 #define P6SEL1_OFS                                         ( 8)                  /*!< P6SEL1 Offset */
2156 #define P6SEL1_M                                           (0xff00)              /*!< Port 6 Select 1 */
2157 /* DIO_P5IV[P5IV] Bits */
2158 #define P5IV_OFS                                           ( 0)                  /*!< P5IV Offset */
2159 #define P5IV_M                                             (0x001f)              /*!< Port 5 interrupt vector value */
2160 #define P5IV0                                              (0x0001)              /*!< Port 5 interrupt vector value */
2161 #define P5IV1                                              (0x0002)              /*!< Port 5 interrupt vector value */
2162 #define P5IV2                                              (0x0004)              /*!< Port 5 interrupt vector value */
2163 #define P5IV3                                              (0x0008)              /*!< Port 5 interrupt vector value */
2164 #define P5IV4                                              (0x0010)              /*!< Port 5 interrupt vector value */
2165 #define P5IV_0                                             (0x0000)              /*!< No interrupt pending */
2166 #define P5IV_2                                             (0x0002)              /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
2167 #define P5IV_4                                             (0x0004)              /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
2168 #define P5IV_6                                             (0x0006)              /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
2169 #define P5IV_8                                             (0x0008)              /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
2170 #define P5IV_10                                            (0x000a)              /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
2171 #define P5IV_12                                            (0x000c)              /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
2172 #define P5IV_14                                            (0x000e)              /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
2173 #define P5IV_16                                            (0x0010)              /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
2174 #define P5IV__NONE                                         (0x0000)              /*!< No interrupt pending */
2175 #define P5IV__P5IFG0                                       (0x0002)              /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
2176 #define P5IV__P5IFG1                                       (0x0004)              /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
2177 #define P5IV__P5IFG2                                       (0x0006)              /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
2178 #define P5IV__P5IFG3                                       (0x0008)              /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
2179 #define P5IV__P5IFG4                                       (0x000a)              /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
2180 #define P5IV__P5IFG5                                       (0x000c)              /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
2181 #define P5IV__P5IFG6                                       (0x000e)              /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
2182 #define P5IV__P5IFG7                                       (0x0010)              /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
2183 /* DIO_PCSELC[P5SELC] Bits */
2184 #define P5SELC_OFS                                         ( 0)                  /*!< P5SELC Offset */
2185 #define P5SELC_M                                           (0x00ff)              /*!< Port 5 Complement Select */
2186 /* DIO_PCSELC[P6SELC] Bits */
2187 #define P6SELC_OFS                                         ( 8)                  /*!< P6SELC Offset */
2188 #define P6SELC_M                                           (0xff00)              /*!< Port 6 Complement Select */
2189 /* DIO_PCIES[P5IES] Bits */
2190 #define P5IES_OFS                                          ( 0)                  /*!< P5IES Offset */
2191 #define P5IES_M                                            (0x00ff)              /*!< Port 5 Interrupt Edge Select */
2192 /* DIO_PCIES[P6IES] Bits */
2193 #define P6IES_OFS                                          ( 8)                  /*!< P6IES Offset */
2194 #define P6IES_M                                            (0xff00)              /*!< Port 6 Interrupt Edge Select */
2195 /* DIO_PCIE[P5IE] Bits */
2196 #define P5IE_OFS                                           ( 0)                  /*!< P5IE Offset */
2197 #define P5IE_M                                             (0x00ff)              /*!< Port 5 Interrupt Enable */
2198 /* DIO_PCIE[P6IE] Bits */
2199 #define P6IE_OFS                                           ( 8)                  /*!< P6IE Offset */
2200 #define P6IE_M                                             (0xff00)              /*!< Port 6 Interrupt Enable */
2201 /* DIO_PCIFG[P5IFG] Bits */
2202 #define P5IFG_OFS                                          ( 0)                  /*!< P5IFG Offset */
2203 #define P5IFG_M                                            (0x00ff)              /*!< Port 5 Interrupt Flag */
2204 /* DIO_PCIFG[P6IFG] Bits */
2205 #define P6IFG_OFS                                          ( 8)                  /*!< P6IFG Offset */
2206 #define P6IFG_M                                            (0xff00)              /*!< Port 6 Interrupt Flag */
2207 /* DIO_P6IV[P6IV] Bits */
2208 #define P6IV_OFS                                           ( 0)                  /*!< P6IV Offset */
2209 #define P6IV_M                                             (0x001f)              /*!< Port 6 interrupt vector value */
2210 #define P6IV0                                              (0x0001)              /*!< Port 6 interrupt vector value */
2211 #define P6IV1                                              (0x0002)              /*!< Port 6 interrupt vector value */
2212 #define P6IV2                                              (0x0004)              /*!< Port 6 interrupt vector value */
2213 #define P6IV3                                              (0x0008)              /*!< Port 6 interrupt vector value */
2214 #define P6IV4                                              (0x0010)              /*!< Port 6 interrupt vector value */
2215 #define P6IV_0                                             (0x0000)              /*!< No interrupt pending */
2216 #define P6IV_2                                             (0x0002)              /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
2217 #define P6IV_4                                             (0x0004)              /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
2218 #define P6IV_6                                             (0x0006)              /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
2219 #define P6IV_8                                             (0x0008)              /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
2220 #define P6IV_10                                            (0x000a)              /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
2221 #define P6IV_12                                            (0x000c)              /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
2222 #define P6IV_14                                            (0x000e)              /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
2223 #define P6IV_16                                            (0x0010)              /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
2224 #define P6IV__NONE                                         (0x0000)              /*!< No interrupt pending */
2225 #define P6IV__P6IFG0                                       (0x0002)              /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
2226 #define P6IV__P6IFG1                                       (0x0004)              /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
2227 #define P6IV__P6IFG2                                       (0x0006)              /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
2228 #define P6IV__P6IFG3                                       (0x0008)              /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
2229 #define P6IV__P6IFG4                                       (0x000a)              /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
2230 #define P6IV__P6IFG5                                       (0x000c)              /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
2231 #define P6IV__P6IFG6                                       (0x000e)              /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
2232 #define P6IV__P6IFG7                                       (0x0010)              /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
2233 /* DIO_PDIN[P7IN] Bits */
2234 #define P7IN_OFS                                           ( 0)                  /*!< P7IN Offset */
2235 #define P7IN_M                                             (0x00ff)              /*!< Port 7 Input */
2236 /* DIO_PDIN[P8IN] Bits */
2237 #define P8IN_OFS                                           ( 8)                  /*!< P8IN Offset */
2238 #define P8IN_M                                             (0xff00)              /*!< Port 8 Input */
2239 /* DIO_PDOUT[P7OUT] Bits */
2240 #define P7OUT_OFS                                          ( 0)                  /*!< P7OUT Offset */
2241 #define P7OUT_M                                            (0x00ff)              /*!< Port 7 Output */
2242 /* DIO_PDOUT[P8OUT] Bits */
2243 #define P8OUT_OFS                                          ( 8)                  /*!< P8OUT Offset */
2244 #define P8OUT_M                                            (0xff00)              /*!< Port 8 Output */
2245 /* DIO_PDDIR[P7DIR] Bits */
2246 #define P7DIR_OFS                                          ( 0)                  /*!< P7DIR Offset */
2247 #define P7DIR_M                                            (0x00ff)              /*!< Port 7 Direction */
2248 /* DIO_PDDIR[P8DIR] Bits */
2249 #define P8DIR_OFS                                          ( 8)                  /*!< P8DIR Offset */
2250 #define P8DIR_M                                            (0xff00)              /*!< Port 8 Direction */
2251 /* DIO_PDREN[P7REN] Bits */
2252 #define P7REN_OFS                                          ( 0)                  /*!< P7REN Offset */
2253 #define P7REN_M                                            (0x00ff)              /*!< Port 7 Resistor Enable */
2254 /* DIO_PDREN[P8REN] Bits */
2255 #define P8REN_OFS                                          ( 8)                  /*!< P8REN Offset */
2256 #define P8REN_M                                            (0xff00)              /*!< Port 8 Resistor Enable */
2257 /* DIO_PDDS[P7DS] Bits */
2258 #define P7DS_OFS                                           ( 0)                  /*!< P7DS Offset */
2259 #define P7DS_M                                             (0x00ff)              /*!< Port 7 Drive Strength */
2260 /* DIO_PDDS[P8DS] Bits */
2261 #define P8DS_OFS                                           ( 8)                  /*!< P8DS Offset */
2262 #define P8DS_M                                             (0xff00)              /*!< Port 8 Drive Strength */
2263 /* DIO_PDSEL0[P7SEL0] Bits */
2264 #define P7SEL0_OFS                                         ( 0)                  /*!< P7SEL0 Offset */
2265 #define P7SEL0_M                                           (0x00ff)              /*!< Port 7 Select 0 */
2266 /* DIO_PDSEL0[P8SEL0] Bits */
2267 #define P8SEL0_OFS                                         ( 8)                  /*!< P8SEL0 Offset */
2268 #define P8SEL0_M                                           (0xff00)              /*!< Port 8 Select 0 */
2269 /* DIO_PDSEL1[P7SEL1] Bits */
2270 #define P7SEL1_OFS                                         ( 0)                  /*!< P7SEL1 Offset */
2271 #define P7SEL1_M                                           (0x00ff)              /*!< Port 7 Select 1 */
2272 /* DIO_PDSEL1[P8SEL1] Bits */
2273 #define P8SEL1_OFS                                         ( 8)                  /*!< P8SEL1 Offset */
2274 #define P8SEL1_M                                           (0xff00)              /*!< Port 8 Select 1 */
2275 /* DIO_P7IV[P7IV] Bits */
2276 #define P7IV_OFS                                           ( 0)                  /*!< P7IV Offset */
2277 #define P7IV_M                                             (0x001f)              /*!< Port 7 interrupt vector value */
2278 #define P7IV0                                              (0x0001)              /*!< Port 7 interrupt vector value */
2279 #define P7IV1                                              (0x0002)              /*!< Port 7 interrupt vector value */
2280 #define P7IV2                                              (0x0004)              /*!< Port 7 interrupt vector value */
2281 #define P7IV3                                              (0x0008)              /*!< Port 7 interrupt vector value */
2282 #define P7IV4                                              (0x0010)              /*!< Port 7 interrupt vector value */
2283 #define P7IV_0                                             (0x0000)              /*!< No interrupt pending */
2284 #define P7IV_2                                             (0x0002)              /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
2285 #define P7IV_4                                             (0x0004)              /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
2286 #define P7IV_6                                             (0x0006)              /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
2287 #define P7IV_8                                             (0x0008)              /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
2288 #define P7IV_10                                            (0x000a)              /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
2289 #define P7IV_12                                            (0x000c)              /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
2290 #define P7IV_14                                            (0x000e)              /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
2291 #define P7IV_16                                            (0x0010)              /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
2292 #define P7IV__NONE                                         (0x0000)              /*!< No interrupt pending */
2293 #define P7IV__P7IFG0                                       (0x0002)              /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
2294 #define P7IV__P7IFG1                                       (0x0004)              /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
2295 #define P7IV__P7IFG2                                       (0x0006)              /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
2296 #define P7IV__P7IFG3                                       (0x0008)              /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
2297 #define P7IV__P7IFG4                                       (0x000a)              /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
2298 #define P7IV__P7IFG5                                       (0x000c)              /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
2299 #define P7IV__P7IFG6                                       (0x000e)              /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
2300 #define P7IV__P7IFG7                                       (0x0010)              /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
2301 /* DIO_PDSELC[P7SELC] Bits */
2302 #define P7SELC_OFS                                         ( 0)                  /*!< P7SELC Offset */
2303 #define P7SELC_M                                           (0x00ff)              /*!< Port 7 Complement Select */
2304 /* DIO_PDSELC[P8SELC] Bits */
2305 #define P8SELC_OFS                                         ( 8)                  /*!< P8SELC Offset */
2306 #define P8SELC_M                                           (0xff00)              /*!< Port 8 Complement Select */
2307 /* DIO_PDIES[P7IES] Bits */
2308 #define P7IES_OFS                                          ( 0)                  /*!< P7IES Offset */
2309 #define P7IES_M                                            (0x00ff)              /*!< Port 7 Interrupt Edge Select */
2310 /* DIO_PDIES[P8IES] Bits */
2311 #define P8IES_OFS                                          ( 8)                  /*!< P8IES Offset */
2312 #define P8IES_M                                            (0xff00)              /*!< Port 8 Interrupt Edge Select */
2313 /* DIO_PDIE[P7IE] Bits */
2314 #define P7IE_OFS                                           ( 0)                  /*!< P7IE Offset */
2315 #define P7IE_M                                             (0x00ff)              /*!< Port 7 Interrupt Enable */
2316 /* DIO_PDIE[P8IE] Bits */
2317 #define P8IE_OFS                                           ( 8)                  /*!< P8IE Offset */
2318 #define P8IE_M                                             (0xff00)              /*!< Port 8 Interrupt Enable */
2319 /* DIO_PDIFG[P7IFG] Bits */
2320 #define P7IFG_OFS                                          ( 0)                  /*!< P7IFG Offset */
2321 #define P7IFG_M                                            (0x00ff)              /*!< Port 7 Interrupt Flag */
2322 /* DIO_PDIFG[P8IFG] Bits */
2323 #define P8IFG_OFS                                          ( 8)                  /*!< P8IFG Offset */
2324 #define P8IFG_M                                            (0xff00)              /*!< Port 8 Interrupt Flag */
2325 /* DIO_P8IV[P8IV] Bits */
2326 #define P8IV_OFS                                           ( 0)                  /*!< P8IV Offset */
2327 #define P8IV_M                                             (0x001f)              /*!< Port 8 interrupt vector value */
2328 #define P8IV0                                              (0x0001)              /*!< Port 8 interrupt vector value */
2329 #define P8IV1                                              (0x0002)              /*!< Port 8 interrupt vector value */
2330 #define P8IV2                                              (0x0004)              /*!< Port 8 interrupt vector value */
2331 #define P8IV3                                              (0x0008)              /*!< Port 8 interrupt vector value */
2332 #define P8IV4                                              (0x0010)              /*!< Port 8 interrupt vector value */
2333 #define P8IV_0                                             (0x0000)              /*!< No interrupt pending */
2334 #define P8IV_2                                             (0x0002)              /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
2335 #define P8IV_4                                             (0x0004)              /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
2336 #define P8IV_6                                             (0x0006)              /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
2337 #define P8IV_8                                             (0x0008)              /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
2338 #define P8IV_10                                            (0x000a)              /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
2339 #define P8IV_12                                            (0x000c)              /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
2340 #define P8IV_14                                            (0x000e)              /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
2341 #define P8IV_16                                            (0x0010)              /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
2342 #define P8IV__NONE                                         (0x0000)              /*!< No interrupt pending */
2343 #define P8IV__P8IFG0                                       (0x0002)              /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
2344 #define P8IV__P8IFG1                                       (0x0004)              /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
2345 #define P8IV__P8IFG2                                       (0x0006)              /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
2346 #define P8IV__P8IFG3                                       (0x0008)              /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
2347 #define P8IV__P8IFG4                                       (0x000a)              /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
2348 #define P8IV__P8IFG5                                       (0x000c)              /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
2349 #define P8IV__P8IFG6                                       (0x000e)              /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
2350 #define P8IV__P8IFG7                                       (0x0010)              /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
2351 /* DIO_PEIN[P9IN] Bits */
2352 #define P9IN_OFS                                           ( 0)                  /*!< P9IN Offset */
2353 #define P9IN_M                                             (0x00ff)              /*!< Port 9 Input */
2354 /* DIO_PEIN[P10IN] Bits */
2355 #define P10IN_OFS                                          ( 8)                  /*!< P10IN Offset */
2356 #define P10IN_M                                            (0xff00)              /*!< Port 10 Input */
2357 /* DIO_PEOUT[P9OUT] Bits */
2358 #define P9OUT_OFS                                          ( 0)                  /*!< P9OUT Offset */
2359 #define P9OUT_M                                            (0x00ff)              /*!< Port 9 Output */
2360 /* DIO_PEOUT[P10OUT] Bits */
2361 #define P10OUT_OFS                                         ( 8)                  /*!< P10OUT Offset */
2362 #define P10OUT_M                                           (0xff00)              /*!< Port 10 Output */
2363 /* DIO_PEDIR[P9DIR] Bits */
2364 #define P9DIR_OFS                                          ( 0)                  /*!< P9DIR Offset */
2365 #define P9DIR_M                                            (0x00ff)              /*!< Port 9 Direction */
2366 /* DIO_PEDIR[P10DIR] Bits */
2367 #define P10DIR_OFS                                         ( 8)                  /*!< P10DIR Offset */
2368 #define P10DIR_M                                           (0xff00)              /*!< Port 10 Direction */
2369 /* DIO_PEREN[P9REN] Bits */
2370 #define P9REN_OFS                                          ( 0)                  /*!< P9REN Offset */
2371 #define P9REN_M                                            (0x00ff)              /*!< Port 9 Resistor Enable */
2372 /* DIO_PEREN[P10REN] Bits */
2373 #define P10REN_OFS                                         ( 8)                  /*!< P10REN Offset */
2374 #define P10REN_M                                           (0xff00)              /*!< Port 10 Resistor Enable */
2375 /* DIO_PEDS[P9DS] Bits */
2376 #define P9DS_OFS                                           ( 0)                  /*!< P9DS Offset */
2377 #define P9DS_M                                             (0x00ff)              /*!< Port 9 Drive Strength */
2378 /* DIO_PEDS[P10DS] Bits */
2379 #define P10DS_OFS                                          ( 8)                  /*!< P10DS Offset */
2380 #define P10DS_M                                            (0xff00)              /*!< Port 10 Drive Strength */
2381 /* DIO_PESEL0[P9SEL0] Bits */
2382 #define P9SEL0_OFS                                         ( 0)                  /*!< P9SEL0 Offset */
2383 #define P9SEL0_M                                           (0x00ff)              /*!< Port 9 Select 0 */
2384 /* DIO_PESEL0[P10SEL0] Bits */
2385 #define P10SEL0_OFS                                        ( 8)                  /*!< P10SEL0 Offset */
2386 #define P10SEL0_M                                          (0xff00)              /*!< Port 10 Select 0 */
2387 /* DIO_PESEL1[P9SEL1] Bits */
2388 #define P9SEL1_OFS                                         ( 0)                  /*!< P9SEL1 Offset */
2389 #define P9SEL1_M                                           (0x00ff)              /*!< Port 9 Select 1 */
2390 /* DIO_PESEL1[P10SEL1] Bits */
2391 #define P10SEL1_OFS                                        ( 8)                  /*!< P10SEL1 Offset */
2392 #define P10SEL1_M                                          (0xff00)              /*!< Port 10 Select 1 */
2393 /* DIO_P9IV[P9IV] Bits */
2394 #define P9IV_OFS                                           ( 0)                  /*!< P9IV Offset */
2395 #define P9IV_M                                             (0x001f)              /*!< Port 9 interrupt vector value */
2396 #define P9IV0                                              (0x0001)              /*!< Port 9 interrupt vector value */
2397 #define P9IV1                                              (0x0002)              /*!< Port 9 interrupt vector value */
2398 #define P9IV2                                              (0x0004)              /*!< Port 9 interrupt vector value */
2399 #define P9IV3                                              (0x0008)              /*!< Port 9 interrupt vector value */
2400 #define P9IV4                                              (0x0010)              /*!< Port 9 interrupt vector value */
2401 #define P9IV_0                                             (0x0000)              /*!< No interrupt pending */
2402 #define P9IV_2                                             (0x0002)              /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
2403 #define P9IV_4                                             (0x0004)              /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
2404 #define P9IV_6                                             (0x0006)              /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
2405 #define P9IV_8                                             (0x0008)              /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
2406 #define P9IV_10                                            (0x000a)              /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
2407 #define P9IV_12                                            (0x000c)              /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
2408 #define P9IV_14                                            (0x000e)              /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
2409 #define P9IV_16                                            (0x0010)              /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
2410 #define P9IV__NONE                                         (0x0000)              /*!< No interrupt pending */
2411 #define P9IV__P9IFG0                                       (0x0002)              /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
2412 #define P9IV__P9IFG1                                       (0x0004)              /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
2413 #define P9IV__P9IFG2                                       (0x0006)              /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
2414 #define P9IV__P9IFG3                                       (0x0008)              /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
2415 #define P9IV__P9IFG4                                       (0x000a)              /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
2416 #define P9IV__P9IFG5                                       (0x000c)              /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
2417 #define P9IV__P9IFG6                                       (0x000e)              /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
2418 #define P9IV__P9IFG7                                       (0x0010)              /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
2419 /* DIO_PESELC[P9SELC] Bits */
2420 #define P9SELC_OFS                                         ( 0)                  /*!< P9SELC Offset */
2421 #define P9SELC_M                                           (0x00ff)              /*!< Port 9 Complement Select */
2422 /* DIO_PESELC[P10SELC] Bits */
2423 #define P10SELC_OFS                                        ( 8)                  /*!< P10SELC Offset */
2424 #define P10SELC_M                                          (0xff00)              /*!< Port 10 Complement Select */
2425 /* DIO_PEIES[P9IES] Bits */
2426 #define P9IES_OFS                                          ( 0)                  /*!< P9IES Offset */
2427 #define P9IES_M                                            (0x00ff)              /*!< Port 9 Interrupt Edge Select */
2428 /* DIO_PEIES[P10IES] Bits */
2429 #define P10IES_OFS                                         ( 8)                  /*!< P10IES Offset */
2430 #define P10IES_M                                           (0xff00)              /*!< Port 10 Interrupt Edge Select */
2431 /* DIO_PEIE[P9IE] Bits */
2432 #define P9IE_OFS                                           ( 0)                  /*!< P9IE Offset */
2433 #define P9IE_M                                             (0x00ff)              /*!< Port 9 Interrupt Enable */
2434 /* DIO_PEIE[P10IE] Bits */
2435 #define P10IE_OFS                                          ( 8)                  /*!< P10IE Offset */
2436 #define P10IE_M                                            (0xff00)              /*!< Port 10 Interrupt Enable */
2437 /* DIO_PEIFG[P9IFG] Bits */
2438 #define P9IFG_OFS                                          ( 0)                  /*!< P9IFG Offset */
2439 #define P9IFG_M                                            (0x00ff)              /*!< Port 9 Interrupt Flag */
2440 /* DIO_PEIFG[P10IFG] Bits */
2441 #define P10IFG_OFS                                         ( 8)                  /*!< P10IFG Offset */
2442 #define P10IFG_M                                           (0xff00)              /*!< Port 10 Interrupt Flag */
2443 /* DIO_P10IV[P10IV] Bits */
2444 #define P10IV_OFS                                          ( 0)                  /*!< P10IV Offset */
2445 #define P10IV_M                                            (0x001f)              /*!< Port 10 interrupt vector value */
2446 #define P10IV0                                             (0x0001)              /*!< Port 10 interrupt vector value */
2447 #define P10IV1                                             (0x0002)              /*!< Port 10 interrupt vector value */
2448 #define P10IV2                                             (0x0004)              /*!< Port 10 interrupt vector value */
2449 #define P10IV3                                             (0x0008)              /*!< Port 10 interrupt vector value */
2450 #define P10IV4                                             (0x0010)              /*!< Port 10 interrupt vector value */
2451 #define P10IV_0                                            (0x0000)              /*!< No interrupt pending */
2452 #define P10IV_2                                            (0x0002)              /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
2453 #define P10IV_4                                            (0x0004)              /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
2454 #define P10IV_6                                            (0x0006)              /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
2455 #define P10IV_8                                            (0x0008)              /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
2456 #define P10IV_10                                           (0x000a)              /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
2457 #define P10IV_12                                           (0x000c)              /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
2458 #define P10IV_14                                           (0x000e)              /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
2459 #define P10IV_16                                           (0x0010)              /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
2460 #define P10IV__NONE                                        (0x0000)              /*!< No interrupt pending */
2461 #define P10IV__P10IFG0                                     (0x0002)              /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
2462 #define P10IV__P10IFG1                                     (0x0004)              /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
2463 #define P10IV__P10IFG2                                     (0x0006)              /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
2464 #define P10IV__P10IFG3                                     (0x0008)              /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
2465 #define P10IV__P10IFG4                                     (0x000a)              /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
2466 #define P10IV__P10IFG5                                     (0x000c)              /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
2467 #define P10IV__P10IFG6                                     (0x000e)              /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
2468 #define P10IV__P10IFG7                                     (0x0010)              /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
2469 
2470 
2471 /******************************************************************************
2472 * EUSCI_A Bits (legacy section)
2473 ******************************************************************************/
2474 /* UCA0CTLW0[UCSWRST] Bits */
2475 #define UCSWRST_OFS                              EUSCI_A_CTLW0_SWRST_OFS         /*!< UCSWRST Offset */
2476 #define UCSWRST                                  EUSCI_A_CTLW0_SWRST             /*!< Software reset enable */
2477 /* UCA0CTLW0[UCTXBRK] Bits */
2478 #define UCTXBRK_OFS                              EUSCI_A_CTLW0_TXBRK_OFS         /*!< UCTXBRK Offset */
2479 #define UCTXBRK                                  EUSCI_A_CTLW0_TXBRK             /*!< Transmit break */
2480 /* UCA0CTLW0[UCTXADDR] Bits */
2481 #define UCTXADDR_OFS                             EUSCI_A_CTLW0_TXADDR_OFS        /*!< UCTXADDR Offset */
2482 #define UCTXADDR                                 EUSCI_A_CTLW0_TXADDR            /*!< Transmit address */
2483 /* UCA0CTLW0[UCDORM] Bits */
2484 #define UCDORM_OFS                               EUSCI_A_CTLW0_DORM_OFS          /*!< UCDORM Offset */
2485 #define UCDORM                                   EUSCI_A_CTLW0_DORM              /*!< Dormant */
2486 /* UCA0CTLW0[UCBRKIE] Bits */
2487 #define UCBRKIE_OFS                              EUSCI_A_CTLW0_BRKIE_OFS         /*!< UCBRKIE Offset */
2488 #define UCBRKIE                                  EUSCI_A_CTLW0_BRKIE             /*!< Receive break character interrupt enable */
2489 /* UCA0CTLW0[UCRXEIE] Bits */
2490 #define UCRXEIE_OFS                              EUSCI_A_CTLW0_RXEIE_OFS         /*!< UCRXEIE Offset */
2491 #define UCRXEIE                                  EUSCI_A_CTLW0_RXEIE             /*!< Receive erroneous-character interrupt enable */
2492 /* UCA0CTLW0[UCSSEL] Bits */
2493 #define UCSSEL_OFS                               EUSCI_A_CTLW0_SSEL_OFS          /*!< UCSSEL Offset */
2494 #define UCSSEL_M                                 EUSCI_A_CTLW0_SSEL_MASK         /*!< eUSCI_A clock source select */
2495 #define UCSSEL0                                  EUSCI_A_CTLW0_SSEL0             /*!< UCSSEL Bit 0 */
2496 #define UCSSEL1                                  EUSCI_A_CTLW0_SSEL1             /*!< UCSSEL Bit 1 */
2497 #define UCSSEL_0                                 EUSCI_A_CTLW0_UCSSEL_0          /*!< UCLK */
2498 #define UCSSEL_1                                 EUSCI_A_CTLW0_UCSSEL_1          /*!< ACLK */
2499 #define UCSSEL_2                                 EUSCI_A_CTLW0_UCSSEL_2          /*!< SMCLK */
2500 #define UCSSEL__UCLK                             EUSCI_A_CTLW0_SSEL__UCLK        /*!< UCLK */
2501 #define UCSSEL__ACLK                             EUSCI_A_CTLW0_SSEL__ACLK        /*!< ACLK */
2502 #define UCSSEL__SMCLK                            EUSCI_A_CTLW0_SSEL__SMCLK       /*!< SMCLK */
2503 /* UCA0CTLW0[UCSYNC] Bits */
2504 #define UCSYNC_OFS                               EUSCI_A_CTLW0_SYNC_OFS          /*!< UCSYNC Offset */
2505 #define UCSYNC                                   EUSCI_A_CTLW0_SYNC              /*!< Synchronous mode enable */
2506 /* UCA0CTLW0[UCMODE] Bits */
2507 #define UCMODE_OFS                               EUSCI_A_CTLW0_MODE_OFS          /*!< UCMODE Offset */
2508 #define UCMODE_M                                 EUSCI_A_CTLW0_MODE_MASK         /*!< eUSCI_A mode */
2509 #define UCMODE0                                  EUSCI_A_CTLW0_MODE0             /*!< UCMODE Bit 0 */
2510 #define UCMODE1                                  EUSCI_A_CTLW0_MODE1             /*!< UCMODE Bit 1 */
2511 #define UCMODE_0                                 EUSCI_A_CTLW0_MODE_0            /*!< UART mode */
2512 #define UCMODE_1                                 EUSCI_A_CTLW0_MODE_1            /*!< Idle-line multiprocessor mode */
2513 #define UCMODE_2                                 EUSCI_A_CTLW0_MODE_2            /*!< Address-bit multiprocessor mode */
2514 #define UCMODE_3                                 EUSCI_A_CTLW0_MODE_3            /*!< UART mode with automatic baud-rate detection */
2515 /* UCA0CTLW0[UCSPB] Bits */
2516 #define UCSPB_OFS                                EUSCI_A_CTLW0_SPB_OFS           /*!< UCSPB Offset */
2517 #define UCSPB                                    EUSCI_A_CTLW0_SPB               /*!< Stop bit select */
2518 /* UCA0CTLW0[UC7BIT] Bits */
2519 #define UC7BIT_OFS                               EUSCI_A_CTLW0_SEVENBIT_OFS      /*!< UC7BIT Offset */
2520 #define UC7BIT                                   EUSCI_A_CTLW0_SEVENBIT          /*!< Character length */
2521 /* UCA0CTLW0[UCMSB] Bits */
2522 #define UCMSB_OFS                                EUSCI_A_CTLW0_MSB_OFS           /*!< UCMSB Offset */
2523 #define UCMSB                                    EUSCI_A_CTLW0_MSB               /*!< MSB first select */
2524 /* UCA0CTLW0[UCPAR] Bits */
2525 #define UCPAR_OFS                                EUSCI_A_CTLW0_PAR_OFS           /*!< UCPAR Offset */
2526 #define UCPAR                                    EUSCI_A_CTLW0_PAR               /*!< Parity select */
2527 /* UCA0CTLW0[UCPEN] Bits */
2528 #define UCPEN_OFS                                EUSCI_A_CTLW0_PEN_OFS           /*!< UCPEN Offset */
2529 #define UCPEN                                    EUSCI_A_CTLW0_PEN               /*!< Parity enable */
2530 /* UCA0CTLW0_SPI[UCSWRST] Bits */
2531 //#define UCSWRST_OFS                              EUSCI_A_CTLW0_SWRST_OFS         /*!< UCSWRST Offset */
2532 //#define UCSWRST                                  EUSCI_A_CTLW0_SWRST             /*!< Software reset enable */
2533 /* UCA0CTLW0_SPI[UCSTEM] Bits */
2534 #define UCSTEM_OFS                               EUSCI_A_CTLW0_STEM_OFS          /*!< UCSTEM Offset */
2535 #define UCSTEM                                   EUSCI_A_CTLW0_STEM              /*!< STE mode select in master mode. */
2536 /* UCA0CTLW0_SPI[UCSSEL] Bits */
2537 //#define UCSSEL_OFS                               EUSCI_A_CTLW0_SSEL_OFS          /*!< UCSSEL Offset */
2538 //#define UCSSEL_M                                 EUSCI_A_CTLW0_SSEL_MASK         /*!< eUSCI_A clock source select */
2539 //#define UCSSEL0                                  EUSCI_A_CTLW0_SSEL0             /*!< UCSSEL Bit 0 */
2540 //#define UCSSEL1                                  EUSCI_A_CTLW0_SSEL1             /*!< UCSSEL Bit 1 */
2541 //#define UCSSEL_0                                 EUSCI_A_CTLW0_UCSSEL_0          /*!< Reserved */
2542 //#define UCSSEL_1                                 EUSCI_A_CTLW0_UCSSEL_1          /*!< ACLK */
2543 //#define UCSSEL_2                                 EUSCI_A_CTLW0_UCSSEL_2          /*!< SMCLK */
2544 //#define UCSSEL__ACLK                             EUSCI_A_CTLW0_SSEL__ACLK        /*!< ACLK */
2545 //#define UCSSEL__SMCLK                            EUSCI_A_CTLW0_SSEL__SMCLK       /*!< SMCLK */
2546 /* UCA0CTLW0_SPI[UCSYNC] Bits */
2547 //#define UCSYNC_OFS                               EUSCI_A_CTLW0_SYNC_OFS          /*!< UCSYNC Offset */
2548 //#define UCSYNC                                   EUSCI_A_CTLW0_SYNC              /*!< Synchronous mode enable */
2549 /* UCA0CTLW0_SPI[UCMODE] Bits */
2550 //#define UCMODE_OFS                               EUSCI_A_CTLW0_MODE_OFS          /*!< UCMODE Offset */
2551 //#define UCMODE_M                                 EUSCI_A_CTLW0_MODE_MASK         /*!< eUSCI mode */
2552 //#define UCMODE0                                  EUSCI_A_CTLW0_MODE0             /*!< UCMODE Bit 0 */
2553 //#define UCMODE1                                  EUSCI_A_CTLW0_MODE1             /*!< UCMODE Bit 1 */
2554 //#define UCMODE_0                                 EUSCI_A_CTLW0_MODE_0            /*!< 3-pin SPI */
2555 //#define UCMODE_1                                 EUSCI_A_CTLW0_MODE_1            /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
2556 //#define UCMODE_2                                 EUSCI_A_CTLW0_MODE_2            /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
2557 /* UCA0CTLW0_SPI[UCMST] Bits */
2558 #define UCMST_OFS                                EUSCI_A_CTLW0_MST_OFS           /*!< UCMST Offset */
2559 #define UCMST                                    EUSCI_A_CTLW0_MST               /*!< Master mode select */
2560 /* UCA0CTLW0_SPI[UC7BIT] Bits */
2561 //#define UC7BIT_OFS                               EUSCI_A_CTLW0_SEVENBIT_OFS      /*!< UC7BIT Offset */
2562 //#define UC7BIT                                   EUSCI_A_CTLW0_SEVENBIT          /*!< Character length */
2563 /* UCA0CTLW0_SPI[UCMSB] Bits */
2564 //#define UCMSB_OFS                                EUSCI_A_CTLW0_MSB_OFS           /*!< UCMSB Offset */
2565 //#define UCMSB                                    EUSCI_A_CTLW0_MSB               /*!< MSB first select */
2566 /* UCA0CTLW0_SPI[UCCKPL] Bits */
2567 #define UCCKPL_OFS                               EUSCI_A_CTLW0_CKPL_OFS          /*!< UCCKPL Offset */
2568 #define UCCKPL                                   EUSCI_A_CTLW0_CKPL              /*!< Clock polarity select */
2569 /* UCA0CTLW0_SPI[UCCKPH] Bits */
2570 #define UCCKPH_OFS                               EUSCI_A_CTLW0_CKPH_OFS          /*!< UCCKPH Offset */
2571 #define UCCKPH                                   EUSCI_A_CTLW0_CKPH              /*!< Clock phase select */
2572 /* UCA0CTLW1[UCGLIT] Bits */
2573 #define UCGLIT_OFS                               EUSCI_A_CTLW1_GLIT_OFS          /*!< UCGLIT Offset */
2574 #define UCGLIT_M                                 EUSCI_A_CTLW1_GLIT_MASK         /*!< Deglitch time */
2575 #define UCGLIT0                                  EUSCI_A_CTLW1_GLIT0             /*!< UCGLIT Bit 0 */
2576 #define UCGLIT1                                  EUSCI_A_CTLW1_GLIT1             /*!< UCGLIT Bit 1 */
2577 #define UCGLIT_0                                 EUSCI_A_CTLW1_GLIT_0            /*!< Approximately 2 ns (equivalent of 1 delay element) */
2578 #define UCGLIT_1                                 EUSCI_A_CTLW1_GLIT_1            /*!< Approximately 50 ns */
2579 #define UCGLIT_2                                 EUSCI_A_CTLW1_GLIT_2            /*!< Approximately 100 ns */
2580 #define UCGLIT_3                                 EUSCI_A_CTLW1_GLIT_3            /*!< Approximately 200 ns */
2581 /* UCA0MCTLW[UCOS16] Bits */
2582 #define UCOS16_OFS                               EUSCI_A_MCTLW_OS16_OFS          /*!< UCOS16 Offset */
2583 #define UCOS16                                   EUSCI_A_MCTLW_OS16              /*!< Oversampling mode enabled */
2584 /* UCA0MCTLW[UCBRF] Bits */
2585 #define UCBRF_OFS                                EUSCI_A_MCTLW_BRF_OFS           /*!< UCBRF Offset */
2586 #define UCBRF_M                                  EUSCI_A_MCTLW_BRF_MASK          /*!< First modulation stage select */
2587 /* UCA0MCTLW[UCBRS] Bits */
2588 #define UCBRS_OFS                                EUSCI_A_MCTLW_BRS_OFS           /*!< UCBRS Offset */
2589 #define UCBRS_M                                  EUSCI_A_MCTLW_BRS_MASK          /*!< Second modulation stage select */
2590 /* UCA0STATW[UCBUSY] Bits */
2591 #define UCBUSY_OFS                               EUSCI_A_STATW_BUSY_OFS          /*!< UCBUSY Offset */
2592 #define UCBUSY                                   EUSCI_A_STATW_BUSY              /*!< eUSCI_A busy */
2593 /* UCA0STATW[UCADDR_UCIDLE] Bits */
2594 #define UCADDR_UCIDLE_OFS                        EUSCI_A_STATW_ADDR_IDLE_OFS     /*!< UCADDR_UCIDLE Offset */
2595 #define UCADDR_UCIDLE                            EUSCI_A_STATW_ADDR_IDLE         /*!< Address received / Idle line detected */
2596 /* UCA0STATW[UCRXERR] Bits */
2597 #define UCRXERR_OFS                              EUSCI_A_STATW_RXERR_OFS         /*!< UCRXERR Offset */
2598 #define UCRXERR                                  EUSCI_A_STATW_RXERR             /*!< Receive error flag */
2599 /* UCA0STATW[UCBRK] Bits */
2600 #define UCBRK_OFS                                EUSCI_A_STATW_BRK_OFS           /*!< UCBRK Offset */
2601 #define UCBRK                                    EUSCI_A_STATW_BRK               /*!< Break detect flag */
2602 /* UCA0STATW[UCPE] Bits */
2603 #define UCPE_OFS                                 EUSCI_A_STATW_PE_OFS            /*!< UCPE Offset */
2604 #define UCPE                                     EUSCI_A_STATW_PE
2605 /* UCA0STATW[UCOE] Bits */
2606 #define UCOE_OFS                                 EUSCI_A_STATW_OE_OFS            /*!< UCOE Offset */
2607 #define UCOE                                     EUSCI_A_STATW_OE                /*!< Overrun error flag */
2608 /* UCA0STATW[UCFE] Bits */
2609 #define UCFE_OFS                                 EUSCI_A_STATW_FE_OFS            /*!< UCFE Offset */
2610 #define UCFE                                     EUSCI_A_STATW_FE                /*!< Framing error flag */
2611 /* UCA0STATW[UCLISTEN] Bits */
2612 #define UCLISTEN_OFS                             EUSCI_A_STATW_LISTEN_OFS        /*!< UCLISTEN Offset */
2613 #define UCLISTEN                                 EUSCI_A_STATW_LISTEN            /*!< Listen enable */
2614 /* UCA0STATW_SPI[UCBUSY] Bits */
2615 //#define UCBUSY_OFS                               EUSCI_A_STATW_SPI_BUSY_OFS      /*!< UCBUSY Offset */
2616 //#define UCBUSY                                   EUSCI_A_STATW_SPI_BUSY          /*!< eUSCI_A busy */
2617 /* UCA0STATW_SPI[UCOE] Bits */
2618 //#define UCOE_OFS                                 EUSCI_A_STATW_OE_OFS            /*!< UCOE Offset */
2619 //#define UCOE                                     EUSCI_A_STATW_OE                /*!< Overrun error flag */
2620 /* UCA0STATW_SPI[UCFE] Bits */
2621 //#define UCFE_OFS                                 EUSCI_A_STATW_FE_OFS            /*!< UCFE Offset */
2622 //#define UCFE                                     EUSCI_A_STATW_FE                /*!< Framing error flag */
2623 /* UCA0STATW_SPI[UCLISTEN] Bits */
2624 //#define UCLISTEN_OFS                             EUSCI_A_STATW_LISTEN_OFS        /*!< UCLISTEN Offset */
2625 //#define UCLISTEN                                 EUSCI_A_STATW_LISTEN            /*!< Listen enable */
2626 /* UCA0RXBUF[UCRXBUF] Bits */
2627 #define UCRXBUF_OFS                              EUSCI_A_RXBUF_RXBUF_OFS         /*!< UCRXBUF Offset */
2628 #define UCRXBUF_M                                EUSCI_A_RXBUF_RXBUF_MASK        /*!< Receive data buffer */
2629 /* UCA0RXBUF_SPI[UCRXBUF] Bits */
2630 //#define UCRXBUF_OFS                              EUSCI_A_RXBUF_RXBUF_OFS         /*!< UCRXBUF Offset */
2631 //#define UCRXBUF_M                                EUSCI_A_RXBUF_RXBUF_MASK        /*!< Receive data buffer */
2632 /* UCA0TXBUF[UCTXBUF] Bits */
2633 #define UCTXBUF_OFS                              EUSCI_A_TXBUF_TXBUF_OFS         /*!< UCTXBUF Offset */
2634 #define UCTXBUF_M                                EUSCI_A_TXBUF_TXBUF_MASK        /*!< Transmit data buffer */
2635 /* UCA0TXBUF_SPI[UCTXBUF] Bits */
2636 //#define UCTXBUF_OFS                              EUSCI_A_TXBUF_TXBUF_OFS         /*!< UCTXBUF Offset */
2637 //#define UCTXBUF_M                                EUSCI_A_TXBUF_TXBUF_MASK        /*!< Transmit data buffer */
2638 /* UCA0ABCTL[UCABDEN] Bits */
2639 #define UCABDEN_OFS                              EUSCI_A_ABCTL_ABDEN_OFS         /*!< UCABDEN Offset */
2640 #define UCABDEN                                  EUSCI_A_ABCTL_ABDEN             /*!< Automatic baud-rate detect enable */
2641 /* UCA0ABCTL[UCBTOE] Bits */
2642 #define UCBTOE_OFS                               EUSCI_A_ABCTL_BTOE_OFS          /*!< UCBTOE Offset */
2643 #define UCBTOE                                   EUSCI_A_ABCTL_BTOE              /*!< Break time out error */
2644 /* UCA0ABCTL[UCSTOE] Bits */
2645 #define UCSTOE_OFS                               EUSCI_A_ABCTL_STOE_OFS          /*!< UCSTOE Offset */
2646 #define UCSTOE                                   EUSCI_A_ABCTL_STOE              /*!< Synch field time out error */
2647 /* UCA0ABCTL[UCDELIM] Bits */
2648 #define UCDELIM_OFS                              EUSCI_A_ABCTL_DELIM_OFS         /*!< UCDELIM Offset */
2649 #define UCDELIM_M                                EUSCI_A_ABCTL_DELIM_MASK        /*!< Break/synch delimiter length */
2650 #define UCDELIM0                                 EUSCI_A_ABCTL_DELIM0            /*!< UCDELIM Bit 0 */
2651 #define UCDELIM1                                 EUSCI_A_ABCTL_DELIM1            /*!< UCDELIM Bit 1 */
2652 #define UCDELIM_0                                EUSCI_A_ABCTL_DELIM_0           /*!< 1 bit time */
2653 #define UCDELIM_1                                EUSCI_A_ABCTL_DELIM_1           /*!< 2 bit times */
2654 #define UCDELIM_2                                EUSCI_A_ABCTL_DELIM_2           /*!< 3 bit times */
2655 #define UCDELIM_3                                EUSCI_A_ABCTL_DELIM_3           /*!< 4 bit times */
2656 /* UCA0IRCTL[UCIREN] Bits */
2657 #define UCIREN_OFS                               EUSCI_A_IRCTL_IREN_OFS          /*!< UCIREN Offset */
2658 #define UCIREN                                   EUSCI_A_IRCTL_IREN              /*!< IrDA encoder/decoder enable */
2659 /* UCA0IRCTL[UCIRTXCLK] Bits */
2660 #define UCIRTXCLK_OFS                            EUSCI_A_IRCTL_IRTXCLK_OFS       /*!< UCIRTXCLK Offset */
2661 #define UCIRTXCLK                                EUSCI_A_IRCTL_IRTXCLK           /*!< IrDA transmit pulse clock select */
2662 /* UCA0IRCTL[UCIRTXPL] Bits */
2663 #define UCIRTXPL_OFS                             EUSCI_A_IRCTL_IRTXPL_OFS        /*!< UCIRTXPL Offset */
2664 #define UCIRTXPL_M                               EUSCI_A_IRCTL_IRTXPL_MASK       /*!< Transmit pulse length */
2665 /* UCA0IRCTL[UCIRRXFE] Bits */
2666 #define UCIRRXFE_OFS                             EUSCI_A_IRCTL_IRRXFE_OFS        /*!< UCIRRXFE Offset */
2667 #define UCIRRXFE                                 EUSCI_A_IRCTL_IRRXFE            /*!< IrDA receive filter enabled */
2668 /* UCA0IRCTL[UCIRRXPL] Bits */
2669 #define UCIRRXPL_OFS                             EUSCI_A_IRCTL_IRRXPL_OFS        /*!< UCIRRXPL Offset */
2670 #define UCIRRXPL                                 EUSCI_A_IRCTL_IRRXPL            /*!< IrDA receive input UCAxRXD polarity */
2671 /* UCA0IRCTL[UCIRRXFL] Bits */
2672 #define UCIRRXFL_OFS                             EUSCI_A_IRCTL_IRRXFL_OFS        /*!< UCIRRXFL Offset */
2673 #define UCIRRXFL_M                               EUSCI_A_IRCTL_IRRXFL_MASK       /*!< Receive filter length */
2674 /* UCA0IE[UCRXIE] Bits */
2675 #define UCRXIE_OFS                               EUSCI_A_IE_RXIE_OFS             /*!< UCRXIE Offset */
2676 #define UCRXIE                                   EUSCI_A_IE_RXIE                 /*!< Receive interrupt enable */
2677 /* UCA0IE[UCTXIE] Bits */
2678 #define UCTXIE_OFS                               EUSCI_A_IE_TXIE_OFS             /*!< UCTXIE Offset */
2679 #define UCTXIE                                   EUSCI_A_IE_TXIE                 /*!< Transmit interrupt enable */
2680 /* UCA0IE[UCSTTIE] Bits */
2681 #define UCSTTIE_OFS                              EUSCI_A_IE_STTIE_OFS            /*!< UCSTTIE Offset */
2682 #define UCSTTIE                                  EUSCI_A_IE_STTIE                /*!< Start bit interrupt enable */
2683 /* UCA0IE[UCTXCPTIE] Bits */
2684 #define UCTXCPTIE_OFS                            EUSCI_A_IE_TXCPTIE_OFS          /*!< UCTXCPTIE Offset */
2685 #define UCTXCPTIE                                EUSCI_A_IE_TXCPTIE              /*!< Transmit complete interrupt enable */
2686 /* UCA0IE_SPI[UCRXIE] Bits */
2687 //#define UCRXIE_OFS                               EUSCI_A_IE_RXIE_OFS             /*!< UCRXIE Offset */
2688 //#define UCRXIE                                   EUSCI_A_IE_RXIE                 /*!< Receive interrupt enable */
2689 /* UCA0IE_SPI[UCTXIE] Bits */
2690 //#define UCTXIE_OFS                               EUSCI_A_IE_TXIE_OFS             /*!< UCTXIE Offset */
2691 //#define UCTXIE                                   EUSCI_A_IE_TXIE                 /*!< Transmit interrupt enable */
2692 /* UCA0IFG[UCRXIFG] Bits */
2693 #define UCRXIFG_OFS                              EUSCI_A_IFG_RXIFG_OFS           /*!< UCRXIFG Offset */
2694 #define UCRXIFG                                  EUSCI_A_IFG_RXIFG               /*!< Receive interrupt flag */
2695 /* UCA0IFG[UCTXIFG] Bits */
2696 #define UCTXIFG_OFS                              EUSCI_A_IFG_TXIFG_OFS           /*!< UCTXIFG Offset */
2697 #define UCTXIFG                                  EUSCI_A_IFG_TXIFG               /*!< Transmit interrupt flag */
2698 /* UCA0IFG[UCSTTIFG] Bits */
2699 #define UCSTTIFG_OFS                             EUSCI_A_IFG_STTIFG_OFS          /*!< UCSTTIFG Offset */
2700 #define UCSTTIFG                                 EUSCI_A_IFG_STTIFG              /*!< Start bit interrupt flag */
2701 /* UCA0IFG[UCTXCPTIFG] Bits */
2702 #define UCTXCPTIFG_OFS                           EUSCI_A_IFG_TXCPTIFG_OFS        /*!< UCTXCPTIFG Offset */
2703 #define UCTXCPTIFG                               EUSCI_A_IFG_TXCPTIFG            /*!< Transmit ready interrupt enable */
2704 /* UCA0IFG_SPI[UCRXIFG] Bits */
2705 //#define UCRXIFG_OFS                              EUSCI_A_IFG_RXIFG_OFS           /*!< UCRXIFG Offset */
2706 //#define UCRXIFG                                  EUSCI_A_IFG_RXIFG               /*!< Receive interrupt flag */
2707 /* UCA0IFG_SPI[UCTXIFG] Bits */
2708 //#define UCTXIFG_OFS                              EUSCI_A_IFG_TXIFG_OFS           /*!< UCTXIFG Offset */
2709 //#define UCTXIFG                                  EUSCI_A_IFG_TXIFG               /*!< Transmit interrupt flag */
2710 
2711 /******************************************************************************
2712 * EUSCI_B Bits (legacy section)
2713 ******************************************************************************/
2714 /* UCB0CTLW0[UCSWRST] Bits */
2715 //#define UCSWRST_OFS                              EUSCI_B_CTLW0_SWRST_OFS         /*!< UCSWRST Offset */
2716 //#define UCSWRST                                  EUSCI_B_CTLW0_SWRST             /*!< Software reset enable */
2717 /* UCB0CTLW0[UCTXSTT] Bits */
2718 #define UCTXSTT_OFS                              EUSCI_B_CTLW0_TXSTT_OFS         /*!< UCTXSTT Offset */
2719 #define UCTXSTT                                  EUSCI_B_CTLW0_TXSTT             /*!< Transmit START condition in master mode */
2720 /* UCB0CTLW0[UCTXSTP] Bits */
2721 #define UCTXSTP_OFS                              EUSCI_B_CTLW0_TXSTP_OFS         /*!< UCTXSTP Offset */
2722 #define UCTXSTP                                  EUSCI_B_CTLW0_TXSTP             /*!< Transmit STOP condition in master mode */
2723 /* UCB0CTLW0[UCTXNACK] Bits */
2724 #define UCTXNACK_OFS                             EUSCI_B_CTLW0_TXNACK_OFS        /*!< UCTXNACK Offset */
2725 #define UCTXNACK                                 EUSCI_B_CTLW0_TXNACK            /*!< Transmit a NACK */
2726 /* UCB0CTLW0[UCTR] Bits */
2727 #define UCTR_OFS                                 EUSCI_B_CTLW0_TR_OFS            /*!< UCTR Offset */
2728 #define UCTR                                     EUSCI_B_CTLW0_TR                /*!< Transmitter/receiver */
2729 /* UCB0CTLW0[UCTXACK] Bits */
2730 #define UCTXACK_OFS                              EUSCI_B_CTLW0_TXACK_OFS         /*!< UCTXACK Offset */
2731 #define UCTXACK                                  EUSCI_B_CTLW0_TXACK             /*!< Transmit ACK condition in slave mode */
2732 /* UCB0CTLW0[UCSSEL] Bits */
2733 //#define UCSSEL_OFS                               EUSCI_B_CTLW0_SSEL_OFS          /*!< UCSSEL Offset */
2734 //#define UCSSEL_M                                 EUSCI_B_CTLW0_SSEL_MASK         /*!< eUSCI_B clock source select */
2735 //#define UCSSEL0                                  EUSCI_B_CTLW0_SSEL0             /*!< UCSSEL Bit 0 */
2736 //#define UCSSEL1                                  EUSCI_B_CTLW0_SSEL1             /*!< UCSSEL Bit 1 */
2737 //#define UCSSEL_0                                 EUSCI_B_CTLW0_UCSSEL_0          /*!< UCLKI */
2738 //#define UCSSEL_1                                 EUSCI_B_CTLW0_UCSSEL_1          /*!< ACLK */
2739 //#define UCSSEL_2                                 EUSCI_B_CTLW0_UCSSEL_2          /*!< SMCLK */
2740 #define UCSSEL_3                                 EUSCI_B_CTLW0_UCSSEL_3          /*!< SMCLK */
2741 #define UCSSEL__UCLKI                            EUSCI_B_CTLW0_SSEL__UCLKI       /*!< UCLKI */
2742 //#define UCSSEL__ACLK                             EUSCI_B_CTLW0_SSEL__ACLK        /*!< ACLK */
2743 //#define UCSSEL__SMCLK                            EUSCI_B_CTLW0_SSEL__SMCLK       /*!< SMCLK */
2744 /* UCB0CTLW0[UCSYNC] Bits */
2745 //#define UCSYNC_OFS                               EUSCI_B_CTLW0_SYNC_OFS          /*!< UCSYNC Offset */
2746 //#define UCSYNC                                   EUSCI_B_CTLW0_SYNC              /*!< Synchronous mode enable */
2747 /* UCB0CTLW0[UCMODE] Bits */
2748 //#define UCMODE_OFS                               EUSCI_B_CTLW0_MODE_OFS          /*!< UCMODE Offset */
2749 //#define UCMODE_M                                 EUSCI_B_CTLW0_MODE_MASK         /*!< eUSCI_B mode */
2750 //#define UCMODE0                                  EUSCI_B_CTLW0_MODE0             /*!< UCMODE Bit 0 */
2751 //#define UCMODE1                                  EUSCI_B_CTLW0_MODE1             /*!< UCMODE Bit 1 */
2752 //#define UCMODE_0                                 EUSCI_B_CTLW0_MODE_0            /*!< 3-pin SPI */
2753 //#define UCMODE_1                                 EUSCI_B_CTLW0_MODE_1            /*!< 4-pin SPI (master or slave enabled if STE = 1) */
2754 //#define UCMODE_2                                 EUSCI_B_CTLW0_MODE_2            /*!< 4-pin SPI (master or slave enabled if STE = 0) */
2755 //#define UCMODE_3                                 EUSCI_B_CTLW0_MODE_3            /*!< I2C mode */
2756 /* UCB0CTLW0[UCMST] Bits */
2757 //#define UCMST_OFS                                EUSCI_B_CTLW0_MST_OFS           /*!< UCMST Offset */
2758 //#define UCMST                                    EUSCI_B_CTLW0_MST               /*!< Master mode select */
2759 /* UCB0CTLW0[UCMM] Bits */
2760 #define UCMM_OFS                                 EUSCI_B_CTLW0_MM_OFS            /*!< UCMM Offset */
2761 #define UCMM                                     EUSCI_B_CTLW0_MM                /*!< Multi-master environment select */
2762 /* UCB0CTLW0[UCSLA10] Bits */
2763 #define UCSLA10_OFS                              EUSCI_B_CTLW0_SLA10_OFS         /*!< UCSLA10 Offset */
2764 #define UCSLA10                                  EUSCI_B_CTLW0_SLA10             /*!< Slave addressing mode select */
2765 /* UCB0CTLW0[UCA10] Bits */
2766 #define UCA10_OFS                                EUSCI_B_CTLW0_A10_OFS           /*!< UCA10 Offset */
2767 #define UCA10                                    EUSCI_B_CTLW0_A10               /*!< Own addressing mode select */
2768 /* UCB0CTLW0_SPI[UCSWRST] Bits */
2769 //#define UCSWRST_OFS                              EUSCI_B_CTLW0_SWRST_OFS         /*!< UCSWRST Offset */
2770 //#define UCSWRST                                  EUSCI_B_CTLW0_SWRST             /*!< Software reset enable */
2771 /* UCB0CTLW0_SPI[UCSTEM] Bits */
2772 //#define UCSTEM_OFS                               EUSCI_B_CTLW0_STEM_OFS          /*!< UCSTEM Offset */
2773 //#define UCSTEM                                   EUSCI_B_CTLW0_STEM              /*!< STE mode select in master mode. */
2774 /* UCB0CTLW0_SPI[UCSSEL] Bits */
2775 //#define UCSSEL_OFS                               EUSCI_B_CTLW0_SSEL_OFS          /*!< UCSSEL Offset */
2776 //#define UCSSEL_M                                 EUSCI_B_CTLW0_SSEL_MASK         /*!< eUSCI_B clock source select */
2777 //#define UCSSEL0                                  EUSCI_B_CTLW0_SSEL0             /*!< UCSSEL Bit 0 */
2778 //#define UCSSEL1                                  EUSCI_B_CTLW0_SSEL1             /*!< UCSSEL Bit 1 */
2779 //#define UCSSEL_0                                 EUSCI_B_CTLW0_UCSSEL_0          /*!< Reserved */
2780 //#define UCSSEL_1                                 EUSCI_B_CTLW0_UCSSEL_1          /*!< ACLK */
2781 //#define UCSSEL_2                                 EUSCI_B_CTLW0_UCSSEL_2          /*!< SMCLK */
2782 //#define UCSSEL_3                                 EUSCI_B_CTLW0_UCSSEL_3          /*!< SMCLK */
2783 //#define UCSSEL__ACLK                             EUSCI_B_CTLW0_SSEL__ACLK        /*!< ACLK */
2784 //#define UCSSEL__SMCLK                            EUSCI_B_CTLW0_SSEL__SMCLK       /*!< SMCLK */
2785 /* UCB0CTLW0_SPI[UCSYNC] Bits */
2786 //#define UCSYNC_OFS                               EUSCI_B_CTLW0_SYNC_OFS          /*!< UCSYNC Offset */
2787 //#define UCSYNC                                   EUSCI_B_CTLW0_SYNC              /*!< Synchronous mode enable */
2788 /* UCB0CTLW0_SPI[UCMODE] Bits */
2789 //#define UCMODE_OFS                               EUSCI_B_CTLW0_MODE_OFS          /*!< UCMODE Offset */
2790 //#define UCMODE_M                                 EUSCI_B_CTLW0_MODE_MASK         /*!< eUSCI mode */
2791 //#define UCMODE0                                  EUSCI_B_CTLW0_MODE0             /*!< UCMODE Bit 0 */
2792 //#define UCMODE1                                  EUSCI_B_CTLW0_MODE1             /*!< UCMODE Bit 1 */
2793 //#define UCMODE_0                                 EUSCI_B_CTLW0_MODE_0            /*!< 3-pin SPI */
2794 //#define UCMODE_1                                 EUSCI_B_CTLW0_MODE_1            /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
2795 //#define UCMODE_2                                 EUSCI_B_CTLW0_MODE_2            /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
2796 //#define UCMODE_3                                 EUSCI_B_CTLW0_MODE_3            /*!< I2C mode */
2797 /* UCB0CTLW0_SPI[UCMST] Bits */
2798 //#define UCMST_OFS                                EUSCI_B_CTLW0_MST_OFS           /*!< UCMST Offset */
2799 //#define UCMST                                    EUSCI_B_CTLW0_MST               /*!< Master mode select */
2800 /* UCB0CTLW0_SPI[UC7BIT] Bits */
2801 //#define UC7BIT_OFS                               EUSCI_B_CTLW0_SEVENBIT_OFS      /*!< UC7BIT Offset */
2802 //#define UC7BIT                                   EUSCI_B_CTLW0_SEVENBIT          /*!< Character length */
2803 /* UCB0CTLW0_SPI[UCMSB] Bits */
2804 //#define UCMSB_OFS                                EUSCI_B_CTLW0_MSB_OFS           /*!< UCMSB Offset */
2805 //#define UCMSB                                    EUSCI_B_CTLW0_MSB               /*!< MSB first select */
2806 /* UCB0CTLW0_SPI[UCCKPL] Bits */
2807 //#define UCCKPL_OFS                               EUSCI_B_CTLW0_CKPL_OFS          /*!< UCCKPL Offset */
2808 //#define UCCKPL                                   EUSCI_B_CTLW0_CKPL              /*!< Clock polarity select */
2809 /* UCB0CTLW0_SPI[UCCKPH] Bits */
2810 //#define UCCKPH_OFS                               EUSCI_B_CTLW0_CKPH_OFS          /*!< UCCKPH Offset */
2811 //#define UCCKPH                                   EUSCI_B_CTLW0_CKPH              /*!< Clock phase select */
2812 /* UCB0CTLW1[UCGLIT] Bits */
2813 //#define UCGLIT_OFS                               EUSCI_B_CTLW1_GLIT_OFS          /*!< UCGLIT Offset */
2814 //#define UCGLIT_M                                 EUSCI_B_CTLW1_GLIT_MASK         /*!< Deglitch time */
2815 //#define UCGLIT0                                  EUSCI_B_CTLW1_GLIT0             /*!< UCGLIT Bit 0 */
2816 //#define UCGLIT1                                  EUSCI_B_CTLW1_GLIT1             /*!< UCGLIT Bit 1 */
2817 //#define UCGLIT_0                                 EUSCI_B_CTLW1_GLIT_0            /*!< 50 ns */
2818 //#define UCGLIT_1                                 EUSCI_B_CTLW1_GLIT_1            /*!< 25 ns */
2819 //#define UCGLIT_2                                 EUSCI_B_CTLW1_GLIT_2            /*!< 12.5 ns */
2820 //#define UCGLIT_3                                 EUSCI_B_CTLW1_GLIT_3            /*!< 6.25 ns */
2821 /* UCB0CTLW1[UCASTP] Bits */
2822 #define UCASTP_OFS                               EUSCI_B_CTLW1_ASTP_OFS          /*!< UCASTP Offset */
2823 #define UCASTP_M                                 EUSCI_B_CTLW1_ASTP_MASK         /*!< Automatic STOP condition generation */
2824 #define UCASTP0                                  EUSCI_B_CTLW1_ASTP0             /*!< UCASTP Bit 0 */
2825 #define UCASTP1                                  EUSCI_B_CTLW1_ASTP1             /*!< UCASTP Bit 1 */
2826 #define UCASTP_0                                 EUSCI_B_CTLW1_ASTP_0            /*!< No automatic STOP generation. The STOP condition is generated after the user  */
2827                                                                                  /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
2828 #define UCASTP_1                                 EUSCI_B_CTLW1_ASTP_1            /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in  */
2829                                                                                  /* UCBxTBCNT */
2830 #define UCASTP_2                                 EUSCI_B_CTLW1_ASTP_2            /*!< A STOP condition is generated automatically after the byte counter value  */
2831                                                                                  /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */
2832                                                                                  /* threshold */
2833 /* UCB0CTLW1[UCSWACK] Bits */
2834 #define UCSWACK_OFS                              EUSCI_B_CTLW1_SWACK_OFS         /*!< UCSWACK Offset */
2835 #define UCSWACK                                  EUSCI_B_CTLW1_SWACK             /*!< SW or HW ACK control */
2836 /* UCB0CTLW1[UCSTPNACK] Bits */
2837 #define UCSTPNACK_OFS                            EUSCI_B_CTLW1_STPNACK_OFS       /*!< UCSTPNACK Offset */
2838 #define UCSTPNACK                                EUSCI_B_CTLW1_STPNACK           /*!< ACK all master bytes */
2839 /* UCB0CTLW1[UCCLTO] Bits */
2840 #define UCCLTO_OFS                               EUSCI_B_CTLW1_CLTO_OFS          /*!< UCCLTO Offset */
2841 #define UCCLTO_M                                 EUSCI_B_CTLW1_CLTO_MASK         /*!< Clock low timeout select */
2842 #define UCCLTO0                                  EUSCI_B_CTLW1_CLTO0             /*!< UCCLTO Bit 0 */
2843 #define UCCLTO1                                  EUSCI_B_CTLW1_CLTO1             /*!< UCCLTO Bit 1 */
2844 #define UCCLTO_0                                 EUSCI_B_CTLW1_CLTO_0            /*!< Disable clock low timeout counter */
2845 #define UCCLTO_1                                 EUSCI_B_CTLW1_CLTO_1            /*!< 135 000 SYSCLK cycles (approximately 28 ms) */
2846 #define UCCLTO_2                                 EUSCI_B_CTLW1_CLTO_2            /*!< 150 000 SYSCLK cycles (approximately 31 ms) */
2847 #define UCCLTO_3                                 EUSCI_B_CTLW1_CLTO_3            /*!< 165 000 SYSCLK cycles (approximately 34 ms) */
2848 /* UCB0CTLW1[UCETXINT] Bits */
2849 #define UCETXINT_OFS                             EUSCI_B_CTLW1_ETXINT_OFS        /*!< UCETXINT Offset */
2850 #define UCETXINT                                 EUSCI_B_CTLW1_ETXINT            /*!< Early UCTXIFG0 */
2851 /* UCB0STATW[UCBBUSY] Bits */
2852 #define UCBBUSY_OFS                              EUSCI_B_STATW_BBUSY_OFS         /*!< UCBBUSY Offset */
2853 #define UCBBUSY                                  EUSCI_B_STATW_BBUSY             /*!< Bus busy */
2854 /* UCB0STATW[UCGC] Bits */
2855 #define UCGC_OFS                                 EUSCI_B_STATW_GC_OFS            /*!< UCGC Offset */
2856 #define UCGC                                     EUSCI_B_STATW_GC                /*!< General call address received */
2857 /* UCB0STATW[UCSCLLOW] Bits */
2858 #define UCSCLLOW_OFS                             EUSCI_B_STATW_SCLLOW_OFS        /*!< UCSCLLOW Offset */
2859 #define UCSCLLOW                                 EUSCI_B_STATW_SCLLOW            /*!< SCL low */
2860 /* UCB0STATW[UCBCNT] Bits */
2861 #define UCBCNT_OFS                               EUSCI_B_STATW_BCNT_OFS          /*!< UCBCNT Offset */
2862 #define UCBCNT_M                                 EUSCI_B_STATW_BCNT_MASK         /*!< Hardware byte counter value */
2863 /* UCB0STATW_SPI[UCBUSY] Bits */
2864 //#define UCBUSY_OFS                               EUSCI_B_STATW_SPI_BUSY_OFS      /*!< UCBUSY Offset */
2865 //#define UCBUSY                                   EUSCI_B_STATW_SPI_BUSY          /*!< eUSCI_B busy */
2866 /* UCB0STATW_SPI[UCOE] Bits */
2867 //#define UCOE_OFS                                 EUSCI_B_STATW_OE_OFS            /*!< UCOE Offset */
2868 //#define UCOE                                     EUSCI_B_STATW_OE                /*!< Overrun error flag */
2869 /* UCB0STATW_SPI[UCFE] Bits */
2870 //#define UCFE_OFS                                 EUSCI_B_STATW_FE_OFS            /*!< UCFE Offset */
2871 //#define UCFE                                     EUSCI_B_STATW_FE                /*!< Framing error flag */
2872 /* UCB0STATW_SPI[UCLISTEN] Bits */
2873 //#define UCLISTEN_OFS                             EUSCI_B_STATW_LISTEN_OFS        /*!< UCLISTEN Offset */
2874 //#define UCLISTEN                                 EUSCI_B_STATW_LISTEN            /*!< Listen enable */
2875 /* UCB0TBCNT[UCTBCNT] Bits */
2876 #define UCTBCNT_OFS                              EUSCI_B_TBCNT_TBCNT_OFS         /*!< UCTBCNT Offset */
2877 #define UCTBCNT_M                                EUSCI_B_TBCNT_TBCNT_MASK        /*!< Byte counter threshold value */
2878 /* UCB0RXBUF[UCRXBUF] Bits */
2879 //#define UCRXBUF_OFS                              EUSCI_B_RXBUF_RXBUF_OFS         /*!< UCRXBUF Offset */
2880 //#define UCRXBUF_M                                EUSCI_B_RXBUF_RXBUF_MASK        /*!< Receive data buffer */
2881 /* UCB0RXBUF_SPI[UCRXBUF] Bits */
2882 //#define UCRXBUF_OFS                              EUSCI_B_RXBUF_RXBUF_OFS         /*!< UCRXBUF Offset */
2883 //#define UCRXBUF_M                                EUSCI_B_RXBUF_RXBUF_MASK        /*!< Receive data buffer */
2884 /* UCB0TXBUF[UCTXBUF] Bits */
2885 //#define UCTXBUF_OFS                              EUSCI_B_TXBUF_TXBUF_OFS         /*!< UCTXBUF Offset */
2886 //#define UCTXBUF_M                                EUSCI_B_TXBUF_TXBUF_MASK        /*!< Transmit data buffer */
2887 /* UCB0TXBUF_SPI[UCTXBUF] Bits */
2888 //#define UCTXBUF_OFS                              EUSCI_B_TXBUF_TXBUF_OFS         /*!< UCTXBUF Offset */
2889 //#define UCTXBUF_M                                EUSCI_B_TXBUF_TXBUF_MASK        /*!< Transmit data buffer */
2890 /* UCB0I2COA0[I2COA0] Bits */
2891 #define I2COA0_OFS                               EUSCI_B_I2COA0_I2COA0_OFS       /*!< I2COA0 Offset */
2892 #define I2COA0_M                                 EUSCI_B_I2COA0_I2COA0_MASK      /*!< I2C own address */
2893 /* UCB0I2COA0[UCOAEN] Bits */
2894 #define UCOAEN_OFS                               EUSCI_B_I2COA0_OAEN_OFS         /*!< UCOAEN Offset */
2895 #define UCOAEN                                   EUSCI_B_I2COA0_OAEN             /*!< Own Address enable register */
2896 /* UCB0I2COA0[UCGCEN] Bits */
2897 #define UCGCEN_OFS                               EUSCI_B_I2COA0_GCEN_OFS         /*!< UCGCEN Offset */
2898 #define UCGCEN                                   EUSCI_B_I2COA0_GCEN             /*!< General call response enable */
2899 /* UCB0I2COA1[I2COA1] Bits */
2900 #define I2COA1_OFS                               EUSCI_B_I2COA1_I2COA1_OFS       /*!< I2COA1 Offset */
2901 #define I2COA1_M                                 EUSCI_B_I2COA1_I2COA1_MASK      /*!< I2C own address */
2902 /* UCB0I2COA1[UCOAEN] Bits */
2903 //#define UCOAEN_OFS                               EUSCI_B_I2COA1_OAEN_OFS         /*!< UCOAEN Offset */
2904 //#define UCOAEN                                   EUSCI_B_I2COA1_OAEN             /*!< Own Address enable register */
2905 /* UCB0I2COA2[I2COA2] Bits */
2906 #define I2COA2_OFS                               EUSCI_B_I2COA2_I2COA2_OFS       /*!< I2COA2 Offset */
2907 #define I2COA2_M                                 EUSCI_B_I2COA2_I2COA2_MASK      /*!< I2C own address */
2908 /* UCB0I2COA2[UCOAEN] Bits */
2909 //#define UCOAEN_OFS                               EUSCI_B_I2COA2_OAEN_OFS         /*!< UCOAEN Offset */
2910 //#define UCOAEN                                   EUSCI_B_I2COA2_OAEN             /*!< Own Address enable register */
2911 /* UCB0I2COA3[I2COA3] Bits */
2912 #define I2COA3_OFS                               EUSCI_B_I2COA3_I2COA3_OFS       /*!< I2COA3 Offset */
2913 #define I2COA3_M                                 EUSCI_B_I2COA3_I2COA3_MASK      /*!< I2C own address */
2914 /* UCB0I2COA3[UCOAEN] Bits */
2915 //#define UCOAEN_OFS                               EUSCI_B_I2COA3_OAEN_OFS         /*!< UCOAEN Offset */
2916 //#define UCOAEN                                   EUSCI_B_I2COA3_OAEN             /*!< Own Address enable register */
2917 /* UCB0ADDRX[ADDRX] Bits */
2918 #define ADDRX_OFS                                EUSCI_B_ADDRX_ADDRX_OFS         /*!< ADDRX Offset */
2919 #define ADDRX_M                                  EUSCI_B_ADDRX_ADDRX_MASK        /*!< Received Address Register */
2920 #define ADDRX0                                   EUSCI_B_ADDRX_ADDRX0            /*!< ADDRX Bit 0 */
2921 #define ADDRX1                                   EUSCI_B_ADDRX_ADDRX1            /*!< ADDRX Bit 1 */
2922 #define ADDRX2                                   EUSCI_B_ADDRX_ADDRX2            /*!< ADDRX Bit 2 */
2923 #define ADDRX3                                   EUSCI_B_ADDRX_ADDRX3            /*!< ADDRX Bit 3 */
2924 #define ADDRX4                                   EUSCI_B_ADDRX_ADDRX4            /*!< ADDRX Bit 4 */
2925 #define ADDRX5                                   EUSCI_B_ADDRX_ADDRX5            /*!< ADDRX Bit 5 */
2926 #define ADDRX6                                   EUSCI_B_ADDRX_ADDRX6            /*!< ADDRX Bit 6 */
2927 #define ADDRX7                                   EUSCI_B_ADDRX_ADDRX7            /*!< ADDRX Bit 7 */
2928 #define ADDRX8                                   EUSCI_B_ADDRX_ADDRX8            /*!< ADDRX Bit 8 */
2929 #define ADDRX9                                   EUSCI_B_ADDRX_ADDRX9            /*!< ADDRX Bit 9 */
2930 /* UCB0ADDMASK[ADDMASK] Bits */
2931 #define ADDMASK_OFS                              EUSCI_B_ADDMASK_ADDMASK_OFS     /*!< ADDMASK Offset */
2932 #define ADDMASK_M                                EUSCI_B_ADDMASK_ADDMASK_MASK
2933 /* UCB0I2CSA[I2CSA] Bits */
2934 #define I2CSA_OFS                                EUSCI_B_I2CSA_I2CSA_OFS         /*!< I2CSA Offset */
2935 #define I2CSA_M                                  EUSCI_B_I2CSA_I2CSA_MASK        /*!< I2C slave address */
2936 /* UCB0IE[UCRXIE0] Bits */
2937 #define UCRXIE0_OFS                              EUSCI_B_IE_RXIE0_OFS            /*!< UCRXIE0 Offset */
2938 #define UCRXIE0                                  EUSCI_B_IE_RXIE0                /*!< Receive interrupt enable 0 */
2939 /* UCB0IE[UCTXIE0] Bits */
2940 #define UCTXIE0_OFS                              EUSCI_B_IE_TXIE0_OFS            /*!< UCTXIE0 Offset */
2941 #define UCTXIE0                                  EUSCI_B_IE_TXIE0                /*!< Transmit interrupt enable 0 */
2942 /* UCB0IE[UCSTTIE] Bits */
2943 //#define UCSTTIE_OFS                              EUSCI_B_IE_STTIE_OFS            /*!< UCSTTIE Offset */
2944 //#define UCSTTIE                                  EUSCI_B_IE_STTIE                /*!< START condition interrupt enable */
2945 /* UCB0IE[UCSTPIE] Bits */
2946 #define UCSTPIE_OFS                              EUSCI_B_IE_STPIE_OFS            /*!< UCSTPIE Offset */
2947 #define UCSTPIE                                  EUSCI_B_IE_STPIE                /*!< STOP condition interrupt enable */
2948 /* UCB0IE[UCALIE] Bits */
2949 #define UCALIE_OFS                               EUSCI_B_IE_ALIE_OFS             /*!< UCALIE Offset */
2950 #define UCALIE                                   EUSCI_B_IE_ALIE                 /*!< Arbitration lost interrupt enable */
2951 /* UCB0IE[UCNACKIE] Bits */
2952 #define UCNACKIE_OFS                             EUSCI_B_IE_NACKIE_OFS           /*!< UCNACKIE Offset */
2953 #define UCNACKIE                                 EUSCI_B_IE_NACKIE               /*!< Not-acknowledge interrupt enable */
2954 /* UCB0IE[UCBCNTIE] Bits */
2955 #define UCBCNTIE_OFS                             EUSCI_B_IE_BCNTIE_OFS           /*!< UCBCNTIE Offset */
2956 #define UCBCNTIE                                 EUSCI_B_IE_BCNTIE               /*!< Byte counter interrupt enable */
2957 /* UCB0IE[UCCLTOIE] Bits */
2958 #define UCCLTOIE_OFS                             EUSCI_B_IE_CLTOIE_OFS           /*!< UCCLTOIE Offset */
2959 #define UCCLTOIE                                 EUSCI_B_IE_CLTOIE               /*!< Clock low timeout interrupt enable */
2960 /* UCB0IE[UCRXIE1] Bits */
2961 #define UCRXIE1_OFS                              EUSCI_B_IE_RXIE1_OFS            /*!< UCRXIE1 Offset */
2962 #define UCRXIE1                                  EUSCI_B_IE_RXIE1                /*!< Receive interrupt enable 1 */
2963 /* UCB0IE[UCTXIE1] Bits */
2964 #define UCTXIE1_OFS                              EUSCI_B_IE_TXIE1_OFS            /*!< UCTXIE1 Offset */
2965 #define UCTXIE1                                  EUSCI_B_IE_TXIE1                /*!< Transmit interrupt enable 1 */
2966 /* UCB0IE[UCRXIE2] Bits */
2967 #define UCRXIE2_OFS                              EUSCI_B_IE_RXIE2_OFS            /*!< UCRXIE2 Offset */
2968 #define UCRXIE2                                  EUSCI_B_IE_RXIE2                /*!< Receive interrupt enable 2 */
2969 /* UCB0IE[UCTXIE2] Bits */
2970 #define UCTXIE2_OFS                              EUSCI_B_IE_TXIE2_OFS            /*!< UCTXIE2 Offset */
2971 #define UCTXIE2                                  EUSCI_B_IE_TXIE2                /*!< Transmit interrupt enable 2 */
2972 /* UCB0IE[UCRXIE3] Bits */
2973 #define UCRXIE3_OFS                              EUSCI_B_IE_RXIE3_OFS            /*!< UCRXIE3 Offset */
2974 #define UCRXIE3                                  EUSCI_B_IE_RXIE3                /*!< Receive interrupt enable 3 */
2975 /* UCB0IE[UCTXIE3] Bits */
2976 #define UCTXIE3_OFS                              EUSCI_B_IE_TXIE3_OFS            /*!< UCTXIE3 Offset */
2977 #define UCTXIE3                                  EUSCI_B_IE_TXIE3                /*!< Transmit interrupt enable 3 */
2978 /* UCB0IE[UCBIT9IE] Bits */
2979 #define UCBIT9IE_OFS                             EUSCI_B_IE_BIT9IE_OFS           /*!< UCBIT9IE Offset */
2980 #define UCBIT9IE                                 EUSCI_B_IE_BIT9IE               /*!< Bit position 9 interrupt enable */
2981 /* UCB0IE_SPI[UCRXIE] Bits */
2982 //#define UCRXIE_OFS                               EUSCI_B_IE_RXIE_OFS             /*!< UCRXIE Offset */
2983 //#define UCRXIE                                   EUSCI_B_IE_RXIE                 /*!< Receive interrupt enable */
2984 /* UCB0IE_SPI[UCTXIE] Bits */
2985 //#define UCTXIE_OFS                               EUSCI_B_IE_TXIE_OFS             /*!< UCTXIE Offset */
2986 //#define UCTXIE                                   EUSCI_B_IE_TXIE                 /*!< Transmit interrupt enable */
2987 /* UCB0IFG[UCRXIFG0] Bits */
2988 #define UCRXIFG0_OFS                             EUSCI_B_IFG_RXIFG0_OFS          /*!< UCRXIFG0 Offset */
2989 #define UCRXIFG0                                 EUSCI_B_IFG_RXIFG0              /*!< eUSCI_B receive interrupt flag 0 */
2990 /* UCB0IFG[UCTXIFG0] Bits */
2991 #define UCTXIFG0_OFS                             EUSCI_B_IFG_TXIFG0_OFS          /*!< UCTXIFG0 Offset */
2992 #define UCTXIFG0                                 EUSCI_B_IFG_TXIFG0              /*!< eUSCI_B transmit interrupt flag 0 */
2993 /* UCB0IFG[UCSTTIFG] Bits */
2994 //#define UCSTTIFG_OFS                             EUSCI_B_IFG_STTIFG_OFS          /*!< UCSTTIFG Offset */
2995 //#define UCSTTIFG                                 EUSCI_B_IFG_STTIFG              /*!< START condition interrupt flag */
2996 /* UCB0IFG[UCSTPIFG] Bits */
2997 #define UCSTPIFG_OFS                             EUSCI_B_IFG_STPIFG_OFS          /*!< UCSTPIFG Offset */
2998 #define UCSTPIFG                                 EUSCI_B_IFG_STPIFG              /*!< STOP condition interrupt flag */
2999 /* UCB0IFG[UCALIFG] Bits */
3000 #define UCALIFG_OFS                              EUSCI_B_IFG_ALIFG_OFS           /*!< UCALIFG Offset */
3001 #define UCALIFG                                  EUSCI_B_IFG_ALIFG               /*!< Arbitration lost interrupt flag */
3002 /* UCB0IFG[UCNACKIFG] Bits */
3003 #define UCNACKIFG_OFS                            EUSCI_B_IFG_NACKIFG_OFS         /*!< UCNACKIFG Offset */
3004 #define UCNACKIFG                                EUSCI_B_IFG_NACKIFG             /*!< Not-acknowledge received interrupt flag */
3005 /* UCB0IFG[UCBCNTIFG] Bits */
3006 #define UCBCNTIFG_OFS                            EUSCI_B_IFG_BCNTIFG_OFS         /*!< UCBCNTIFG Offset */
3007 #define UCBCNTIFG                                EUSCI_B_IFG_BCNTIFG             /*!< Byte counter interrupt flag */
3008 /* UCB0IFG[UCCLTOIFG] Bits */
3009 #define UCCLTOIFG_OFS                            EUSCI_B_IFG_CLTOIFG_OFS         /*!< UCCLTOIFG Offset */
3010 #define UCCLTOIFG                                EUSCI_B_IFG_CLTOIFG             /*!< Clock low timeout interrupt flag */
3011 /* UCB0IFG[UCRXIFG1] Bits */
3012 #define UCRXIFG1_OFS                             EUSCI_B_IFG_RXIFG1_OFS          /*!< UCRXIFG1 Offset */
3013 #define UCRXIFG1                                 EUSCI_B_IFG_RXIFG1              /*!< eUSCI_B receive interrupt flag 1 */
3014 /* UCB0IFG[UCTXIFG1] Bits */
3015 #define UCTXIFG1_OFS                             EUSCI_B_IFG_TXIFG1_OFS          /*!< UCTXIFG1 Offset */
3016 #define UCTXIFG1                                 EUSCI_B_IFG_TXIFG1              /*!< eUSCI_B transmit interrupt flag 1 */
3017 /* UCB0IFG[UCRXIFG2] Bits */
3018 #define UCRXIFG2_OFS                             EUSCI_B_IFG_RXIFG2_OFS          /*!< UCRXIFG2 Offset */
3019 #define UCRXIFG2                                 EUSCI_B_IFG_RXIFG2              /*!< eUSCI_B receive interrupt flag 2 */
3020 /* UCB0IFG[UCTXIFG2] Bits */
3021 #define UCTXIFG2_OFS                             EUSCI_B_IFG_TXIFG2_OFS          /*!< UCTXIFG2 Offset */
3022 #define UCTXIFG2                                 EUSCI_B_IFG_TXIFG2              /*!< eUSCI_B transmit interrupt flag 2 */
3023 /* UCB0IFG[UCRXIFG3] Bits */
3024 #define UCRXIFG3_OFS                             EUSCI_B_IFG_RXIFG3_OFS          /*!< UCRXIFG3 Offset */
3025 #define UCRXIFG3                                 EUSCI_B_IFG_RXIFG3              /*!< eUSCI_B receive interrupt flag 3 */
3026 /* UCB0IFG[UCTXIFG3] Bits */
3027 #define UCTXIFG3_OFS                             EUSCI_B_IFG_TXIFG3_OFS          /*!< UCTXIFG3 Offset */
3028 #define UCTXIFG3                                 EUSCI_B_IFG_TXIFG3              /*!< eUSCI_B transmit interrupt flag 3 */
3029 /* UCB0IFG[UCBIT9IFG] Bits */
3030 #define UCBIT9IFG_OFS                            EUSCI_B_IFG_BIT9IFG_OFS         /*!< UCBIT9IFG Offset */
3031 #define UCBIT9IFG                                EUSCI_B_IFG_BIT9IFG             /*!< Bit position 9 interrupt flag */
3032 /* UCB0IFG_SPI[UCRXIFG] Bits */
3033 //#define UCRXIFG_OFS                              EUSCI_B_IFG_RXIFG_OFS           /*!< UCRXIFG Offset */
3034 //#define UCRXIFG                                  EUSCI_B_IFG_RXIFG               /*!< Receive interrupt flag */
3035 /* UCB0IFG_SPI[UCTXIFG] Bits */
3036 //#define UCTXIFG_OFS                              EUSCI_B_IFG_TXIFG_OFS           /*!< UCTXIFG Offset */
3037 //#define UCTXIFG                                  EUSCI_B_IFG_TXIFG               /*!< Transmit interrupt flag */
3038 
3039 /******************************************************************************
3040 * PMAP Bits (legacy section)
3041 ******************************************************************************/
3042 /* PMAPCTL[PMAPLOCKED] Bits */
3043 #define PMAPLOCKED_OFS                           PMAP_CTL_LOCKED_OFS             /*!< PMAPLOCKED Offset */
3044 #define PMAPLOCKED                               PMAP_CTL_LOCKED                 /*!< Port mapping lock bit */
3045 /* PMAPCTL[PMAPRECFG] Bits */
3046 #define PMAPRECFG_OFS                            PMAP_CTL_PRECFG_OFS             /*!< PMAPRECFG Offset */
3047 #define PMAPRECFG                                PMAP_CTL_PRECFG                 /*!< Port mapping reconfiguration control bit */
3048 /* Pre-defined bitfield values */
3049 /* PMAP_PMAPCTL[PMAPLOCKED] Bits */
3050 #define PMAPLOCKED_OFS                                     PMAP_CTL_LOCKED_OFS   /*!< PMAPLOCKED Offset */
3051 #define PMAPLOCKED                                         PMAP_CTL_LOCKED       /*!< Port mapping lock bit */
3052 /* PMAP_PMAPCTL[PMAPRECFG] Bits */
3053 #define PMAPRECFG_OFS                                      PMAP_CTL_PRECFG_OFS   /*!< PMAPRECFG Offset */
3054 #define PMAPRECFG                                          PMAP_CTL_PRECFG       /*!< Port mapping reconfiguration control bit */
3055 
3056 #define PM_NONE                                            PMAP_NONE
3057 #define PM_UCA0CLK                                         PMAP_UCA0CLK
3058 #define PM_UCA0RXD                                         PMAP_UCA0RXD
3059 #define PM_UCA0SOMI                                        PMAP_UCA0SOMI
3060 #define PM_UCA0TXD                                         PMAP_UCA0TXD
3061 #define PM_UCA0SIMO                                        PMAP_UCA0SIMO
3062 #define PM_UCB0CLK                                         PMAP_UCB0CLK
3063 #define PM_UCB0SDA                                         PMAP_UCB0SDA
3064 #define PM_UCB0SIMO                                        PMAP_UCB0SIMO
3065 #define PM_UCB0SCL                                         PMAP_UCB0SCL
3066 #define PM_UCB0SOMI                                        PMAP_UCB0SOMI
3067 #define PM_UCA1STE                                         PMAP_UCA1STE
3068 #define PM_UCA1CLK                                         PMAP_UCA1CLK
3069 #define PM_UCA1RXD                                         PMAP_UCA1RXD
3070 #define PM_UCA1SOMI                                        PMAP_UCA1SOMI
3071 #define PM_UCA1TXD                                         PMAP_UCA1TXD
3072 #define PM_UCA1SIMO                                        PMAP_UCA1SIMO
3073 #define PM_UCA2STE                                         PMAP_UCA2STE
3074 #define PM_UCA2CLK                                         PMAP_UCA2CLK
3075 #define PM_UCA2RXD                                         PMAP_UCA2RXD
3076 #define PM_UCA2SOMI                                        PMAP_UCA2SOMI
3077 #define PM_UCA2TXD                                         PMAP_UCA2TXD
3078 #define PM_UCA2SIMO                                        PMAP_UCA2SIMO
3079 #define PM_UCB2STE                                         PMAP_UCB2STE
3080 #define PM_UCB2CLK                                         PMAP_UCB2CLK
3081 #define PM_UCB2SDA                                         PMAP_UCB2SDA
3082 #define PM_UCB2SIMO                                        PMAP_UCB2SIMO
3083 #define PM_UCB2SCL                                         PMAP_UCB2SCL
3084 #define PM_UCB2SOMI                                        PMAP_UCB2SOMI
3085 #define PM_TA0CCR0A                                        PMAP_TA0CCR0A
3086 #define PM_TA0CCR1A                                        PMAP_TA0CCR1A
3087 #define PM_TA0CCR2A                                        PMAP_TA0CCR2A
3088 #define PM_TA0CCR3A                                        PMAP_TA0CCR3A
3089 #define PM_TA0CCR4A                                        PMAP_TA0CCR4A
3090 #define PM_TA1CCR1A                                        PMAP_TA1CCR1A
3091 #define PM_TA1CCR2A                                        PMAP_TA1CCR2A
3092 #define PM_TA1CCR3A                                        PMAP_TA1CCR3A
3093 #define PM_TA1CCR4A                                        PMAP_TA1CCR4A
3094 #define PM_TA0CLK                                          PMAP_TA0CLK
3095 #define PM_CE0OUT                                          PMAP_CE0OUT
3096 #define PM_TA1CLK                                          PMAP_TA1CLK
3097 #define PM_CE1OUT                                          PMAP_CE1OUT
3098 #define PM_DMAE0                                           PMAP_DMAE0
3099 #define PM_SMCLK                                           PMAP_SMCLK
3100 #define PM_ANALOG                                          PMAP_ANALOG
3101 
3102 #define PMAPKEY                                            PMAP_KEYID_VAL        /*!< Port Mapping Key */
3103 #define PMAPPWD                                            PMAP_KEYID_VAL        /*!< Legacy Definition: Mapping Key register */
3104 #define PMAPPW                                             PMAP_KEYID_VAL        /*!< Legacy Definition: Port Mapping Password */
3105 
3106 
3107 /******************************************************************************
3108 * REF_A Bits (legacy section)
3109 ******************************************************************************/
3110 /* REFCTL0[REFON] Bits */
3111 #define REFON_OFS                                REF_A_CTL0_ON_OFS               /*!< REFON Offset */
3112 #define REFON                                    REF_A_CTL0_ON                   /*!< Reference enable */
3113 /* REFCTL0[REFOUT] Bits */
3114 #define REFOUT_OFS                               REF_A_CTL0_OUT_OFS              /*!< REFOUT Offset */
3115 #define REFOUT                                   REF_A_CTL0_OUT                  /*!< Reference output buffer */
3116 /* REFCTL0[REFTCOFF] Bits */
3117 #define REFTCOFF_OFS                             REF_A_CTL0_TCOFF_OFS            /*!< REFTCOFF Offset */
3118 #define REFTCOFF                                 REF_A_CTL0_TCOFF                /*!< Temperature sensor disabled */
3119 /* REFCTL0[REFVSEL] Bits */
3120 #define REFVSEL_OFS                              REF_A_CTL0_VSEL_OFS             /*!< REFVSEL Offset */
3121 #define REFVSEL_M                                REF_A_CTL0_VSEL_MASK            /*!< Reference voltage level select */
3122 #define REFVSEL0                                 REF_A_CTL0_VSEL0                /*!< REFVSEL Bit 0 */
3123 #define REFVSEL1                                 REF_A_CTL0_VSEL1                /*!< REFVSEL Bit 1 */
3124 #define REFVSEL_0                                REF_A_CTL0_VSEL_0               /*!< 1.2 V available when reference requested or REFON = 1 */
3125 #define REFVSEL_1                                REF_A_CTL0_VSEL_1               /*!< 1.45 V available when reference requested or REFON = 1 */
3126 #define REFVSEL_3                                REF_A_CTL0_VSEL_3               /*!< 2.5 V available when reference requested or REFON = 1 */
3127 /* REFCTL0[REFGENOT] Bits */
3128 #define REFGENOT_OFS                             REF_A_CTL0_GENOT_OFS            /*!< REFGENOT Offset */
3129 #define REFGENOT                                 REF_A_CTL0_GENOT                /*!< Reference generator one-time trigger */
3130 /* REFCTL0[REFBGOT] Bits */
3131 #define REFBGOT_OFS                              REF_A_CTL0_BGOT_OFS             /*!< REFBGOT Offset */
3132 #define REFBGOT                                  REF_A_CTL0_BGOT                 /*!< Bandgap and bandgap buffer one-time trigger */
3133 /* REFCTL0[REFGENACT] Bits */
3134 #define REFGENACT_OFS                            REF_A_CTL0_GENACT_OFS           /*!< REFGENACT Offset */
3135 #define REFGENACT                                REF_A_CTL0_GENACT               /*!< Reference generator active */
3136 /* REFCTL0[REFBGACT] Bits */
3137 #define REFBGACT_OFS                             REF_A_CTL0_BGACT_OFS            /*!< REFBGACT Offset */
3138 #define REFBGACT                                 REF_A_CTL0_BGACT                /*!< Reference bandgap active */
3139 /* REFCTL0[REFGENBUSY] Bits */
3140 #define REFGENBUSY_OFS                           REF_A_CTL0_GENBUSY_OFS          /*!< REFGENBUSY Offset */
3141 #define REFGENBUSY                               REF_A_CTL0_GENBUSY              /*!< Reference generator busy */
3142 /* REFCTL0[BGMODE] Bits */
3143 #define BGMODE_OFS                               REF_A_CTL0_BGMODE_OFS           /*!< BGMODE Offset */
3144 #define BGMODE                                   REF_A_CTL0_BGMODE               /*!< Bandgap mode */
3145 /* REFCTL0[REFGENRDY] Bits */
3146 #define REFGENRDY_OFS                            REF_A_CTL0_GENRDY_OFS           /*!< REFGENRDY Offset */
3147 #define REFGENRDY                                REF_A_CTL0_GENRDY               /*!< Variable reference voltage ready status */
3148 /* REFCTL0[REFBGRDY] Bits */
3149 #define REFBGRDY_OFS                             REF_A_CTL0_BGRDY_OFS            /*!< REFBGRDY Offset */
3150 #define REFBGRDY                                 REF_A_CTL0_BGRDY                /*!< Buffered bandgap voltage ready status */
3151 
3152 /******************************************************************************
3153 * RTC_C Bits (legacy section)
3154 ******************************************************************************/
3155 /* RTCCTL0[RTCRDYIFG] Bits */
3156 #define RTCRDYIFG_OFS                            RTC_C_CTL0_RDYIFG_OFS           /*!< RTCRDYIFG Offset */
3157 #define RTCRDYIFG                                RTC_C_CTL0_RDYIFG               /*!< Real-time clock ready interrupt flag */
3158 /* RTCCTL0[RTCAIFG] Bits */
3159 #define RTCAIFG_OFS                              RTC_C_CTL0_AIFG_OFS             /*!< RTCAIFG Offset */
3160 #define RTCAIFG                                  RTC_C_CTL0_AIFG                 /*!< Real-time clock alarm interrupt flag */
3161 /* RTCCTL0[RTCTEVIFG] Bits */
3162 #define RTCTEVIFG_OFS                            RTC_C_CTL0_TEVIFG_OFS           /*!< RTCTEVIFG Offset */
3163 #define RTCTEVIFG                                RTC_C_CTL0_TEVIFG               /*!< Real-time clock time event interrupt flag */
3164 /* RTCCTL0[RTCOFIFG] Bits */
3165 #define RTCOFIFG_OFS                             RTC_C_CTL0_OFIFG_OFS            /*!< RTCOFIFG Offset */
3166 #define RTCOFIFG                                 RTC_C_CTL0_OFIFG                /*!< 32-kHz crystal oscillator fault interrupt flag */
3167 /* RTCCTL0[RTCRDYIE] Bits */
3168 #define RTCRDYIE_OFS                             RTC_C_CTL0_RDYIE_OFS            /*!< RTCRDYIE Offset */
3169 #define RTCRDYIE                                 RTC_C_CTL0_RDYIE                /*!< Real-time clock ready interrupt enable */
3170 /* RTCCTL0[RTCAIE] Bits */
3171 #define RTCAIE_OFS                               RTC_C_CTL0_AIE_OFS              /*!< RTCAIE Offset */
3172 #define RTCAIE                                   RTC_C_CTL0_AIE                  /*!< Real-time clock alarm interrupt enable */
3173 /* RTCCTL0[RTCTEVIE] Bits */
3174 #define RTCTEVIE_OFS                             RTC_C_CTL0_TEVIE_OFS            /*!< RTCTEVIE Offset */
3175 #define RTCTEVIE                                 RTC_C_CTL0_TEVIE                /*!< Real-time clock time event interrupt enable */
3176 /* RTCCTL0[RTCOFIE] Bits */
3177 #define RTCOFIE_OFS                              RTC_C_CTL0_OFIE_OFS             /*!< RTCOFIE Offset */
3178 #define RTCOFIE                                  RTC_C_CTL0_OFIE                 /*!< 32-kHz crystal oscillator fault interrupt enable */
3179 /* RTCCTL0[RTCKEY] Bits */
3180 #define RTCKEY_OFS                               RTC_C_CTL0_KEY_OFS              /*!< RTCKEY Offset */
3181 #define RTCKEY_M                                 RTC_C_CTL0_KEY_MASK             /*!< Real-time clock key */
3182 /* RTCCTL13[RTCTEV] Bits */
3183 #define RTCTEV_OFS                               RTC_C_CTL13_TEV_OFS             /*!< RTCTEV Offset */
3184 #define RTCTEV_M                                 RTC_C_CTL13_TEV_MASK            /*!< Real-time clock time event */
3185 #define RTCTEV0                                  RTC_C_CTL13_TEV0                /*!< RTCTEV Bit 0 */
3186 #define RTCTEV1                                  RTC_C_CTL13_TEV1                /*!< RTCTEV Bit 1 */
3187 #define RTCTEV_0                                 RTC_C_CTL13_TEV_0               /*!< Minute changed */
3188 #define RTCTEV_1                                 RTC_C_CTL13_TEV_1               /*!< Hour changed */
3189 #define RTCTEV_2                                 RTC_C_CTL13_TEV_2               /*!< Every day at midnight (00:00) */
3190 #define RTCTEV_3                                 RTC_C_CTL13_TEV_3               /*!< Every day at noon (12:00) */
3191 /* RTCCTL13[RTCSSEL] Bits */
3192 #define RTCSSEL_OFS                              RTC_C_CTL13_SSEL_OFS            /*!< RTCSSEL Offset */
3193 #define RTCSSEL_M                                RTC_C_CTL13_SSEL_MASK           /*!< Real-time clock source select */
3194 #define RTCSSEL0                                 RTC_C_CTL13_SSEL0               /*!< RTCSSEL Bit 0 */
3195 #define RTCSSEL1                                 RTC_C_CTL13_SSEL1               /*!< RTCSSEL Bit 1 */
3196 #define RTCSSEL_0                                RTC_C_CTL13_SSEL_0              /*!< BCLK */
3197 #define RTCSSEL__BCLK                            RTC_C_CTL13_SSEL__BCLK          /*!< BCLK */
3198 /* RTCCTL13[RTCRDY] Bits */
3199 #define RTCRDY_OFS                               RTC_C_CTL13_RDY_OFS             /*!< RTCRDY Offset */
3200 #define RTCRDY                                   RTC_C_CTL13_RDY                 /*!< Real-time clock ready */
3201 /* RTCCTL13[RTCMODE] Bits */
3202 #define RTCMODE_OFS                              RTC_C_CTL13_MODE_OFS            /*!< RTCMODE Offset */
3203 #define RTCMODE                                  RTC_C_CTL13_MODE
3204 /* RTCCTL13[RTCHOLD] Bits */
3205 #define RTCHOLD_OFS                              RTC_C_CTL13_HOLD_OFS            /*!< RTCHOLD Offset */
3206 #define RTCHOLD                                  RTC_C_CTL13_HOLD                /*!< Real-time clock hold */
3207 /* RTCCTL13[RTCBCD] Bits */
3208 #define RTCBCD_OFS                               RTC_C_CTL13_BCD_OFS             /*!< RTCBCD Offset */
3209 #define RTCBCD                                   RTC_C_CTL13_BCD                 /*!< Real-time clock BCD select */
3210 /* RTCCTL13[RTCCALF] Bits */
3211 #define RTCCALF_OFS                              RTC_C_CTL13_CALF_OFS            /*!< RTCCALF Offset */
3212 #define RTCCALF_M                                RTC_C_CTL13_CALF_MASK           /*!< Real-time clock calibration frequency */
3213 #define RTCCALF0                                 RTC_C_CTL13_CALF0               /*!< RTCCALF Bit 0 */
3214 #define RTCCALF1                                 RTC_C_CTL13_CALF1               /*!< RTCCALF Bit 1 */
3215 #define RTCCALF_0                                RTC_C_CTL13_CALF_0              /*!< No frequency output to RTCCLK pin */
3216 #define RTCCALF_1                                RTC_C_CTL13_CALF_1              /*!< 512 Hz */
3217 #define RTCCALF_2                                RTC_C_CTL13_CALF_2              /*!< 256 Hz */
3218 #define RTCCALF_3                                RTC_C_CTL13_CALF_3              /*!< 1 Hz */
3219 #define RTCCALF__NONE                            RTC_C_CTL13_CALF__NONE          /*!< No frequency output to RTCCLK pin */
3220 #define RTCCALF__512                             RTC_C_CTL13_CALF__512           /*!< 512 Hz */
3221 #define RTCCALF__256                             RTC_C_CTL13_CALF__256           /*!< 256 Hz */
3222 #define RTCCALF__1                               RTC_C_CTL13_CALF__1             /*!< 1 Hz */
3223 /* RTCOCAL[RTCOCAL] Bits */
3224 #define RTCOCAL_OFS                              RTC_C_OCAL_OCAL_OFS             /*!< RTCOCAL Offset */
3225 #define RTCOCAL_M                                RTC_C_OCAL_OCAL_MASK            /*!< Real-time clock offset error calibration */
3226 /* RTCOCAL[RTCOCALS] Bits */
3227 #define RTCOCALS_OFS                             RTC_C_OCAL_OCALS_OFS            /*!< RTCOCALS Offset */
3228 #define RTCOCALS                                 RTC_C_OCAL_OCALS                /*!< Real-time clock offset error calibration sign */
3229 /* RTCTCMP[RTCTCMP] Bits */
3230 #define RTCTCMP_OFS                              RTC_C_TCMP_TCMPX_OFS            /*!< RTCTCMP Offset */
3231 #define RTCTCMP_M                                RTC_C_TCMP_TCMPX_MASK           /*!< Real-time clock temperature compensation */
3232 /* RTCTCMP[RTCTCOK] Bits */
3233 #define RTCTCOK_OFS                              RTC_C_TCMP_TCOK_OFS             /*!< RTCTCOK Offset */
3234 #define RTCTCOK                                  RTC_C_TCMP_TCOK                 /*!< Real-time clock temperature compensation write OK */
3235 /* RTCTCMP[RTCTCRDY] Bits */
3236 #define RTCTCRDY_OFS                             RTC_C_TCMP_TCRDY_OFS            /*!< RTCTCRDY Offset */
3237 #define RTCTCRDY                                 RTC_C_TCMP_TCRDY                /*!< Real-time clock temperature compensation ready */
3238 /* RTCTCMP[RTCTCMPS] Bits */
3239 #define RTCTCMPS_OFS                             RTC_C_TCMP_TCMPS_OFS            /*!< RTCTCMPS Offset */
3240 #define RTCTCMPS                                 RTC_C_TCMP_TCMPS                /*!< Real-time clock temperature compensation sign */
3241 /* RTCPS0CTL[RT0PSIFG] Bits */
3242 #define RT0PSIFG_OFS                             RTC_C_PS0CTL_RT0PSIFG_OFS       /*!< RT0PSIFG Offset */
3243 #define RT0PSIFG                                 RTC_C_PS0CTL_RT0PSIFG           /*!< Prescale timer 0 interrupt flag */
3244 /* RTCPS0CTL[RT0PSIE] Bits */
3245 #define RT0PSIE_OFS                              RTC_C_PS0CTL_RT0PSIE_OFS        /*!< RT0PSIE Offset */
3246 #define RT0PSIE                                  RTC_C_PS0CTL_RT0PSIE            /*!< Prescale timer 0 interrupt enable */
3247 /* RTCPS0CTL[RT0IP] Bits */
3248 #define RT0IP_OFS                                RTC_C_PS0CTL_RT0IP_OFS          /*!< RT0IP Offset */
3249 #define RT0IP_M                                  RTC_C_PS0CTL_RT0IP_MASK         /*!< Prescale timer 0 interrupt interval */
3250 #define RT0IP0                                   RTC_C_PS0CTL_RT0IP0             /*!< RT0IP Bit 0 */
3251 #define RT0IP1                                   RTC_C_PS0CTL_RT0IP1             /*!< RT0IP Bit 1 */
3252 #define RT0IP2                                   RTC_C_PS0CTL_RT0IP2             /*!< RT0IP Bit 2 */
3253 #define RT0IP_0                                  RTC_C_PS0CTL_RT0IP_0            /*!< Divide by 2 */
3254 #define RT0IP_1                                  RTC_C_PS0CTL_RT0IP_1            /*!< Divide by 4 */
3255 #define RT0IP_2                                  RTC_C_PS0CTL_RT0IP_2            /*!< Divide by 8 */
3256 #define RT0IP_3                                  RTC_C_PS0CTL_RT0IP_3            /*!< Divide by 16 */
3257 #define RT0IP_4                                  RTC_C_PS0CTL_RT0IP_4            /*!< Divide by 32 */
3258 #define RT0IP_5                                  RTC_C_PS0CTL_RT0IP_5            /*!< Divide by 64 */
3259 #define RT0IP_6                                  RTC_C_PS0CTL_RT0IP_6            /*!< Divide by 128 */
3260 #define RT0IP_7                                  RTC_C_PS0CTL_RT0IP_7            /*!< Divide by 256 */
3261 #define RT0IP__2                                 RTC_C_PS0CTL_RT0IP__2           /*!< Divide by 2 */
3262 #define RT0IP__4                                 RTC_C_PS0CTL_RT0IP__4           /*!< Divide by 4 */
3263 #define RT0IP__8                                 RTC_C_PS0CTL_RT0IP__8           /*!< Divide by 8 */
3264 #define RT0IP__16                                RTC_C_PS0CTL_RT0IP__16          /*!< Divide by 16 */
3265 #define RT0IP__32                                RTC_C_PS0CTL_RT0IP__32          /*!< Divide by 32 */
3266 #define RT0IP__64                                RTC_C_PS0CTL_RT0IP__64          /*!< Divide by 64 */
3267 #define RT0IP__128                               RTC_C_PS0CTL_RT0IP__128         /*!< Divide by 128 */
3268 #define RT0IP__256                               RTC_C_PS0CTL_RT0IP__256         /*!< Divide by 256 */
3269 /* RTCPS1CTL[RT1PSIFG] Bits */
3270 #define RT1PSIFG_OFS                             RTC_C_PS1CTL_RT1PSIFG_OFS       /*!< RT1PSIFG Offset */
3271 #define RT1PSIFG                                 RTC_C_PS1CTL_RT1PSIFG           /*!< Prescale timer 1 interrupt flag */
3272 /* RTCPS1CTL[RT1PSIE] Bits */
3273 #define RT1PSIE_OFS                              RTC_C_PS1CTL_RT1PSIE_OFS        /*!< RT1PSIE Offset */
3274 #define RT1PSIE                                  RTC_C_PS1CTL_RT1PSIE            /*!< Prescale timer 1 interrupt enable */
3275 /* RTCPS1CTL[RT1IP] Bits */
3276 #define RT1IP_OFS                                RTC_C_PS1CTL_RT1IP_OFS          /*!< RT1IP Offset */
3277 #define RT1IP_M                                  RTC_C_PS1CTL_RT1IP_MASK         /*!< Prescale timer 1 interrupt interval */
3278 #define RT1IP0                                   RTC_C_PS1CTL_RT1IP0             /*!< RT1IP Bit 0 */
3279 #define RT1IP1                                   RTC_C_PS1CTL_RT1IP1             /*!< RT1IP Bit 1 */
3280 #define RT1IP2                                   RTC_C_PS1CTL_RT1IP2             /*!< RT1IP Bit 2 */
3281 #define RT1IP_0                                  RTC_C_PS1CTL_RT1IP_0            /*!< Divide by 2 */
3282 #define RT1IP_1                                  RTC_C_PS1CTL_RT1IP_1            /*!< Divide by 4 */
3283 #define RT1IP_2                                  RTC_C_PS1CTL_RT1IP_2            /*!< Divide by 8 */
3284 #define RT1IP_3                                  RTC_C_PS1CTL_RT1IP_3            /*!< Divide by 16 */
3285 #define RT1IP_4                                  RTC_C_PS1CTL_RT1IP_4            /*!< Divide by 32 */
3286 #define RT1IP_5                                  RTC_C_PS1CTL_RT1IP_5            /*!< Divide by 64 */
3287 #define RT1IP_6                                  RTC_C_PS1CTL_RT1IP_6            /*!< Divide by 128 */
3288 #define RT1IP_7                                  RTC_C_PS1CTL_RT1IP_7            /*!< Divide by 256 */
3289 #define RT1IP__2                                 RTC_C_PS1CTL_RT1IP__2           /*!< Divide by 2 */
3290 #define RT1IP__4                                 RTC_C_PS1CTL_RT1IP__4           /*!< Divide by 4 */
3291 #define RT1IP__8                                 RTC_C_PS1CTL_RT1IP__8           /*!< Divide by 8 */
3292 #define RT1IP__16                                RTC_C_PS1CTL_RT1IP__16          /*!< Divide by 16 */
3293 #define RT1IP__32                                RTC_C_PS1CTL_RT1IP__32          /*!< Divide by 32 */
3294 #define RT1IP__64                                RTC_C_PS1CTL_RT1IP__64          /*!< Divide by 64 */
3295 #define RT1IP__128                               RTC_C_PS1CTL_RT1IP__128         /*!< Divide by 128 */
3296 #define RT1IP__256                               RTC_C_PS1CTL_RT1IP__256         /*!< Divide by 256 */
3297 /* RTCPS[RT0PS] Bits */
3298 #define RT0PS_OFS                                RTC_C_PS_RT0PS_OFS              /*!< RT0PS Offset */
3299 #define RT0PS_M                                  RTC_C_PS_RT0PS_MASK             /*!< Prescale timer 0 counter value */
3300 /* RTCPS[RT1PS] Bits */
3301 #define RT1PS_OFS                                RTC_C_PS_RT1PS_OFS              /*!< RT1PS Offset */
3302 #define RT1PS_M                                  RTC_C_PS_RT1PS_MASK             /*!< Prescale timer 1 counter value */
3303 /* RTCTIM0[SECONDS] Bits */
3304 #define SECONDS_OFS                              RTC_C_TIM0_SEC_OFS              /*!< Seconds Offset */
3305 #define SECONDS_M                                RTC_C_TIM0_SEC_MASK             /*!< Seconds (0 to 59) */
3306 /* RTCTIM0[MINUTES] Bits */
3307 #define MINUTES_OFS                              RTC_C_TIM0_MIN_OFS              /*!< Minutes Offset */
3308 #define MINUTES_M                                RTC_C_TIM0_MIN_MASK             /*!< Minutes (0 to 59) */
3309 /* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */
3310 #define SECONDSLOWDIGIT_OFS                      RTC_C_TIM0_SEC_LD_OFS           /*!< SecondsLowDigit Offset */
3311 #define SECONDSLOWDIGIT_M                        RTC_C_TIM0_SEC_LD_MASK          /*!< Seconds  low digit (0 to 9) */
3312 /* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */
3313 #define SECONDSHIGHDIGIT_OFS                     RTC_C_TIM0_SEC_HD_OFS           /*!< SecondsHighDigit Offset */
3314 #define SECONDSHIGHDIGIT_M                       RTC_C_TIM0_SEC_HD_MASK          /*!< Seconds  high digit (0 to 5) */
3315 /* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */
3316 #define MINUTESLOWDIGIT_OFS                      RTC_C_TIM0_MIN_LD_OFS           /*!< MinutesLowDigit Offset */
3317 #define MINUTESLOWDIGIT_M                        RTC_C_TIM0_MIN_LD_MASK          /*!< Minutes  low digit (0 to 9) */
3318 /* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */
3319 #define MINUTESHIGHDIGIT_OFS                     RTC_C_TIM0_MIN_HD_OFS           /*!< MinutesHighDigit Offset */
3320 #define MINUTESHIGHDIGIT_M                       RTC_C_TIM0_MIN_HD_MASK          /*!< Minutes  high digit (0 to 5) */
3321 /* RTCTIM1[HOURS] Bits */
3322 #define HOURS_OFS                                RTC_C_TIM1_HOUR_OFS             /*!< Hours Offset */
3323 #define HOURS_M                                  RTC_C_TIM1_HOUR_MASK            /*!< Hours (0 to 23) */
3324 /* RTCTIM1[DAYOFWEEK] Bits */
3325 #define DAYOFWEEK_OFS                            RTC_C_TIM1_DOW_OFS              /*!< DayofWeek Offset */
3326 #define DAYOFWEEK_M                              RTC_C_TIM1_DOW_MASK             /*!< Day of week (0 to 6) */
3327 /* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */
3328 #define HOURSLOWDIGIT_OFS                        RTC_C_TIM1_HOUR_LD_OFS          /*!< HoursLowDigit Offset */
3329 #define HOURSLOWDIGIT_M                          RTC_C_TIM1_HOUR_LD_MASK         /*!< Hours  low digit (0 to 9) */
3330 /* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */
3331 #define HOURSHIGHDIGIT_OFS                       RTC_C_TIM1_HOUR_HD_OFS          /*!< HoursHighDigit Offset */
3332 #define HOURSHIGHDIGIT_M                         RTC_C_TIM1_HOUR_HD_MASK         /*!< Hours  high digit (0 to 2) */
3333 /* RTCTIM1_BCD[DAYOFWEEK] Bits */
3334 //#define DAYOFWEEK_OFS                            RTC_C_TIM1_DOW_OFS              /*!< DayofWeek Offset */
3335 //#define DAYOFWEEK_M                              RTC_C_TIM1_DOW_MASK             /*!< Day of week (0 to 6) */
3336 /* RTCDATE[DAY] Bits */
3337 #define DAY_OFS                                  RTC_C_DATE_DAY_OFS              /*!< Day Offset */
3338 #define DAY_M                                    RTC_C_DATE_DAY_MASK             /*!< Day of month (1 to 28, 29, 30, 31) */
3339 /* RTCDATE[MONTH] Bits */
3340 #define MONTH_OFS                                RTC_C_DATE_MON_OFS              /*!< Month Offset */
3341 #define MONTH_M                                  RTC_C_DATE_MON_MASK             /*!< Month (1 to 12) */
3342 /* RTCDATE_BCD[DAYLOWDIGIT] Bits */
3343 #define DAYLOWDIGIT_OFS                          RTC_C_DATE_DAY_LD_OFS           /*!< DayLowDigit Offset */
3344 #define DAYLOWDIGIT_M                            RTC_C_DATE_DAY_LD_MASK          /*!< Day of month  low digit (0 to 9) */
3345 /* RTCDATE_BCD[DAYHIGHDIGIT] Bits */
3346 #define DAYHIGHDIGIT_OFS                         RTC_C_DATE_DAY_HD_OFS           /*!< DayHighDigit Offset */
3347 #define DAYHIGHDIGIT_M                           RTC_C_DATE_DAY_HD_MASK          /*!< Day of month  high digit (0 to 3) */
3348 /* RTCDATE_BCD[MONTHLOWDIGIT] Bits */
3349 #define MONTHLOWDIGIT_OFS                        RTC_C_DATE_MON_LD_OFS           /*!< MonthLowDigit Offset */
3350 #define MONTHLOWDIGIT_M                          RTC_C_DATE_MON_LD_MASK          /*!< Month  low digit (0 to 9) */
3351 /* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */
3352 #define MONTHHIGHDIGIT_OFS                       RTC_C_DATE_MON_HD_OFS           /*!< MonthHighDigit Offset */
3353 #define MONTHHIGHDIGIT                           RTC_C_DATE_MON_HD               /*!< Month  high digit (0 or 1) */
3354 /* RTCYEAR[YEARLOWBYTE] Bits */
3355 #define YEARLOWBYTE_OFS                          RTC_C_YEAR_YEAR_LB_OFS          /*!< YearLowByte Offset */
3356 #define YEARLOWBYTE_M                            RTC_C_YEAR_YEAR_LB_MASK         /*!< Year  low byte. Valid values for Year are 0 to 4095. */
3357 /* RTCYEAR[YEARHIGHBYTE] Bits */
3358 #define YEARHIGHBYTE_OFS                         RTC_C_YEAR_YEAR_HB_OFS          /*!< YearHighByte Offset */
3359 #define YEARHIGHBYTE_M                           RTC_C_YEAR_YEAR_HB_MASK         /*!< Year  high byte. Valid values for Year are 0 to 4095. */
3360 /* RTCYEAR_BCD[YEAR] Bits */
3361 #define YEAR_OFS                                 RTC_C_YEAR_YEAR_OFS             /*!< Year Offset */
3362 #define YEAR_M                                   RTC_C_YEAR_YEAR_MASK            /*!< Year  lowest digit (0 to 9) */
3363 /* RTCYEAR_BCD[DECADE] Bits */
3364 #define DECADE_OFS                               RTC_C_YEAR_DEC_OFS              /*!< Decade Offset */
3365 #define DECADE_M                                 RTC_C_YEAR_DEC_MASK             /*!< Decade (0 to 9) */
3366 /* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */
3367 #define CENTURYLOWDIGIT_OFS                      RTC_C_YEAR_CENT_LD_OFS          /*!< CenturyLowDigit Offset */
3368 #define CENTURYLOWDIGIT_M                        RTC_C_YEAR_CENT_LD_MASK         /*!< Century  low digit (0 to 9) */
3369 /* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */
3370 #define CENTURYHIGHDIGIT_OFS                     RTC_C_YEAR_CENT_HD_OFS          /*!< CenturyHighDigit Offset */
3371 #define CENTURYHIGHDIGIT_M                       RTC_C_YEAR_CENT_HD_MASK         /*!< Century  high digit (0 to 4) */
3372 /* RTCAMINHR[MINUTES] Bits */
3373 //#define MINUTES_OFS                              RTC_C_AMINHR_MIN_OFS            /*!< Minutes Offset */
3374 //#define MINUTES_M                                RTC_C_AMINHR_MIN_MASK           /*!< Minutes (0 to 59) */
3375 /* RTCAMINHR[MINAE] Bits */
3376 #define MINAE_OFS                                RTC_C_AMINHR_MINAE_OFS          /*!< MINAE Offset */
3377 #define MINAE                                    RTC_C_AMINHR_MINAE              /*!< Alarm enable */
3378 /* RTCAMINHR[HOURS] Bits */
3379 //#define HOURS_OFS                                RTC_C_AMINHR_HOUR_OFS           /*!< Hours Offset */
3380 //#define HOURS_M                                  RTC_C_AMINHR_HOUR_MASK          /*!< Hours (0 to 23) */
3381 /* RTCAMINHR[HOURAE] Bits */
3382 #define HOURAE_OFS                               RTC_C_AMINHR_HOURAE_OFS         /*!< HOURAE Offset */
3383 #define HOURAE                                   RTC_C_AMINHR_HOURAE             /*!< Alarm enable */
3384 /* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */
3385 //#define MINUTESLOWDIGIT_OFS                      RTC_C_AMINHR_MIN_LD_OFS         /*!< MinutesLowDigit Offset */
3386 //#define MINUTESLOWDIGIT_M                        RTC_C_AMINHR_MIN_LD_MASK        /*!< Minutes  low digit (0 to 9) */
3387 /* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */
3388 //#define MINUTESHIGHDIGIT_OFS                     RTC_C_AMINHR_MIN_HD_OFS         /*!< MinutesHighDigit Offset */
3389 //#define MINUTESHIGHDIGIT_M                       RTC_C_AMINHR_MIN_HD_MASK        /*!< Minutes  high digit (0 to 5) */
3390 /* RTCAMINHR_BCD[MINAE] Bits */
3391 //#define MINAE_OFS                                RTC_C_AMINHR_MINAE_OFS          /*!< MINAE Offset */
3392 //#define MINAE                                    RTC_C_AMINHR_MINAE              /*!< Alarm enable */
3393 /* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */
3394 //#define HOURSLOWDIGIT_OFS                        RTC_C_AMINHR_HOUR_LD_OFS        /*!< HoursLowDigit Offset */
3395 //#define HOURSLOWDIGIT_M                          RTC_C_AMINHR_HOUR_LD_MASK       /*!< Hours  low digit (0 to 9) */
3396 /* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */
3397 //#define HOURSHIGHDIGIT_OFS                       RTC_C_AMINHR_HOUR_HD_OFS        /*!< HoursHighDigit Offset */
3398 //#define HOURSHIGHDIGIT_M                         RTC_C_AMINHR_HOUR_HD_MASK       /*!< Hours  high digit (0 to 2) */
3399 /* RTCAMINHR_BCD[HOURAE] Bits */
3400 //#define HOURAE_OFS                               RTC_C_AMINHR_HOURAE_OFS         /*!< HOURAE Offset */
3401 //#define HOURAE                                   RTC_C_AMINHR_HOURAE             /*!< Alarm enable */
3402 /* RTCADOWDAY[DAYOFWEEK] Bits */
3403 //#define DAYOFWEEK_OFS                            RTC_C_ADOWDAY_DOW_OFS           /*!< DayofWeek Offset */
3404 //#define DAYOFWEEK_M                              RTC_C_ADOWDAY_DOW_MASK          /*!< Day of week (0 to 6) */
3405 /* RTCADOWDAY[DOWAE] Bits */
3406 #define DOWAE_OFS                                RTC_C_ADOWDAY_DOWAE_OFS         /*!< DOWAE Offset */
3407 #define DOWAE                                    RTC_C_ADOWDAY_DOWAE             /*!< Alarm enable */
3408 /* RTCADOWDAY[DAYOFMONTH] Bits */
3409 #define DAYOFMONTH_OFS                           RTC_C_ADOWDAY_DAY_OFS           /*!< DayofMonth Offset */
3410 #define DAYOFMONTH_M                             RTC_C_ADOWDAY_DAY_MASK          /*!< Day of month (1 to 28, 29, 30, 31) */
3411 /* RTCADOWDAY[DAYAE] Bits */
3412 #define DAYAE_OFS                                RTC_C_ADOWDAY_DAYAE_OFS         /*!< DAYAE Offset */
3413 #define DAYAE                                    RTC_C_ADOWDAY_DAYAE             /*!< Alarm enable */
3414 /* RTCADOWDAY_BCD[DAYOFWEEK] Bits */
3415 //#define DAYOFWEEK_OFS                            RTC_C_ADOWDAY_DOW_OFS           /*!< DayofWeek Offset */
3416 //#define DAYOFWEEK_M                              RTC_C_ADOWDAY_DOW_MASK          /*!< Day of week (0 to 6) */
3417 /* RTCADOWDAY_BCD[DOWAE] Bits */
3418 //#define DOWAE_OFS                                RTC_C_ADOWDAY_DOWAE_OFS         /*!< DOWAE Offset */
3419 //#define DOWAE                                    RTC_C_ADOWDAY_DOWAE             /*!< Alarm enable */
3420 /* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */
3421 //#define DAYLOWDIGIT_OFS                          RTC_C_ADOWDAY_DAY_LD_OFS        /*!< DayLowDigit Offset */
3422 //#define DAYLOWDIGIT_M                            RTC_C_ADOWDAY_DAY_LD_MASK       /*!< Day of month  low digit (0 to 9) */
3423 /* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */
3424 //#define DAYHIGHDIGIT_OFS                         RTC_C_ADOWDAY_DAY_HD_OFS        /*!< DayHighDigit Offset */
3425 //#define DAYHIGHDIGIT_M                           RTC_C_ADOWDAY_DAY_HD_MASK       /*!< Day of month  high digit (0 to 3) */
3426 /* RTCADOWDAY_BCD[DAYAE] Bits */
3427 //#define DAYAE_OFS                                RTC_C_ADOWDAY_DAYAE_OFS         /*!< DAYAE Offset */
3428 //#define DAYAE                                    RTC_C_ADOWDAY_DAYAE             /*!< Alarm enable */
3429 /* Pre-defined bitfield values */
3430 #define RTCKEY                                             RTC_C_KEY              /*!< RTC_C Key Value for RTC_C write access */
3431 #define RTCKEY_H                                           RTC_C_KEY_H            /*!< RTC_C Key Value for RTC_C write access */
3432 #define RTCKEY_VAL                                         RTC_C_KEY_VAL          /*!< RTC_C Key Value for RTC_C write access */
3433 
3434 
3435 /******************************************************************************
3436 * TIMER_A Bits (legacy section)
3437 ******************************************************************************/
3438 /* TA0CTL[TAIFG] Bits */
3439 #define TAIFG_OFS                                TIMER_A_CTL_IFG_OFS             /*!< TAIFG Offset */
3440 #define TAIFG                                    TIMER_A_CTL_IFG                 /*!< TimerA interrupt flag */
3441 /* TA0CTL[TAIE] Bits */
3442 #define TAIE_OFS                                 TIMER_A_CTL_IE_OFS              /*!< TAIE Offset */
3443 #define TAIE                                     TIMER_A_CTL_IE                  /*!< TimerA interrupt enable */
3444 /* TA0CTL[TACLR] Bits */
3445 #define TACLR_OFS                                TIMER_A_CTL_CLR_OFS             /*!< TACLR Offset */
3446 #define TACLR                                    TIMER_A_CTL_CLR                 /*!< TimerA clear */
3447 /* TA0CTL[MC] Bits */
3448 #define MC_OFS                                   TIMER_A_CTL_MC_OFS              /*!< MC Offset */
3449 #define MC_M                                     TIMER_A_CTL_MC_MASK             /*!< Mode control */
3450 #define MC0                                      TIMER_A_CTL_MC0                 /*!< MC Bit 0 */
3451 #define MC1                                      TIMER_A_CTL_MC1                 /*!< MC Bit 1 */
3452 #define MC_0                                     TIMER_A_CTL_MC_0                /*!< Stop mode: Timer is halted */
3453 #define MC_1                                     TIMER_A_CTL_MC_1                /*!< Up mode: Timer counts up to TAxCCR0 */
3454 #define MC_2                                     TIMER_A_CTL_MC_2                /*!< Continuous mode: Timer counts up to 0FFFFh */
3455 #define MC_3                                     TIMER_A_CTL_MC_3                /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
3456 #define MC__STOP                                 TIMER_A_CTL_MC__STOP            /*!< Stop mode: Timer is halted */
3457 #define MC__UP                                   TIMER_A_CTL_MC__UP              /*!< Up mode: Timer counts up to TAxCCR0 */
3458 #define MC__CONTINUOUS                           TIMER_A_CTL_MC__CONTINUOUS      /*!< Continuous mode: Timer counts up to 0FFFFh */
3459 #define MC__UPDOWN                               TIMER_A_CTL_MC__UPDOWN          /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
3460 /* TA0CTL[ID] Bits */
3461 #define ID_OFS                                   TIMER_A_CTL_ID_OFS              /*!< ID Offset */
3462 #define ID_M                                     TIMER_A_CTL_ID_MASK             /*!< Input divider */
3463 #define ID0                                      TIMER_A_CTL_ID0                 /*!< ID Bit 0 */
3464 #define ID1                                      TIMER_A_CTL_ID1                 /*!< ID Bit 1 */
3465 #define ID_0                                     TIMER_A_CTL_ID_0                /*!< /1 */
3466 #define ID_1                                     TIMER_A_CTL_ID_1                /*!< /2 */
3467 #define ID_2                                     TIMER_A_CTL_ID_2                /*!< /4 */
3468 #define ID_3                                     TIMER_A_CTL_ID_3                /*!< /8 */
3469 #define ID__1                                    TIMER_A_CTL_ID__1               /*!< /1 */
3470 #define ID__2                                    TIMER_A_CTL_ID__2               /*!< /2 */
3471 #define ID__4                                    TIMER_A_CTL_ID__4               /*!< /4 */
3472 #define ID__8                                    TIMER_A_CTL_ID__8               /*!< /8 */
3473 /* TA0CTL[TASSEL] Bits */
3474 #define TASSEL_OFS                               TIMER_A_CTL_SSEL_OFS            /*!< TASSEL Offset */
3475 #define TASSEL_M                                 TIMER_A_CTL_SSEL_MASK           /*!< TimerA clock source select */
3476 #define TASSEL0                                  TIMER_A_CTL_SSEL0               /*!< TASSEL Bit 0 */
3477 #define TASSEL1                                  TIMER_A_CTL_SSEL1               /*!< TASSEL Bit 1 */
3478 #define TASSEL_0                                 TIMER_A_CTL_TASSEL_0            /*!< TAxCLK */
3479 #define TASSEL_1                                 TIMER_A_CTL_TASSEL_1            /*!< ACLK */
3480 #define TASSEL_2                                 TIMER_A_CTL_TASSEL_2            /*!< SMCLK */
3481 #define TASSEL_3                                 TIMER_A_CTL_TASSEL_3            /*!< INCLK */
3482 #define TASSEL__TACLK                            TIMER_A_CTL_SSEL__TACLK         /*!< TAxCLK */
3483 #define TASSEL__ACLK                             TIMER_A_CTL_SSEL__ACLK          /*!< ACLK */
3484 #define TASSEL__SMCLK                            TIMER_A_CTL_SSEL__SMCLK         /*!< SMCLK */
3485 #define TASSEL__INCLK                            TIMER_A_CTL_SSEL__INCLK         /*!< INCLK */
3486 /* TA0CCTLn[CCIFG] Bits */
3487 #define CCIFG_OFS                                TIMER_A_CCTLN_CCIFG_OFS         /*!< CCIFG Offset */
3488 #define CCIFG                                    TIMER_A_CCTLN_CCIFG             /*!< Capture/compare interrupt flag */
3489 /* TA0CCTLn[COV] Bits */
3490 #define COV_OFS                                  TIMER_A_CCTLN_COV_OFS           /*!< COV Offset */
3491 #define COV                                      TIMER_A_CCTLN_COV               /*!< Capture overflow */
3492 /* TA0CCTLn[OUT] Bits */
3493 #define OUT_OFS                                  TIMER_A_CCTLN_OUT_OFS           /*!< OUT Offset */
3494 //#define OUT                                      TIMER_A_CCTLN_OUT               /*!< Output */
3495 /* TA0CCTLn[CCI] Bits */
3496 #define CCI_OFS                                  TIMER_A_CCTLN_CCI_OFS           /*!< CCI Offset */
3497 #define CCI                                      TIMER_A_CCTLN_CCI               /*!< Capture/compare input */
3498 /* TA0CCTLn[CCIE] Bits */
3499 #define CCIE_OFS                                 TIMER_A_CCTLN_CCIE_OFS          /*!< CCIE Offset */
3500 #define CCIE                                     TIMER_A_CCTLN_CCIE              /*!< Capture/compare interrupt enable */
3501 /* TA0CCTLn[OUTMOD] Bits */
3502 #define OUTMOD_OFS                               TIMER_A_CCTLN_OUTMOD_OFS        /*!< OUTMOD Offset */
3503 #define OUTMOD_M                                 TIMER_A_CCTLN_OUTMOD_MASK       /*!< Output mode */
3504 #define OUTMOD0                                  TIMER_A_CCTLN_OUTMOD0           /*!< OUTMOD Bit 0 */
3505 #define OUTMOD1                                  TIMER_A_CCTLN_OUTMOD1           /*!< OUTMOD Bit 1 */
3506 #define OUTMOD2                                  TIMER_A_CCTLN_OUTMOD2           /*!< OUTMOD Bit 2 */
3507 #define OUTMOD_0                                 TIMER_A_CCTLN_OUTMOD_0          /*!< OUT bit value */
3508 #define OUTMOD_1                                 TIMER_A_CCTLN_OUTMOD_1          /*!< Set */
3509 #define OUTMOD_2                                 TIMER_A_CCTLN_OUTMOD_2          /*!< Toggle/reset */
3510 #define OUTMOD_3                                 TIMER_A_CCTLN_OUTMOD_3          /*!< Set/reset */
3511 #define OUTMOD_4                                 TIMER_A_CCTLN_OUTMOD_4          /*!< Toggle */
3512 #define OUTMOD_5                                 TIMER_A_CCTLN_OUTMOD_5          /*!< Reset */
3513 #define OUTMOD_6                                 TIMER_A_CCTLN_OUTMOD_6          /*!< Toggle/set */
3514 #define OUTMOD_7                                 TIMER_A_CCTLN_OUTMOD_7          /*!< Reset/set */
3515 /* TA0CCTLn[CAP] Bits */
3516 #define CAP_OFS                                  TIMER_A_CCTLN_CAP_OFS           /*!< CAP Offset */
3517 #define CAP                                      TIMER_A_CCTLN_CAP               /*!< Capture mode */
3518 /* TA0CCTLn[SCCI] Bits */
3519 #define SCCI_OFS                                 TIMER_A_CCTLN_SCCI_OFS          /*!< SCCI Offset */
3520 #define SCCI                                     TIMER_A_CCTLN_SCCI              /*!< Synchronized capture/compare input */
3521 /* TA0CCTLn[SCS] Bits */
3522 #define SCS_OFS                                  TIMER_A_CCTLN_SCS_OFS           /*!< SCS Offset */
3523 #define SCS                                      TIMER_A_CCTLN_SCS               /*!< Synchronize capture source */
3524 /* TA0CCTLn[CCIS] Bits */
3525 #define CCIS_OFS                                 TIMER_A_CCTLN_CCIS_OFS          /*!< CCIS Offset */
3526 #define CCIS_M                                   TIMER_A_CCTLN_CCIS_MASK         /*!< Capture/compare input select */
3527 #define CCIS0                                    TIMER_A_CCTLN_CCIS0             /*!< CCIS Bit 0 */
3528 #define CCIS1                                    TIMER_A_CCTLN_CCIS1             /*!< CCIS Bit 1 */
3529 #define CCIS_0                                   TIMER_A_CCTLN_CCIS_0            /*!< CCIxA */
3530 #define CCIS_1                                   TIMER_A_CCTLN_CCIS_1            /*!< CCIxB */
3531 #define CCIS_2                                   TIMER_A_CCTLN_CCIS_2            /*!< GND */
3532 #define CCIS_3                                   TIMER_A_CCTLN_CCIS_3            /*!< VCC */
3533 #define CCIS__CCIA                               TIMER_A_CCTLN_CCIS__CCIA        /*!< CCIxA */
3534 #define CCIS__CCIB                               TIMER_A_CCTLN_CCIS__CCIB        /*!< CCIxB */
3535 #define CCIS__GND                                TIMER_A_CCTLN_CCIS__GND         /*!< GND */
3536 #define CCIS__VCC                                TIMER_A_CCTLN_CCIS__VCC         /*!< VCC */
3537 /* TA0CCTLn[CM] Bits */
3538 #define CM_OFS                                   TIMER_A_CCTLN_CM_OFS            /*!< CM Offset */
3539 #define CM_M                                     TIMER_A_CCTLN_CM_MASK           /*!< Capture mode */
3540 #define CM0                                      TIMER_A_CCTLN_CM0               /*!< CM Bit 0 */
3541 #define CM1                                      TIMER_A_CCTLN_CM1               /*!< CM Bit 1 */
3542 #define CM_0                                     TIMER_A_CCTLN_CM_0              /*!< No capture */
3543 #define CM_1                                     TIMER_A_CCTLN_CM_1              /*!< Capture on rising edge */
3544 #define CM_2                                     TIMER_A_CCTLN_CM_2              /*!< Capture on falling edge */
3545 #define CM_3                                     TIMER_A_CCTLN_CM_3              /*!< Capture on both rising and falling edges */
3546 #define CM__NONE                                 TIMER_A_CCTLN_CM__NONE          /*!< No capture */
3547 #define CM__RISING                               TIMER_A_CCTLN_CM__RISING        /*!< Capture on rising edge */
3548 #define CM__FALLING                              TIMER_A_CCTLN_CM__FALLING       /*!< Capture on falling edge */
3549 #define CM__BOTH                                 TIMER_A_CCTLN_CM__BOTH          /*!< Capture on both rising and falling edges */
3550 /* TA0EX0[TAIDEX] Bits */
3551 #define TAIDEX_OFS                               TIMER_A_EX0_IDEX_OFS            /*!< TAIDEX Offset */
3552 #define TAIDEX_M                                 TIMER_A_EX0_IDEX_MASK           /*!< Input divider expansion */
3553 #define TAIDEX0                                  TIMER_A_EX0_IDEX0               /*!< TAIDEX Bit 0 */
3554 #define TAIDEX1                                  TIMER_A_EX0_IDEX1               /*!< TAIDEX Bit 1 */
3555 #define TAIDEX2                                  TIMER_A_EX0_IDEX2               /*!< TAIDEX Bit 2 */
3556 #define TAIDEX_0                                 TIMER_A_EX0_TAIDEX_0            /*!< Divide by 1 */
3557 #define TAIDEX_1                                 TIMER_A_EX0_TAIDEX_1            /*!< Divide by 2 */
3558 #define TAIDEX_2                                 TIMER_A_EX0_TAIDEX_2            /*!< Divide by 3 */
3559 #define TAIDEX_3                                 TIMER_A_EX0_TAIDEX_3            /*!< Divide by 4 */
3560 #define TAIDEX_4                                 TIMER_A_EX0_TAIDEX_4            /*!< Divide by 5 */
3561 #define TAIDEX_5                                 TIMER_A_EX0_TAIDEX_5            /*!< Divide by 6 */
3562 #define TAIDEX_6                                 TIMER_A_EX0_TAIDEX_6            /*!< Divide by 7 */
3563 #define TAIDEX_7                                 TIMER_A_EX0_TAIDEX_7            /*!< Divide by 8 */
3564 #define TAIDEX__1                                TIMER_A_EX0_IDEX__1             /*!< Divide by 1 */
3565 #define TAIDEX__2                                TIMER_A_EX0_IDEX__2             /*!< Divide by 2 */
3566 #define TAIDEX__3                                TIMER_A_EX0_IDEX__3             /*!< Divide by 3 */
3567 #define TAIDEX__4                                TIMER_A_EX0_IDEX__4             /*!< Divide by 4 */
3568 #define TAIDEX__5                                TIMER_A_EX0_IDEX__5             /*!< Divide by 5 */
3569 #define TAIDEX__6                                TIMER_A_EX0_IDEX__6             /*!< Divide by 6 */
3570 #define TAIDEX__7                                TIMER_A_EX0_IDEX__7             /*!< Divide by 7 */
3571 #define TAIDEX__8                                TIMER_A_EX0_IDEX__8             /*!< Divide by 8 */
3572 
3573 /******************************************************************************
3574 * WDT_A Bits (legacy section)
3575 ******************************************************************************/
3576 /* WDTCTL[WDTIS] Bits */
3577 #define WDTIS_OFS                                WDT_A_CTL_IS_OFS                /*!< WDTIS Offset */
3578 #define WDTIS_M                                  WDT_A_CTL_IS_MASK               /*!< Watchdog timer interval select */
3579 #define WDTIS0                                   WDT_A_CTL_IS0                   /*!< WDTIS Bit 0 */
3580 #define WDTIS1                                   WDT_A_CTL_IS1                   /*!< WDTIS Bit 1 */
3581 #define WDTIS2                                   WDT_A_CTL_IS2                   /*!< WDTIS Bit 2 */
3582 #define WDTIS_0                                  WDT_A_CTL_IS_0                  /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
3583 #define WDTIS_1                                  WDT_A_CTL_IS_1                  /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
3584 #define WDTIS_2                                  WDT_A_CTL_IS_2                  /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
3585 #define WDTIS_3                                  WDT_A_CTL_IS_3                  /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
3586 #define WDTIS_4                                  WDT_A_CTL_IS_4                  /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
3587 #define WDTIS_5                                  WDT_A_CTL_IS_5                  /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
3588 #define WDTIS_6                                  WDT_A_CTL_IS_6                  /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
3589 #define WDTIS_7                                  WDT_A_CTL_IS_7                  /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
3590 /* WDTCTL[WDTCNTCL] Bits */
3591 #define WDTCNTCL_OFS                             WDT_A_CTL_CNTCL_OFS             /*!< WDTCNTCL Offset */
3592 #define WDTCNTCL                                 WDT_A_CTL_CNTCL                 /*!< Watchdog timer counter clear */
3593 /* WDTCTL[WDTTMSEL] Bits */
3594 #define WDTTMSEL_OFS                             WDT_A_CTL_TMSEL_OFS             /*!< WDTTMSEL Offset */
3595 #define WDTTMSEL                                 WDT_A_CTL_TMSEL                 /*!< Watchdog timer mode select */
3596 /* WDTCTL[WDTSSEL] Bits */
3597 #define WDTSSEL_OFS                              WDT_A_CTL_SSEL_OFS              /*!< WDTSSEL Offset */
3598 #define WDTSSEL_M                                WDT_A_CTL_SSEL_MASK             /*!< Watchdog timer clock source select */
3599 #define WDTSSEL0                                 WDT_A_CTL_SSEL0                 /*!< WDTSSEL Bit 0 */
3600 #define WDTSSEL1                                 WDT_A_CTL_SSEL1                 /*!< WDTSSEL Bit 1 */
3601 #define WDTSSEL_0                                WDT_A_CTL_SSEL_0                /*!< SMCLK */
3602 #define WDTSSEL_1                                WDT_A_CTL_SSEL_1                /*!< ACLK */
3603 #define WDTSSEL_2                                WDT_A_CTL_SSEL_2                /*!< VLOCLK */
3604 #define WDTSSEL_3                                WDT_A_CTL_SSEL_3                /*!< BCLK */
3605 #define WDTSSEL__SMCLK                           WDT_A_CTL_SSEL__SMCLK           /*!< SMCLK */
3606 #define WDTSSEL__ACLK                            WDT_A_CTL_SSEL__ACLK            /*!< ACLK */
3607 #define WDTSSEL__VLOCLK                          WDT_A_CTL_SSEL__VLOCLK          /*!< VLOCLK */
3608 #define WDTSSEL__BCLK                            WDT_A_CTL_SSEL__BCLK            /*!< BCLK */
3609 /* WDTCTL[WDTHOLD] Bits */
3610 #define WDTHOLD_OFS                              WDT_A_CTL_HOLD_OFS              /*!< WDTHOLD Offset */
3611 #define WDTHOLD                                  WDT_A_CTL_HOLD                  /*!< Watchdog timer hold */
3612 /* WDTCTL[WDTPW] Bits */
3613 #define WDTPW_OFS                                WDT_A_CTL_PW_OFS                /*!< WDTPW Offset */
3614 #define WDTPW_M                                  WDT_A_CTL_PW_MASK               /*!< Watchdog timer password */
3615 /* Pre-defined bitfield values */
3616 #define WDTPW                                          WDT_A_CTL_PW              /*!< WDT Key Value for WDT write access */
3617 
3618 
3619 #ifdef __cplusplus
3620 }
3621 #endif
3622 
3623 #endif /* __MSP432P401R_CLASSIC_H__ */
3624