1/*
2 * Copyright 2021-22, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nxp/nxp_rt11xx_cm7.dtsi>
10#include "mimxrt1170_evk.dtsi"
11
12/ {
13	model = "NXP MIMXRT1170-EVK board";
14	compatible = "nxp,mimxrt1176";
15
16	aliases {
17		mipi-dsi = &mipi_dsi;
18		watchdog0 = &wdog1;
19	};
20
21	chosen {
22		zephyr,sram = &sdram0;
23		zephyr,dtcm = &dtcm;
24		zephyr,itcm = &itcm;
25		zephyr,console = &lpuart1;
26		zephyr,shell-uart = &lpuart1;
27		zephyr,canbus = &flexcan3;
28		zephyr,flash-controller = &is25wp128;
29		zephyr,flash = &is25wp128;
30		zephyr,code-partition = &slot0_partition;
31		zephyr,cpu1-region = &ocram;
32		zephyr,ipc = &mailbox_a;
33	};
34
35	sdram0: memory@80000000 {
36		/* Winbond W9825G6KH-5I */
37		device_type = "memory";
38		reg = <0x80000000 DT_SIZE_M(64)>;
39	};
40
41	/*
42	 * This node describes the GPIO pins of the MIPI FPC interface,
43	 * J48 on the EVK. This interface is standard to several
44	 * NXP EVKs, and is used with several MIPI displays
45	 * (available as zephyr shields)
46	 */
47	nxp_mipi_connector: mipi-connector {
48		compatible = "gpio-nexus";
49		#gpio-cells = <2>;
50		gpio-map-mask = <0xffffffff 0xffffffc0>;
51		gpio-map-pass-thru = <0 0x3f>;
52		gpio-map =	<0  0 &gpio9 29 0>,	/* Pin 1, LEDK */
53				<21 0 &gpio9 1  0>,	/* Pin 21, RESET */
54				<22 0 &gpio9 4  0>,	/* Pin 22, LPTE */
55				<26 0 &gpio6 4  0>,	/* Pin 26, CTP_I2C SDA */
56				<27 0 &gpio6 5  0>,	/* Pin 27, CTP_I2C SCL */
57				<28 0 &gpio9 0  0>,	/* Pin 28, CTP_RST */
58				<29 0 &gpio2 31 0>,	/* Pin 29, CTP_INT */
59				<32 0 &gpio11 16 0>,	/* Pin 32, PWR_EN */
60				<34 0 &gpio9 29 0>;	/* Pin 34, BL_PWM */
61	};
62};
63
64zephyr_lcdif: &lcdif {};
65
66zephyr_mipi_dsi: &mipi_dsi {
67	dphy-ref-frequency = <24000000>;
68};
69
70&lpuart1 {
71	status = "okay";
72	current-speed = <115200>;
73};
74
75&flexcan3 {
76	status = "okay";
77	bus-speed = <125000>;
78	bus-speed-data = <1000000>;
79	can-transceiver {
80		max-bitrate = <5000000>;
81	};
82};
83
84&lpspi1 {
85	dmas = <&edma0 0 36>, <&edma0 1 37>;
86	dma-names = "rx", "tx";
87	status = "okay";
88};
89
90nxp_mipi_i2c: &lpi2c5 {
91	pinctrl-0 = <&pinmux_lpi2c5>;
92	pinctrl-names = "default";
93	#address-cells = <1>;
94	#size-cells = <0>;
95};
96
97&lpadc0 {
98	status = "okay";
99};
100
101&usdhc1 {
102	status = "okay";
103	detect-dat3;
104	pwr-gpios = <&gpio10 2 GPIO_ACTIVE_LOW>;
105	sdmmc {
106		compatible = "zephyr,sdmmc-disk";
107		status = "okay";
108	};
109};
110
111&edma0 {
112	status = "okay";
113};
114
115/* GPT and Systick are enabled. If power management is enabled, the GPT
116 * timer will be used instead of systick, as allows the core clock to
117 * be gated.
118 */
119&gpt_hw_timer {
120	status = "okay";
121};
122
123&systick {
124	status = "okay";
125};
126
127&wdog1 {
128	status = "okay";
129};
130
131&enet {
132	status = "okay";
133	int-gpios = <&gpio9 11 GPIO_ACTIVE_HIGH>;
134	reset-gpios = <&gpio12 12 GPIO_ACTIVE_HIGH>;
135	ptp {
136		status = "okay";
137	};
138};
139
140&sai1 {
141	status = "okay";
142};
143
144zephyr_udc0: &usb1 {
145	status = "okay";
146};
147
148&mailbox_a {
149	status = "okay";
150};
151