1/* 2 * Copyright (c) 2018 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <skeleton.dtsi> 8#include <zephyr/dt-bindings/gpio/gpio.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 cpu@0 { 18 clock-frequency = <0>; 19 compatible = "sifive,e51", "riscv"; 20 device_type = "cpu"; 21 reg = < 0x0 >; 22 riscv,isa = "rv64imac_zicsr_zifencei"; 23 hlic0: interrupt-controller { 24 compatible = "riscv,cpu-intc"; 25 #address-cells = <0>; 26 #interrupt-cells = <1>; 27 interrupt-controller; 28 }; 29 }; 30 31 cpu@1 { 32 clock-frequency = <0>; 33 compatible = "sifive,u54", "riscv"; 34 device_type = "cpu"; 35 reg = < 0x1 >; 36 riscv,isa = "rv64gc"; 37 hlic1: interrupt-controller { 38 compatible = "riscv,cpu-intc"; 39 #address-cells = <0>; 40 #interrupt-cells = <1>; 41 interrupt-controller; 42 }; 43 }; 44 45 cpu@2 { 46 clock-frequency = <0>; 47 compatible = "sifive,u54", "riscv"; 48 device_type = "cpu"; 49 reg = < 0x2 >; 50 riscv,isa = "rv64gc"; 51 hlic2: interrupt-controller { 52 compatible = "riscv,cpu-intc"; 53 #address-cells = <0>; 54 #interrupt-cells = <1>; 55 interrupt-controller; 56 }; 57 }; 58 59 cpu@3 { 60 clock-frequency = <0>; 61 compatible = "sifive,u54", "riscv"; 62 device_type = "cpu"; 63 reg = < 0x3 >; 64 riscv,isa = "rv64gc"; 65 hlic3: interrupt-controller { 66 compatible = "riscv,cpu-intc"; 67 #address-cells = <0>; 68 #interrupt-cells = <1>; 69 interrupt-controller; 70 }; 71 }; 72 73 cpu@4 { 74 clock-frequency = <0>; 75 compatible = "sifive,u54", "riscv"; 76 device_type = "cpu"; 77 reg = < 0x4 >; 78 riscv,isa = "rv64gc"; 79 hlic4: interrupt-controller { 80 compatible = "riscv,cpu-intc"; 81 #address-cells = <0>; 82 #interrupt-cells = <1>; 83 interrupt-controller; 84 }; 85 }; 86 }; 87 88 soc { 89 #address-cells = <1>; 90 #size-cells = <1>; 91 compatible = "simple-bus"; 92 ranges; 93 94 sram0: memory@8000000 { 95 compatible = "mmio-sram"; 96 reg = <0x8000000 0x80000>; 97 }; 98 99 sram1: memory@80000000 { 100 compatible = "mmio-sram"; 101 reg = <0x80000000 0x800000>; 102 }; 103 104 clint: clint@2000000 { 105 compatible = "sifive,clint0"; 106 interrupts-extended = <&hlic0 3 &hlic0 7 107 &hlic1 3 &hlic1 7 108 &hlic2 3 &hlic2 7 109 &hlic3 3 &hlic3 7 110 &hlic4 3 &hlic4 7>; 111 interrupt-names = "soft0", "timer0", "soft1", "timer1", 112 "soft2", "timer2", "soft3", "timer3", 113 "soft4", "timer4"; 114 reg = <0x2000000 0x10000>; 115 }; 116 117 plic: interrupt-controller@c000000 { 118 compatible = "sifive,plic-1.0.0"; 119 #interrupt-cells = <2>; 120 #address-cells = <1>; 121 interrupt-controller; 122 interrupts-extended = <&hlic0 11 123 &hlic1 11 &hlic1 9 124 &hlic2 11 &hlic2 9 125 &hlic3 11 &hlic3 9 126 &hlic4 11 &hlic4 9>; 127 reg = <0x0c000000 0x04000000>; 128 riscv,max-priority = <7>; 129 riscv,ndev = <186>; 130 }; 131 132 mbox: mailbox@37020000 { 133 compatible = "microchip,mpfs-mailbox"; 134 reg = <0x37020000 0x58>, <0x2000318C 0x40>, 135 <0x37020800 0x100>; 136 interrupt-parent = <&plic>; 137 interrupts = <96 1>; 138 #mbox-cells = <1>; 139 status = "disabled"; 140 }; 141 142 uart0: uart@20000000 { 143 compatible = "ns16550"; 144 reg = <0x20000000 0x1000>; 145 clock-frequency = <150000000>; 146 current-speed = <115200>; 147 interrupt-parent = <&plic>; 148 interrupts = <90 1>; 149 reg-shift = <2>; 150 status = "disabled"; 151 }; 152 153 uart1: uart@20100000 { 154 compatible = "ns16550"; 155 reg = <0x20100000 0x1000>; 156 clock-frequency = <150000000>; 157 current-speed = <115200>; 158 interrupt-parent = <&plic>; 159 interrupts = <91 1>; 160 reg-shift = <2>; 161 status = "disabled"; 162 }; 163 164 uart2: uart@20102000 { 165 compatible = "ns16550"; 166 reg = <0x20102000 0x1000>; 167 clock-frequency = <150000000>; 168 current-speed = <115200>; 169 interrupt-parent = <&plic>; 170 interrupts = <92 1>; 171 reg-shift = <2>; 172 status = "disabled"; 173 }; 174 175 uart3: uart@20104000 { 176 compatible = "ns16550"; 177 reg = <0x20104000 0x1000>; 178 clock-frequency = <150000000>; 179 current-speed = <115200>; 180 interrupt-parent = <&plic>; 181 interrupts = <93 1>; 182 reg-shift = <2>; 183 status = "disabled"; 184 }; 185 186 uart4: uart@20106000 { 187 compatible = "ns16550"; 188 reg = <0x20106000 0x1000>; 189 clock-frequency = <150000000>; 190 current-speed = <115200>; 191 interrupt-parent = <&plic>; 192 interrupts = <94 1>; 193 reg-shift = <2>; 194 status = "disabled"; 195 }; 196 197 qspi0: spi@21000000 { 198 compatible = "microchip,mpfs-qspi"; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 reg = <0x21000000 0x1000>; 202 interrupt-parent = <&plic>; 203 interrupts = <85 1>; 204 status = "disabled"; 205 clock-frequency = <150000000>; 206 }; 207 208 spi1: spi@20109000 { 209 compatible = "microchip,mpfs-spi"; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 reg = <0x20109000 0x1000>; 213 interrupt-parent = <&plic>; 214 interrupts = <55 1>; 215 status = "disabled"; 216 clock-frequency = <150000000>; 217 }; 218 219 syscontroller_qspi: spi@37020100 { 220 compatible = "microchip,mpfs-qspi"; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 reg = <0x37020100 0x1000>; 224 interrupt-parent = <&plic>; 225 interrupts = <110 1>; 226 status = "disabled"; 227 clock-frequency = <150000000>; 228 }; 229 230 gpio0: gpio@20120000 { 231 compatible = "microchip,mpfs-gpio"; 232 reg = <0x20120000 0x1000>; 233 interrupt-parent = <&plic>; 234 interrupts = <51 1>; 235 interrupt-controller; 236 #interrupt-cells = <1>; 237 gpio-controller; 238 #gpio-cells = <2>; 239 ngpios = <32>; 240 status = "disabled"; 241 }; 242 243 gpio1: gpio@20121000 { 244 compatible = "microchip,mpfs-gpio"; 245 reg = <0x20121000 0x1000>; 246 interrupt-parent = <&plic>; 247 interrupts = <52 1>; 248 interrupt-controller; 249 #interrupt-cells = <1>; 250 gpio-controller; 251 #gpio-cells = <2>; 252 ngpios = <32>; 253 status = "disabled"; 254 }; 255 256 gpio2: gpio@20122000 { 257 compatible = "microchip,mpfs-gpio"; 258 reg = <0x20122000 0x1000>; 259 interrupt-parent = <&plic>; 260 interrupts = <53 1>; 261 interrupt-controller; 262 #interrupt-cells = <1>; 263 gpio-controller; 264 #gpio-cells = <2>; 265 ngpios = <32>; 266 status = "disabled"; 267 }; 268 269 i2c0: i2c@2010a000 { 270 compatible = "microchip,mpfs-i2c"; 271 reg = <0x2010a000 0x1000>; 272 interrupt-parent = <&plic>; 273 interrupts = <58 1>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 clock-frequency = <100000>; 277 status = "disabled"; 278 }; 279 280 i2c1: i2c@2010b000 { 281 compatible = "microchip,mpfs-i2c"; 282 reg = <0x2010b000 0x1000>; 283 interrupt-parent = <&plic>; 284 interrupts = <61 1>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 clock-frequency = <100000>; 288 status = "disabled"; 289 }; 290 }; 291}; 292