1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file mfclk.cypersonality 6* \version 3.0 7* 8* \brief 9* CLK_MF personality description file. 10* This supports CAT1A, CAT1B and CAT1D devices. 11* 12******************************************************************************** 13* \copyright 14* Copyright (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or 15* an affiliate of Cypress Semiconductor Corporation. 16* SPDX-License-Identifier: Apache-2.0 17* 18* Licensed under the Apache License, Version 2.0 (the "License"); 19* you may not use this file except in compliance with the License. 20* You may obtain a copy of the License at 21* 22* http://www.apache.org/licenses/LICENSE-2.0 23* 24* Unless required by applicable law or agreed to in writing, software 25* distributed under the License is distributed on an "AS IS" BASIS, 26* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27* See the License for the specific language governing permissions and 28* limitations under the License. 29*****************************************************************************--> 30 31<Personality id="mfclk" name="CLK_MF" version="3.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 32 <Dependencies> 33 <IpBlock name="mxs40srss,mxs40ssrss,mxs22srss" /> 34 <Resource name="srss\.clock\.mfclk" /> 35 </Dependencies> 36 <ExposedMembers> 37 <ExposedMember key="frequency" paramId="frequency" /> 38 <ExposedMember key="accuracy" paramId="accuracy" /> 39 <ExposedMember key="error" paramId="error" /> 40 <ExposedMember key="sourceClock" paramId="sourceClock" /> 41 </ExposedMembers> 42 <Parameters> 43 <!-- PDL documentation --> 44 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk.html" linkText="Open SysClk Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 45 46 <ParamChoice id="sourceClock" name="Source Clock" group="General" default="`${"mxs22srss" eq getIpBlockName() ? "wco" : "mfo"}`" visible="true" editable="true" desc="Source clock path"> 47 <Entry name="MFO" value="mfo" visible="`${("mxs40srss" eq getIpBlockName()) || ("mxs40ssrss" eq getIpBlockName())}`"/> 48 <Entry name="ILO" value="ilo" visible="`${"mxs40ssrss" eq getIpBlockName() ? "true" : "false"}`"/> 49 <Entry name="WCO" value="wco" visible="`${("mxs40ssrss" eq getIpBlockName()) || ("mxs22srss" eq getIpBlockName())}`"/> 50 <Entry name="PILO" value="pilo" visible="`${"mxs40ssrss" eq getIpBlockName() ? "true" : "false"}`"/> 51 <Entry name="ECO Prescaler" value="ecoprescaler" visible="`${"mxs22srss" eq getIpBlockName() ? "true" : "false"}`"/> 52 <Entry name="IHO" value="iho" visible="`${"mxs22srss" eq getIpBlockName() ? "true" : "false"}`"/> 53 </ParamChoice> 54 <ParamString id="sourceClockApiName" name="Source Clock API Name" group="Internal" default="`${sourceClock eq mfo ? "MFO" : 55 sourceClock eq ilo ? "ILO" : 56 sourceClock eq wco ? "WCO" : 57 sourceClock eq pilo ? "PILO" : 58 sourceClock eq ecoprescaler ? "ECO_PRESCALER" : "IHO"}`" visible="false" editable="false" desc="" /> 59 60 <ParamString id="sourceClockRsc" name="Source Clock" group="Internal" default="`${"srss[0].clock[0]." . sourceClock . "[0]"}`" visible="false" editable="false" desc="" /> 61 <ParamBool id="error" name="Clock Error" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" /> 62 <ParamRange id="sourceFreq" name="Source Frequency" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "frequency") : 0}`" min="0" max="`${"mxs22srss" eq getIpBlockName() ? "25000000" : "2000000"}`" resolution="1" visible="false" editable="false" desc="" /> 63 <ParamString id="accuracy" name="accuracy" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "accuracy") : 0}`" visible="false" editable="false" desc="" /> 64 <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFreq,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" /> 65 <ParamRange id="divider" name="Divider" group="General" default="1" min="`${"mxs22srss" eq getIpBlockName() && sourceClock eq iho ? "2" : "1"}`" max="256" resolution="1" visible="true" editable="true" desc="The source clock frequency divider" /> 66 <ParamRange id="frequency" name="Frequency" group="Internal" default="`${sourceFreq / divider}`" min="0" max="`${"mxs22srss" eq getIpBlockName() ? "25000000" : "2000000"}`" resolution="1" visible="false" editable="false" desc="" /> 67 <ParamString id="frequencyInfo" name="Frequency" group="General" default="`${formatFrequency(frequency,accuracy)}`" visible="true" editable="false" desc="The resulting CLK_MF output clock frequency" /> 68 <ParamSignal port="clk_mf[0]" name="Clock Output" group="General" visible="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" desc="A medium-frequency clock output driving specific peripherals" canBeEmpty="true" /> 69 </Parameters> 70 <DRCs> 71 <DRC type="ERROR" text="Source clock for CLK_MF is not enabled" condition="`${error}`" > 72 <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" /> 73 </DRC> 74 </DRCs> 75 <ConfigFirmware> 76 <ConfigInclude value="cy_sysclk.h" include="true" /> 77 <ConfigDefine name="CY_CFG_SYSCLK_CLKMF_ENABLED" value="1" public="false" include="true" /> 78 <ConfigDefine name="CY_CFG_SYSCLK_CLKMF_FREQ" value="`${frequency}`UL" public="false" include="true" /> 79 <ConfigDefine name="CY_CFG_SYSCLK_CLKMF_DIVIDER" value="`${divider}`UL" public="false" include="true" /> 80 <ConfigDefine name="CY_CFG_SYSCLK_CLKMF_SOURCE" value="CY_SYSCLK_CLKMF_IN_`${sourceClockApiName}`" public="true" include="`${"mxs40ssrss" eq getIpBlockName() ? "true" : "false"}`" /> 81 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkMfInit()" body=" Cy_SysClk_ClkMfDisable();
 Cy_SysClk_ClkMfSetDivider(CY_CFG_SYSCLK_CLKMF_DIVIDER);
 Cy_SysClk_ClkMfEnable();" public="false" include="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" /> 82 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkMfInit()" body=" Cy_SysClk_ClkMfDisable();
 Cy_SysClk_ClkMfSetSource(CY_SYSCLK_CLKMF_IN_`${sourceClockApiName}`);
 Cy_SysClk_ClkMfSetDivider(CY_CFG_SYSCLK_CLKMF_DIVIDER);
 Cy_SysClk_ClkMfEnable();" public="false" include="`${("mxs40ssrss" eq getIpBlockName()) || ("mxs22srss" eq getIpBlockName())}`" /> 83 </ConfigFirmware> 84</Personality> 85
