1 /**************************************************************************//** 2 * @file mem_<Device>.h 3 * @brief CMSIS Cortex-A Memory base and size definitions (used in scatter file) 4 * @version V1.00 5 * @date 10. January 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #ifndef MEM_<Device>_H /* ToDo: replace '<Device>' with your device name */ 26 #define MEM_<Device>_H 27 28 /*---------------------------------------------------------------------------- 29 User Stack & Heap size definition 30 *----------------------------------------------------------------------------*/ 31 /* 32 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 33 */ 34 35 /*--------------------- ROM Configuration ------------------------------------ 36 // 37 // <h> ROM Configuration 38 // <o0> ROM Base Address <0x0-0xFFFFFFFF:8> 39 // <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> 40 // </h> 41 *----------------------------------------------------------------------------*/ 42 #define __ROM_BASE 0x80000000 43 #define __ROM_SIZE 0x00200000 44 45 /*--------------------- RAM Configuration ----------------------------------- 46 // <h> RAM Configuration 47 // <o0> RAM Base Address <0x0-0xFFFFFFFF:8> 48 // <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8> 49 // <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 50 // <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 51 // <h> Stack / Heap Configuration 52 // <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 53 // <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 54 // <h> Exceptional Modes 55 // <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 56 // <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 57 // <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 58 // <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 59 // <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 60 // </h> 61 // </h> 62 // </h> 63 *----------------------------------------------------------------------------*/ 64 #define __RAM_BASE 0x80200000 65 #define __RAM_SIZE 0x00200000 66 67 #define __RW_DATA_SIZE 0x00100000 68 #define __ZI_DATA_SIZE 0x000F0000 69 70 #define __STACK_SIZE 0x00001000 71 #define __HEAP_SIZE 0x00008000 72 73 #define __UND_STACK_SIZE 0x00000100 74 #define __ABT_STACK_SIZE 0x00000100 75 #define __SVC_STACK_SIZE 0x00000100 76 #define __IRQ_STACK_SIZE 0x00000100 77 #define __FIQ_STACK_SIZE 0x00000100 78 79 /*----------------------------------------------------------------------------*/ 80 81 /*--------------------- TTB Configuration ------------------------------------ 82 // 83 // <h> TTB Configuration 84 // <o0> TTB Base Address <0x0-0xFFFFFFFF:8> 85 // <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> 86 // </h> 87 *----------------------------------------------------------------------------*/ 88 #define __TTB_BASE 0x80500000 89 #define __TTB_SIZE 0x00004000 90 91 #endif /* MEM_<Device>_H */ 92
