1 /**************************************************************************//** 2 * @file mem_ARMCA9.h 3 * @brief Memory base and size definitions (used in scatter file) 4 * @version V1.1.0 5 * @date 15. May 2019 6 * 7 * @note 8 * 9 ******************************************************************************/ 10 /* 11 * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 12 * 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the License); you may 16 * not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 */ 27 28 #ifndef __MEM_ARMCA9_H 29 #define __MEM_ARMCA9_H 30 31 /*---------------------------------------------------------------------------- 32 User Stack & Heap size definition 33 *----------------------------------------------------------------------------*/ 34 /* 35 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 36 */ 37 38 /*--------------------- ROM Configuration ------------------------------------ 39 // 40 // <h> ROM Configuration 41 // <i> For compatibility with MMU config the sections must be multiple of 1MB 42 // <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000> 43 // <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 44 // </h> 45 *----------------------------------------------------------------------------*/ 46 #define __ROM_BASE 0x80000000 47 #define __ROM_SIZE 0x00200000 48 49 /*--------------------- RAM Configuration ----------------------------------- 50 // <h> RAM Configuration 51 // <i> For compatibility with MMU config the sections must be multiple of 1MB 52 // <o0> RAM Base Address <0x0-0xFFFFFFFF:0x100000> 53 // <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 54 // <h> Data Sections 55 // <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 56 // <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 57 // </h> 58 // <h> Stack / Heap Configuration 59 // <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 60 // <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 61 // <h> Exceptional Modes 62 // <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 63 // <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 64 // <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 65 // <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 66 // <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 67 // </h> 68 // </h> 69 // </h> 70 *----------------------------------------------------------------------------*/ 71 #define __RAM_BASE 0x80200000 72 #define __RAM_SIZE 0x00300000 73 74 #define __RW_DATA_SIZE 0x00100000 75 #define __ZI_DATA_SIZE 0x000F0000 76 77 #define __STACK_SIZE 0x00002000 78 #define __HEAP_SIZE 0x00100000 79 80 #define __UND_STACK_SIZE 0x00000100 81 #define __ABT_STACK_SIZE 0x00000100 82 #define __SVC_STACK_SIZE 0x00000100 83 #define __IRQ_STACK_SIZE 0x00000100 84 #define __FIQ_STACK_SIZE 0x00000100 85 86 /*----------------------------------------------------------------------------*/ 87 88 /*--------------------- TTB Configuration ------------------------------------ 89 // 90 // <h> TTB Configuration 91 // <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned 92 // <i> The TLB L2 entries are placed after the L1 in the MMU config 93 // <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000> 94 // <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> 95 // </h> 96 *----------------------------------------------------------------------------*/ 97 #define __TTB_BASE 0x80500000 98 #define __TTB_SIZE 0x00005000 99 100 #endif /* __MEM_ARMCA9_H */ 101
