1 /** 2 * 3 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 #ifndef __MEC1723NLJ_SPECS_H__ 27 #define __MEC1723NLJ_SPECS_H__ 28 29 /* MEC1723N-LJ */ 30 #define MEC5_MEC1723_NLJ 31 #define MEC5_PKG176 32 33 #define MEC5_FAM2_ID 0x22u 34 #define MEC172X_FAM_ID 0x00220000u 35 #define MEC1723NLJ_DEV_ID 0x00223700u 36 37 #define MEC5_CODE_SRAM_BASE 0xc0000 38 #define MEC5_CODE_SRAM_SIZE 0x58000 39 #define MEC5_DATA_SRAM_BASE 0x118000 40 #define MEC5_DATA_SRAM_SIZE 0x10000 41 #define MEC5_PUF_DATA_SRAM_BASE 0x127800 42 #define MEC5_PUF_DATA_SRAM_SIZE 0x800 43 44 #define MEC5_ECIA_NUM_GIRQS 19 45 #define MEC5_NVIC_NUM_REGS 7 46 #define MEC5_MAX_NVIC_EXT_INPUTS 181 47 #define MEC5_NVIC_NUM_IP_REGS 46 48 #define MEC5_ECIA_FIRST_GIRQ_NOS 8 49 #define MEC5_ECIA_LAST_GIRQ_NOS 26 50 51 /* ARM Cortex-Mx NVIC hardware numeric priority value 0 is highest priority */ 52 #define MEC5_NVIC_PRI_LO_VAL 7 53 #define MEC5_NVIC_PRI_HI_VAL 0 54 55 #define MEC5_ECIA_DIRECT_BITMAP 0x00bfe000u 56 #define MEC5_ECIA_ALL_BITMAP 0x07ffff00u 57 58 #define MEC_MAX_PCR_SCR_REGS 5 59 60 #define MEC5_ADC_CHANNELS 16 61 62 #define MEC5_BASIC_TIMER_INSTANCES 6 63 #define MEC5_BASIC_TIMER_16_MSK 0x0fu 64 #define MEC5_BASIC_TIMER_32_MSK 0x30u 65 66 #define MEC5_HIB_TIMER_INSTANCES 2 67 #define MEC5_CTMR_TIMER_INSTANCES 4 68 #define MEC5_CCT_INSTANCES 1 69 70 #define MEC5_DMAC_NUM_CHANNELS 16 71 72 #define MEC5_ESPI_HW_VER_14 14 73 #define MEC5_ESPI_IOBAR_MSK_LO 0x57ffffu 74 #define MEC5_ESPI_IOBAR_MSK_HI 0 75 #define MEC5_ESPI_LDN_IOB_MSK_LO 0x001787ffu 76 #define MEC5_ESPI_LDN_IOB_MSK_HI 0x00008003u 77 #define MEC5_ESPI_MEMBAR_MSK_LO 0x3ffu 78 #define MEC5_ESPI_MEMBAR_MSK_HI 0 79 #define MEC5_ESPI_LDN_MEMB_MSK_LO 0x0007007du 80 #define MEC5_ESPI_LDN_MEMB_MSK_HI 0x00008000u 81 #define MEC5_ESPI_PC_SIRQ_BITMAP 0x7ffffu 82 #define MEC5_ESPI_NUM_CTVW 11 83 #define MEC5_ESPI_NUM_TCVW 11 84 85 /* 32 GPIO pins per port */ 86 #define MEC5_GPIO_NUM_PORTS 6 87 #define MEC5_GPIO_PORT0_BITMAP 0x7fffffffu 88 #define MEC5_GPIO_PORT1_BITMAP 0x3fffffffu 89 #define MEC5_GPIO_PORT2_BITMAP 0x3ffffff7u 90 #define MEC5_GPIO_PORT3_BITMAP 0x3f67ffffu 91 #define MEC5_GPIO_PORT4_BITMAP 0x7fffffffu 92 #define MEC5_GPIO_PORT5_BITMAP 0x0000387fu 93 94 /* some pins may not implement Control2 register */ 95 #define MEC5_GPIO_PORT0_C2_BITMAP 0x7fffffffu 96 #define MEC5_GPIO_PORT1_C2_BITMAP 0x3fffffffu 97 #define MEC5_GPIO_PORT2_C2_BITMAP 0x3ffffff7u 98 #define MEC5_GPIO_PORT3_C2_BITMAP 0x3f67ffffu 99 #define MEC5_GPIO_PORT4_C2_BITMAP 0x7fffffffu 100 #define MEC5_GPIO_PORT5_C2_BITMAP 0x0000387fu 101 102 #define MEC5_I2C_SMB_INSTANCES 5 103 #define MEC5_I2C_SMB_BAUD_CLOCK 16000000 104 #define MEC5_I2C_SMB_PORT_MAP 0xffffu 105 106 #define MEC5_QSPI_INSTANCES 1 107 #define MEC5_QSPI_NUM_DESCRS 16 108 /* Individual TX and RX FIFO byte lengths */ 109 #define MEC5_QSPI_FIFO_LEN 8 110 /* TX and RX each implement this number of Local DMA channels */ 111 #define MEC5_QSPI_LDMA_CHANNELS 3 112 113 #define MEC5_GSPI_CTRL_VERSION 1 114 #define MEC5_GSPI_INSTANCES 2 115 116 #define MEC5_UART_INSTANCES 2 117 118 #define MEC5_ACPI_EC_INSTANCES 5 119 120 #define MEC5_EMI_INSTANCES 3 121 122 #define MEC5_MAILBOX_INSTANCES 1 123 124 #define MEC5_PS2_INSTANCES 1 125 126 #define MEC5_KSCAN_INSTANCES 1 127 128 #define MEC5_PWM_INSTANCES 12 129 130 #define MEC5_TACH_INSTANCES 4 131 132 #define MEC5_BBLED_INSTANCES 4 133 134 /* Length in bytes of VBAT memory region */ 135 #define MEC_VBAT_MEM_SIZE 128u 136 #define MEC5_EEPROM_WRITE_PAGE_SIZE 32u 137 138 #define MEC5_VCI_PINS 5 139 #define MEC5_VCI_PINS_MASK 0x3fu 140 #define MEC5_VCI_GPIO_PINS_MASK 0x3eu 141 142 #define MEC5_EEPROM_SIZE_IN_BYTES 2048u 143 144 /* BC-Link */ 145 #define MEC5_BCL_INSTANCES 1 146 147 #endif /* __MEC1723NLJ_SPECS_H__ */ 148
