1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_ESPI_CORE_H 7 #define _MEC_ESPI_CORE_H 8 9 #include <stdbool.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 13 /* Interfaces to any C modules */ 14 #ifdef __cplusplus 15 extern "C" 16 { 17 #endif 18 19 /* forward declarations */ 20 struct mec_espi_io_regs; 21 struct mec_espi_mem_regs; 22 struct mec_espi_vw_regs; 23 24 /* ---- eSPI configuration ---- */ 25 #define MEC_ESPI_CFG_PERIPH_CHAN_SUP_POS 0 26 #define MEC_ESPI_CFG_VW_CHAN_SUP_POS 1 27 #define MEC_ESPI_CFG_OOB_CHAN_SUP_POS 2 28 #define MEC_ESPI_CFG_FLASH_CHAN_SUP_POS 3 29 30 #define MEC_ESPI_CFG_IO_MODE_SUPP_POS 4 31 #define MEC_ESPI_CFG_IO_MODE_SUPP_MSK0 0x3u 32 #define MEC_ESPI_CFG_IO_MODE_SUPP_MSK \ 33 ((MEC_ESPI_CFG_IO_MODE_SUPP_MSK0) << (MEC_ESPI_CFG_IO_MODE_SUPP_POS)) 34 #define MEC_ESPI_CFG_ALERT_OD_SUPP_POS 6 35 #define MEC_ESPI_CFG_PLTRST_EXT_POS 7 36 37 #define MEC_ESPI_CFG_MAX_SUPP_FREQ_POS 8 38 #define MEC_ESPI_CFG_MAX_SUPP_FREQ_MSK0 0x7u 39 #define MEC_ESPI_CFG_MAX_SUPP_FREQ_MSK \ 40 ((MEC_ESPI_CFG_MAX_SUPP_FREQ_MSK0) << (MEC_ESPI_CFG_MAX_SUPP_FREQ_POS)) 41 42 #define MEC_ESPI_CFG_PC_MAX_PLD_SZ_POS 12 43 #define MEC_ESPI_CFG_PC_MAX_PLD_SZ_MSK0 0x7u 44 #define MEC_ESPI_CFG_PC_MAX_PLD_SZ_MSK \ 45 ((MEC_ESPI_CFG_PC_MAX_PLD_SZ_MSK0) << (MEC_ESPI_CFG_PC_MAX_PLD_SZ_POS)) 46 47 #define MEC_ESPI_CFG_OOB_MAX_PLD_SZ_POS 15 48 #define MEC_ESPI_CFG_OOB_MAX_PLD_SZ_MSK0 0x7u 49 #define MEC_ESPI_CFG_OOB_MAX_PLD_SZ_MSK \ 50 ((MEC_ESPI_CFG_OOB_MAX_PLD_SZ_MSK0) << (MEC_ESPI_CFG_OOB_MAX_PLD_SZ_POS)) 51 52 #define MEC_ESPI_CFG_VW_CNT_MAX_POS 18 53 #define MEC_ESPI_CFG_VW_CNT_MAX_MSK0 0x3fu 54 #define MEC_ESPI_CFG_VW_CNT_MAX_MSK \ 55 ((MEC_ESPI_CFG_VW_CNT_MAX_MSK0) << (MEC_ESPI_CFG_VW_CNT_MAX_POS)) 56 57 #define MEC_ESPI_CFG_FLASH_MAX_PLD_SZ_POS 24 58 #define MEC_ESPI_CFG_FLASH_MAX_PLD_SZ_MSK0 0x7u 59 #define MEC_ESPI_CFG_FLASH_MAX_PLD_SZ_MSK \ 60 ((MEC_ESPI_CFG_FLASH_MAX_PLD_SZ_MSK0) << (MEC_ESPI_CFG_FLASH_MAX_PLD_SZ_POS)) 61 #define MEC_ESPI_CFG_FLASH_SHARED_CAF_POS 27 62 #define MEC_ESPI_CFG_FLASH_SHARED_TAF_POS 28 63 #define MEC_ESPI_CFG_FLASH_SHARED_MODE_POS 27 64 #define MEC_ESPI_CFG_FLASH_SHARED_MODE_MSK0 0x3u 65 #define MEC_ESPI_CFG_FLASH_SHARED_MODE_MSK \ 66 ((MEC_ESPI_CFG_FLASH_SHARED_MODE_MSK0) << (MEC_ESPI_CFG_FLASH_SHARED_MODE_POS)) 67 #define MEC_ESPI_CAP_FLASH_SHARED_MAX_RD_REQ_SZ_POS 29 68 #define MEC_ESPI_CAP_FLASH_SHARED_MAX_RD_REQ_SZ_MSK0 0x7u 69 #define MEC_ESPI_CAP_FLASH_SHARED_MAX_RD_REQ_SZ_MSK \ 70 ((MEC_ESPI_CAP_FLASH_SHARED_MAX_RD_REQ_SZ_MSK0) \ 71 << (MEC_ESPI_CAP_FLASH_SHARED_MAX_RD_REQ_SZ_POS)) 72 73 #define MEC_ESPI_RESET_CHG_POS 0 74 #define MEC_ESPI_RESET_STATE_POS 1 75 76 #define MEC_ESPI_RESET_CHG 0x01 77 #define MEC_ESPI_RESET_HI 0x02 78 79 /* Each channel has an API returning a bitmap containing current state 80 * of the channel enable set by the eSPI Host and if the channel enable 81 * changed. 82 */ 83 #define MEC_ESPI_CHAN_ENABLED_POS 0 84 #define MEC_ESPI_CHAN_EN_CHG_POS 1 85 86 #define MEC_ESPI_CHAN_ENABLED 0x01 87 #define MEC_ESPI_CHAN_EN_CHG 0x02 88 89 #define MEC_ESPI_SIRQ_SLOT_DIS 0xffu 90 91 enum mec_espi_max_freq { 92 MEC_ESPI_MAX_SUPP_FREQ_20M = 0, 93 MEC_ESPI_MAX_SUPP_FREQ_25M, 94 MEC_ESPI_MAX_SUPP_FREQ_33M, 95 MEC_ESPI_MAX_SUPP_FREQ_50M, 96 MEC_ESPI_MAX_SUPP_FREQ_66M, 97 }; 98 99 enum mec_espi_io_mode { 100 MEC_ESPI_IO_MODE_1 = 0, 101 MEC_ESPI_IO_MODE_1_2, 102 MEC_ESPI_IO_MODE_1_4, 103 MEC_ESPI_IO_MODE_1_2_4, 104 }; 105 106 enum mec_espi_alert_io_mode { 107 MEC_ESPI_ALERT_IOM_NO_OD = 0, 108 MEC_ESPI_ALERT_IOM_OD, 109 }; 110 111 /* NOTE: OOB maximum payload size has same bit field encoding but actual size 112 * is 9 bytes larger to accomodate MCTP prefix. 113 */ 114 enum mec_espi_chan_max_pld_sz { 115 MEC_ESPI_CHAN_MAX_PLD_64B = 1, 116 }; 117 118 enum mec_espi_fc_sharing { 119 MEC_ESPI_FC_SHARING_MAF = 0, 120 MEC_ESPI_FC_SHARING_MAF_ALT, 121 MEC_ESPI_FC_SHARING_TAF, 122 MEC_ESPI_FC_SHARING_MAF_TAF, 123 }; 124 125 enum mec_espi_vw_max_count { 126 MEC_ESPI_VW_MAX_COUNT_MIN = 7, 127 MEC_ESPI_VW_MAX_COUNT_MAX = 0x3f, 128 }; 129 130 enum mec_espi_cap_id { 131 MEC_ESPI_CAP_ID_GLOBAL = 0, 132 MEC_ESPI_CAP_ID_PC, 133 MEC_ESPI_CAP_ID_VW, 134 MEC_ESPI_CAP_ID_OOB, 135 MEC_ESPI_CAP_ID_FC, 136 MEC_ESPI_CAP_ID_MAX, 137 }; 138 139 /* Set/Get Global capability position and values */ 140 #define MEC_ESPI_CAP_GL_SUPP_PC_POS 0 141 #define MEC_ESPI_CAP_GL_SUPP_VW_POS 1 142 #define MEC_ESPI_CAP_GL_SUPP_OOB_POS 2 143 #define MEC_ESPI_CAP_GL_SUPP_FLASH_POS 3 144 #define MEC_ESPI_CAP_GL_MAX_FREQ_POS 4 145 #define MEC_ESPI_CAP_GL_MAX_FREQ_MSK0 0x7u 146 #define MEC_ESPI_CAP_GL_MAX_FREQ_MSK \ 147 ((MEC_ESPI_CAP_GL_MAX_FREQ_MSK0) << (MEC_ESPI_CAP_GL_MAX_FREQ_POS)) 148 #define MEC_ESPI_CAP_GL_IOM_POS 8 149 #define MEC_ESPI_CAP_GL_IOM_MSK0 0x3u 150 #define MEC_ESPI_CAP_GL_IOM_MSK ((MEC_ESPI_CAP_GL_IOM_MSK0) << (MEC_ESPI_CAP_GL_IOM_POS)) 151 #define MEC_ESPI_CAP_GL_SUPP_ALERT_OD_POS 12 152 #define MEC_ESPI_CAP_GL_PLTRST_EXT_POS 13 153 154 /* Set/Get Peripheral Channel capability position and values */ 155 #define MEC_ESPI_CAP_PC_MAX_PLD_SIZE_POS 0 156 #define MEC_ESPI_CAP_PC_MAX_PLD_SIZE_MSK0 0x7u 157 #define MEC_ESPI_CAP_PC_MAX_PLD_SIZE_MSK \ 158 ((MEC_ESPI_CAP_PC_MAX_PLD_SIZE_MSK0) << (MEC_ESPI_CAP_PC_MAX_PLD_SIZE_POS)) 159 160 #define MEC_ESPI_CAP_PC_MAX_PLD_SZ_64 (1u << (MEC_ESPI_CAP_PC_MAX_PLD_SIZE_POS)) 161 #define MEC_ESPI_CAP_PC_MAX_PLD_SZ_128 (2u << (MEC_ESPI_CAP_PC_MAX_PLD_SIZE_POS)) 162 #define MEC_ESPI_CAP_PC_MAX_PLD_SZ_256 (3u << (MEC_ESPI_CAP_PC_MAX_PLD_SIZE_POS)) 163 #define MEC_ESPI_CAP_PC_MAX_PLD_SZ_DFLT MEC_ESPI_CAP_PC_MAX_PLD_SZ_64 164 165 /* Set/Get Virtual Wire Channel capability position and values */ 166 #define MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_POS 0 167 #define MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_MSK0 0x3fu 168 #define MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_MSK ((MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_MSK0) << (MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_POS)) 169 170 #define MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_8 0x7u 171 #define MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_64 0x3fu 172 #define MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_DFLT MEC_ESPI_CAP_VW_MAX_VW_GRP_CNT_64 173 174 /* Set/Get OOB Channel capability position and values */ 175 #define MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_POS 0 176 #define MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_MSK0 0x7u 177 #define MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_MSK \ 178 ((MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_MSK0) << (MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_POS)) 179 180 #define MEC_ESPI_CAP_OOB_MAX_PLD_SZ_73 (1u << (MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_POS)) 181 #define MEC_ESPI_CAP_OOB_MAX_PLD_SZ_137 (2u << (MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_POS)) 182 #define MEC_ESPI_CAP_OOB_MAX_PLD_SZ_265 (3u << (MEC_ESPI_CAP_OOB_MAX_PLD_SIZE_POS)) 183 #define MEC_ESPI_CAP_OOB_MAX_PLD_SZ_DFLT MEC_ESPI_CAP_OOB_MAX_PLD_SZ_73 184 185 /* Set/Get Flash Channel capability position and values */ 186 #define MEC_ESPI_CAP_FC_MAX_PLD_SIZE_POS 0 187 #define MEC_ESPI_CAP_FC_MAX_PLD_SIZE_MSK0 0x7u 188 #define MEC_ESPI_CAP_FC_MAX_PLD_SIZE_MSK \ 189 ((MEC_ESPI_CAP_FC_MAX_PLD_SIZE_MSK0) << (MEC_ESPI_CAP_FC_MAX_PLD_SIZE_POS)) 190 #define MEC_ESPI_CAP_FC_SHDM_POS 4 191 #define MEC_ESPI_CAP_FC_SHDM_MSK0 0x3u 192 #define MEC_ESPI_CAP_FC_SHDM_MSK ((MEC_ESPI_CAP_FC_SHDM_MSK0) << (MEC_ESPI_CAP_FC_SHDM_POS)) 193 #define MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_POS 8 194 #define MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_MSK0 0x7u 195 #define MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_MSK \ 196 ((MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_MSK0) << (MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_POS)) 197 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_POS 16 198 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_MSK0 0xffu 199 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_MSK \ 200 ((MEC_ESPI_CAP_FC_TAF_ERBSZ_MSK0) << (MEC_ESPI_CAP_FC_TAF_ERBSZ_POS)) 201 202 #define MEC_ESPI_CAP_FC_MAX_PLD_SZ_64 (1u << (MEC_ESPI_CAP_FC_MAX_PLD_SIZE_POS)) 203 #define MEC_ESPI_CAP_FC_MAX_PLD_SZ_128 (2u << (MEC_ESPI_CAP_FC_MAX_PLD_SIZE_POS)) 204 #define MEC_ESPI_CAP_FC_MAX_PLD_SZ_256 (3u << (MEC_ESPI_CAP_FC_MAX_PLD_SIZE_POS)) 205 #define MEC_ESPI_CAP_FC_MAX_PLD_SZ_DFLT MEC_ESPI_CAP_FC_MAX_PLD_SZ_64 206 207 #define MEC_ESPI_CAP_FC_SHDM_CAF (0u << (MEC_ESPI_CAP_FC_SHDM_POS)) 208 #define MEC_ESPI_CAP_FC_SHDM_CAF_ALT (1u << (MEC_ESPI_CAP_FC_SHDM_POS)) 209 #define MEC_ESPI_CAP_FC_SHDM_TAF (2u << (MEC_ESPI_CAP_FC_SHDM_POS)) 210 #define MEC_ESPI_CAP_FC_SHDM_CAF_TAF (3u << (MEC_ESPI_CAP_FC_SHDM_POS)) 211 212 #define MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_64 (1u << (MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_POS)) 213 #define MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_DFLT MEC_ESPI_CAP_FC_TAF_MAX_RDREQ_SIZE_64 214 215 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_1K (1u << (MEC_ESPI_CAP_FC_TAF_ERBSZ_POS)) 216 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_2K (2u << (MEC_ESPI_CAP_FC_TAF_ERBSZ_POS)) 217 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_4K (4u << (MEC_ESPI_CAP_FC_TAF_ERBSZ_POS)) 218 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_8K (8u << (MEC_ESPI_CAP_FC_TAF_ERBSZ_POS)) 219 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_16K (0x10u << (MEC_ESPI_CAP_FC_TAF_ERBSZ_POS)) 220 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_32K (0x20u << (MEC_ESPI_CAP_FC_TAF_ERBSZ_POS)) 221 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_64K (0x40u << (MEC_ESPI_CAP_FC_TAF_ERBSZ_POS)) 222 #define MEC_ESPI_CAP_FC_TAF_ERBSZ_128K (0x80u << (MEC_ESPI_CAP_FC_TAF_ERBSZ_POS)) 223 224 enum mec_espi_global_cap { 225 MEC_ESPI_CAP_MAX_FREQ = 0, 226 MEC_ESPI_CAP_IO_MODE, 227 MEC_ESPI_CAP_ALERT_OD, 228 MEC_ESPI_CAP_PERIPH_CHAN, 229 MEC_ESPI_CAP_PC_MAX_PLD_SIZE, 230 MEC_ESPI_CAP_VWIRE_CHAN, 231 MEC_ESPI_CAP_MAX_VW_COUNT, 232 MEC_ESPI_CAP_OOB_CHAN, 233 MEC_ESPI_CAP_OOB_MAX_PLD_SIZE, 234 MEC_ESPI_CAP_FLASH_CHAN, 235 MEC_ESPI_CAP_FC_MAX_PLD_SIZE, 236 MEC_ESPI_CAP_FC_SHARING, 237 MEC_ESPI_CAP_FC_MAX_RD_REQ_SIZE, 238 MEC_ESPI_CAP_MAX, 239 }; 240 241 #define MEC_ESPI_CFG_FLAG_PC_GIRQ_EN_POS 0 242 #define MEC_ESPI_CFG_FLAG_BM1_GIRQ_EN_POS 1 243 #define MEC_ESPI_CFG_FLAG_BM2_GIRQ_EN_POS 2 244 #define MEC_ESPI_CFG_FLAG_LTR_GIRQ_EN_POS 3 245 #define MEC_ESPI_CFG_FLAG_OOB_UP_GIRQ_EN_POS 4 246 #define MEC_ESPI_CFG_FLAG_OOB_DN_GIRQ_EN_POS 5 247 #define MEC_ESPI_CFG_FLAG_FC_GIRQ_EN_POS 6 248 #define MEC_ESPI_CFG_FLAG_ERST_GIRQ_EN_POS 7 249 #define MEC_ESPI_CFG_FLAG_VW_CT_GIRQ_EN_POS 8 250 #define MEC_ESPI_CFG_FLAG_VW_CHEN_GIRQ_EN_POS 9 251 252 struct mec_espi_config { 253 struct mec_espi_io_regs *iobase; 254 struct mec_espi_mem_regs *mbase; 255 struct mec_espi_vw_regs *vwbase; 256 uint32_t capabilities; 257 uint32_t cfg_flags; 258 }; 259 260 /* Configure eSPI controller hardware capabilities read by the Host eSPI controller 261 * soon after the Host de-asserts ESPI_RESET#. 262 * NOTE eSPI is only fully reset by a full chip reset or power cycle. 263 * The external ESPI_RESET# signal when asserted does hold portions of the logic 264 * in reset state. Please refer to the Microchip eSPI block document. 265 * This routine should be called while the Host is holding ESPI_RESET# asserted active. 266 */ 267 int mec_hal_espi_init(struct mec_espi_config *cfg); 268 269 int mec_hal_espi_capability_set(struct mec_espi_io_regs *iobase, 270 enum mec_espi_global_cap cap, uint32_t cfg); 271 272 int mec_hal_espi_capability_get(struct mec_espi_io_regs *iobase, 273 enum mec_espi_global_cap cap, uint32_t *cfg); 274 275 int mec_hal_espi_cap_set(struct mec_espi_io_regs *iobase, enum mec_espi_cap_id id, uint32_t cfg); 276 uint32_t mec_hal_espi_cap_get(struct mec_espi_io_regs *iobase, enum mec_espi_cap_id id); 277 278 void mec_hal_espi_reset_change_clr(struct mec_espi_io_regs *iobase); 279 void mec_hal_espi_reset_change_intr_en(struct mec_espi_io_regs *iobase, uint8_t enable); 280 void mec_hal_espi_reset_girq_ctrl(uint8_t enable); 281 void mec_hal_espi_reset_girq_status_clr(void); 282 uint32_t mec_hal_espi_reset_girq_status(void); 283 uint32_t mec_hal_espi_reset_girq_result(void); 284 285 /* Return bits indicating ESPI_RESET# has changed and its current state */ 286 uint32_t mec_hal_espi_reset_state(struct mec_espi_io_regs *iobase); 287 288 /* Enable eSPI controller after all static configuration has been performed. 289 * MEC eSPI activate must be set before the Host de-asserts ESPI_RESET#. 290 */ 291 void mec_hal_espi_activate(struct mec_espi_io_regs *iobase, uint8_t enable); 292 int mec_hal_espi_is_activated(struct mec_espi_io_regs *iobase); 293 294 #ifdef __cplusplus 295 } 296 #endif 297 298 #endif /* #ifndef _MEC_ESPI_CORE_H */ 299
