1/* 2 * Copyright (c) 2021 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h> 15#include <freq.h> 16#include <mem.h> 17 18#include "mec172x/mec172x-vw-routing.dtsi" 19 20/ { 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-m4"; 28 reg = <0>; 29 }; 30 }; 31 32 flash0: flash@c0000 { 33 reg = <0x000C0000 0x58000>; 34 }; 35 36 sram0: memory@118000 { 37 compatible = "mmio-sram"; 38 reg = <0x00118000 0x10000>; 39 }; 40 41 soc { 42 ecs: ecs@4000fc00 { 43 reg = <0x4000fc00 0x200>; 44 }; 45 pcr: pcr@40080100 { 46 compatible = "microchip,xec-pcr"; 47 reg = <0x40080100 0x100 0x4000a400 0x100>; 48 reg-names = "pcrr", "vbatr"; 49 interrupts = <174 0>; 50 core-clock-div = <1>; 51 /* MEC172x allows sources to be different */ 52 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>; 53 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>; 54 clk32kmon-period-min = <1435>; 55 clk32kmon-period-max = <1495>; 56 clk32kmon-duty-cycle-var-max = <132>; 57 clk32kmon-valid-min = <4>; 58 xtal-enable-delay-ms = <300>; 59 pll-lock-timeout-ms = <30>; 60 /* pin configured only if one of the sources is set to PIN */ 61 pinctrl-0 = <&clk_32khz_in_gpio165>; 62 pinctrl-names = "default"; 63 #clock-cells = <3>; 64 }; 65 ecia: ecia@4000e000 { 66 compatible = "microchip,xec-ecia"; 67 reg = <0x4000e000 0x400>; 68 direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>; 69 clocks = <&pcr 1 0 MCHP_XEC_PCR_CLK_PERIPH>; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 73 ranges = <0x0 0x4000e000 0x400>; 74 75 girq8: girq8@0 { 76 compatible = "microchip,xec-ecia-girq"; 77 reg = <0x0 0x14>; 78 interrupts = <0 0>; 79 girq-id = <0>; 80 sources = <0 1 2 3 4 5 6 7 81 8 9 10 11 12 13 14 15 82 16 17 18 21 22 24 25 83 26 27 28 29>; 84 status = "disabled"; 85 }; 86 girq9: girq9@14 { 87 compatible = "microchip,xec-ecia-girq"; 88 reg = <0x14 0x14>; 89 interrupts = <1 0>; 90 girq-id = <1>; 91 sources = <0 1 2 3 4 5 6 7 92 8 9 10 11 12 13 14 15 93 16 17 18 19 20 21 22 23 94 24 25 26 27 28 29>; 95 status = "disabled"; 96 }; 97 girq10: girq10@28 { 98 compatible = "microchip,xec-ecia-girq"; 99 reg = <0x28 0x14>; 100 interrupts = <2 0>; 101 girq-id = <2>; 102 sources = <0 1 2 3 4 5 6 7 103 8 9 10 11 12 13 14 15 104 16 17 18 19 20 21 22 23 105 24 25 26 27 28 29 30>; 106 status = "disabled"; 107 }; 108 girq11: girq11@3c { 109 compatible = "microchip,xec-ecia-girq"; 110 reg = <0x3c 0x14>; 111 interrupts = <3 0>; 112 girq-id = <3>; 113 sources = <0 1 2 3 4 5 6 7 114 8 9 10 11 12 13 14 15 115 16 17 18 19 20 21 22 23 116 24 25 26 27 28 29 30>; 117 status = "disabled"; 118 }; 119 girq12: girq12@50 { 120 compatible = "microchip,xec-ecia-girq"; 121 reg = <0x50 0x14>; 122 interrupts = <4 0>; 123 girq-id = <4>; 124 sources = <0 1 2 3 4 5 6 7 125 8 9 10 11 12 13 14 15 126 16 17 18 19 20 21 22 23 127 24 25 26 27 28 29 30>; 128 status = "disabled"; 129 }; 130 girq13: girq13@64 { 131 compatible = "microchip,xec-ecia-girq"; 132 reg = <0x64 0x14>; 133 interrupts = <5 0>; 134 girq-id = <5>; 135 sources = <0 1 2 3 4>; 136 status = "disabled"; 137 }; 138 girq14: girq14@78 { 139 compatible = "microchip,xec-ecia-girq"; 140 reg = <0x78 0x14>; 141 interrupts = <6 0>; 142 girq-id = <6>; 143 sources = <0 1 2 3 4 5 6 7 144 8 9 10 11 12 13 14 15>; 145 status = "disabled"; 146 }; 147 girq15: girq15@8c { 148 compatible = "microchip,xec-ecia-girq"; 149 reg = <0x8c 0x14>; 150 interrupts = <7 0>; 151 girq-id = <7>; 152 sources = <0 1 2 3 4 5 6 7 153 8 9 10 11 12 13 14 15 154 16 17 18 19 20 22>; 155 status = "disabled"; 156 }; 157 girq16: girq16@a0 { 158 compatible = "microchip,xec-ecia-girq"; 159 reg = <0xa0 0x14>; 160 interrupts = <8 0>; 161 girq-id = <8>; 162 sources = <0 2 3>; 163 status = "disabled"; 164 }; 165 girq17: girq17@b4 { 166 compatible = "microchip,xec-ecia-girq"; 167 reg = <0xb4 0x14>; 168 interrupts = <9 0>; 169 girq-id = <9>; 170 sources = <0 1 2 3 4 8 9 10 11 12 13 14 15 171 16 17 20 21 22 23>; 172 status = "disabled"; 173 }; 174 girq18: girq18@c8 { 175 compatible = "microchip,xec-ecia-girq"; 176 reg = <0xc8 0x14>; 177 interrupts = <10 0>; 178 girq-id = <10>; 179 sources = <0 1 2 3 4 5 6 7 180 10 20 21 22 23 181 24 25 26 27 28>; 182 status = "disabled"; 183 }; 184 girq19: girq19@dc { 185 compatible = "microchip,xec-ecia-girq"; 186 reg = <0xdc 0x14>; 187 interrupts = <11 0>; 188 girq-id = <11>; 189 sources = <0 1 2 3 4 5 6 7 8 9 10>; 190 status = "disabled"; 191 }; 192 girq20: girq20@f0 { 193 compatible = "microchip,xec-ecia-girq"; 194 reg = <0xf0 0x14>; 195 interrupts = <12 0>; 196 girq-id = <12>; 197 sources = <3 9>; 198 status = "disabled"; 199 }; 200 girq21: girq21@104 { 201 compatible = "microchip,xec-ecia-girq"; 202 reg = <0x104 0x14>; 203 interrupts = <13 0>; 204 girq-id = <13>; 205 sources = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 206 18 19 25 26>; 207 status = "disabled"; 208 }; 209 girq22: girq22@118 { 210 compatible = "microchip,xec-ecia-girq"; 211 reg = <0x118 0x14>; 212 interrupts = <255 0>; 213 girq-id = <14>; 214 sources = <0 1 2 3 4 5 9 15>; 215 status = "disabled"; 216 }; 217 girq23: girq23@12c { 218 compatible = "microchip,xec-ecia-girq"; 219 reg = <0x12c 0x14>; 220 interrupts = <14 0>; 221 girq-id = <15>; 222 sources = <0 1 2 3 4 5 6 7 8 9 10 16 17>; 223 status = "disabled"; 224 }; 225 girq24: girq24@140 { 226 compatible = "microchip,xec-ecia-girq"; 227 reg = <0x140 0x14>; 228 interrupts = <15 0>; 229 girq-id = <16>; 230 sources = <0 1 2 3 4 5 6 7 8 9 10 11 231 12 13 14 15 16 17 18 19 232 20 21 22 23 24 25 26 27>; 233 status = "disabled"; 234 }; 235 girq25: girq25@154 { 236 compatible = "microchip,xec-ecia-girq"; 237 reg = <0x154 0x14>; 238 interrupts = <16 0>; 239 girq-id = <17>; 240 sources = <0 1 2 3 4 5 6 7 8 9 10 11 241 12 13 14 15>; 242 status = "disabled"; 243 }; 244 girq26: girq26@168 { 245 compatible = "microchip,xec-ecia-girq"; 246 reg = <0x168 0x14>; 247 interrupts = <17 0>; 248 girq-id = <18>; 249 sources = <0 1 2 3 4 5 6 12 13>; 250 status = "disabled"; 251 }; 252 }; 253 pinctrl: pin-controller@40081000 { 254 compatible = "microchip,xec-pinctrl"; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 reg = <0x40081000 0x1000>; 258 259 gpio_000_036: gpio@40081000 { 260 compatible = "microchip,xec-gpio-v2"; 261 reg = < 0x40081000 0x80 0x40081300 0x04 262 0x40081380 0x04 0x400813fc 0x04>; 263 interrupts = <3 2>; 264 gpio-controller; 265 port-id = <0>; 266 girq-id = <11>; 267 #gpio-cells=<2>; 268 }; 269 gpio_040_076: gpio@40081080 { 270 compatible = "microchip,xec-gpio-v2"; 271 reg = < 0x40081080 0x80 0x40081304 0x04 272 0x40081384 0x04 0x400813f8 0x4>; 273 interrupts = <2 2>; 274 gpio-controller; 275 port-id = <1>; 276 girq-id = <10>; 277 #gpio-cells=<2>; 278 }; 279 gpio_100_136: gpio@40081100 { 280 compatible = "microchip,xec-gpio-v2"; 281 reg = < 0x40081100 0x80 0x40081308 0x04 282 0x40081388 0x04 0x400813f4 0x04>; 283 gpio-controller; 284 interrupts = <1 2>; 285 port-id = <2>; 286 girq-id = <9>; 287 #gpio-cells=<2>; 288 }; 289 gpio_140_176: gpio@40081180 { 290 compatible = "microchip,xec-gpio-v2"; 291 reg = < 0x40081180 0x80 0x4008130c 0x04 292 0x4008138c 0x04 0x400813f0 0x04>; 293 gpio-controller; 294 interrupts = <0 2>; 295 port-id = <3>; 296 girq-id = <8>; 297 #gpio-cells=<2>; 298 }; 299 gpio_200_236: gpio@40081200 { 300 compatible = "microchip,xec-gpio-v2"; 301 reg = < 0x40081200 0x80 0x40081310 0x04 302 0x40081390 0x04 0x400813ec 0x04>; 303 gpio-controller; 304 interrupts = <4 2>; 305 port-id = <4>; 306 girq-id = <12>; 307 #gpio-cells=<2>; 308 }; 309 gpio_240_276: gpio@40081280 { 310 compatible = "microchip,xec-gpio-v2"; 311 reg = < 0x40081280 0x80 0x40081314 0x04 312 0x40081394 0x04 0x400813e8 0x04>; 313 gpio-controller; 314 interrupts = <17 2>; 315 port-id = <5>; 316 girq-id = <26>; 317 #gpio-cells=<2>; 318 }; 319 }; 320 wdog: watchdog@40000400 { 321 compatible = "microchip,xec-watchdog"; 322 reg = <0x40000400 0x400>; 323 interrupts = <171 0>; 324 girqs = <21 2>; 325 pcrs = <1 9>; 326 }; 327 rtimer: timer@40007400 { 328 compatible = "microchip,xec-rtos-timer"; 329 reg = <0x40007400 0x10>; 330 interrupts = <111 0>; 331 girqs = <23 10>; 332 }; 333 timer0: timer@40000c00 { 334 compatible = "microchip,xec-timer"; 335 clock-frequency = <48000000>; 336 reg = <0x40000c00 0x20>; 337 interrupts = <136 0>; 338 girqs = <23 0>; 339 pcrs = <1 30>; 340 max-value = <0xFFFF>; 341 prescaler = <0>; 342 status = "disabled"; 343 }; 344 timer1: timer@40000c20 { 345 compatible = "microchip,xec-timer"; 346 clock-frequency = <48000000>; 347 reg = <0x40000c20 0x20>; 348 interrupts = <137 0>; 349 girqs = <23 1>; 350 pcrs = <1 31>; 351 max-value = <0xFFFF>; 352 prescaler = <0>; 353 status = "disabled"; 354 }; 355 timer2: timer@40000c40 { 356 compatible = "microchip,xec-timer"; 357 clock-frequency = <48000000>; 358 reg = <0x40000c40 0x20>; 359 interrupts = <138 0>; 360 girqs = <23 2>; 361 pcrs = <3 21>; 362 max-value = <0xFFFF>; 363 prescaler = <0>; 364 status = "disabled"; 365 }; 366 timer3: timer@40000c60 { 367 compatible = "microchip,xec-timer"; 368 clock-frequency = <48000000>; 369 reg = <0x40000c60 0x20>; 370 interrupts = <139 0>; 371 girqs = <23 3>; 372 pcrs = <3 22>; 373 max-value = <0xFFFF>; 374 prescaler = <0>; 375 status = "disabled"; 376 }; 377 /* 378 * NOTE: When RTOS timer used as kernel timer, timer4 used 379 * to provide high speed busy wait counter. Keep disabled to 380 * prevent counter driver from claiming it. 381 */ 382 timer4: timer@40000c80 { 383 compatible = "microchip,xec-timer"; 384 clock-frequency = <48000000>; 385 reg = <0x40000c80 0x20>; 386 interrupts = <140 0>; 387 girqs = <23 4>; 388 pcrs = <3 23>; 389 max-value = <0xFFFFFFFF>; 390 prescaler = <0>; 391 status = "disabled"; 392 }; 393 timer5: timer@40000ca0 { 394 compatible = "microchip,xec-timer"; 395 clock-frequency = <48000000>; 396 reg = <0x40000ca0 0x20>; 397 interrupts = <141 0>; 398 girqs = <23 5>; 399 pcrs = <3 24>; 400 max-value = <0xFFFFFFFF>; 401 prescaler = <0>; 402 status = "disabled"; 403 }; 404 cntr0: timer@40000d00 { 405 reg = <0x40000d00 0x20>; 406 interrupts = <142 0>; 407 girqs = <23 6>; 408 pcrs = <4 2>; 409 status = "disabled"; 410 }; 411 cntr1: timer@40000d20 { 412 reg = <0x40000d20 0x20>; 413 interrupts = <143 0>; 414 girqs = <23 7>; 415 pcrs = <4 3>; 416 status = "disabled"; 417 }; 418 cntr2: timer@40000d40 { 419 reg = <0x40000d40 0x20>; 420 interrupts = <144 0>; 421 girqs = <23 8>; 422 pcrs = <4 3>; 423 status = "disabled"; 424 }; 425 cntr3: timer@40000d60 { 426 reg = <0x40000d60 0x20>; 427 interrupts = <145 0>; 428 girqs = <23 9>; 429 pcrs = <4 4>; 430 status = "disabled"; 431 }; 432 cctmr0: timer@40001000 { 433 reg = <0x40001000 0x40>; 434 interrupts = <146 0>, <147 0>, <148 0>, <149 0>, 435 <150 0>, <151 0>, <152 0>, <153 0>, 436 <154 0>; 437 girqs = <18 20>, <18 21>, <18 22>, <18 23>, <18 24>, 438 <18 25>, <18 26>, <18 27>, <18 28>; 439 pcrs = <3 30>; 440 status = "disabled"; 441 }; 442 hibtimer0: timer@40009800 { 443 reg = <0x40009800 0x20>; 444 interrupts = <112 0>; 445 girqs = <23 16>; 446 }; 447 hibtimer1: timer@40009820 { 448 reg = <0x40009820 0x20>; 449 interrupts = <113 0>; 450 girqs = <23 17>; 451 }; 452 weektmr0: timer@4000ac80 { 453 reg = <0x4000ac80 0x80>; 454 interrupts = <114 0>, <115 0>, <116 0>, 455 <117 0>, <118 0>; 456 girqs = <21 3>, <21 4>, <21 5>, <21 6>, <21 7>; 457 status = "disabled"; 458 }; 459 bbram: bb-ram@4000a800 { 460 compatible = "microchip,xec-bbram"; 461 reg = <0x4000a800 0x100>; 462 reg-names = "memory"; 463 }; 464 vci0: vci@4000ae00 { 465 reg = <0x4000ae00 0x40>; 466 interrupts = <121 0>, <122 0>, <123 0>, 467 <124 0>, <125 0>; 468 girqs = <21 10>, <21 11>, <21 12>, <21 13>, <21 14>; 469 status = "disabled"; 470 }; 471 dmac: dmac@40002400 { 472 compatible = "microchip,xec-dmac"; 473 reg = <0x40002400 0xc00>; 474 interrupts = <24 1>, <25 1>, <26 1>, <27 1>, 475 <28 1>, <29 1>, <30 1>, <31 1>, 476 <32 1>, <33 1>, <34 1>, <35 1>, 477 <36 1>, <37 1>, <38 1>, <39 1>; 478 girqs = < MCHP_XEC_ECIA(14, 0, 6, 24) 479 MCHP_XEC_ECIA(14, 1, 6, 25) 480 MCHP_XEC_ECIA(14, 2, 6, 26) 481 MCHP_XEC_ECIA(14, 3, 6, 27) 482 MCHP_XEC_ECIA(14, 4, 6, 28) 483 MCHP_XEC_ECIA(14, 5, 6, 29) 484 MCHP_XEC_ECIA(14, 6, 6, 30) 485 MCHP_XEC_ECIA(14, 7, 6, 31) 486 MCHP_XEC_ECIA(14, 8, 6, 32) 487 MCHP_XEC_ECIA(14, 9, 6, 33) 488 MCHP_XEC_ECIA(14, 10, 6, 34) 489 MCHP_XEC_ECIA(14, 11, 6, 35) 490 MCHP_XEC_ECIA(14, 12, 6, 36) 491 MCHP_XEC_ECIA(14, 13, 6, 37) 492 MCHP_XEC_ECIA(14, 14, 6, 38) 493 MCHP_XEC_ECIA(14, 15, 6, 39) >; 494 pcrs = <1 6>; 495 #dma-cells = <2>; 496 dma-channels = <16>; 497 dma-requests = <16>; 498 status = "disabled"; 499 }; 500 eeprom: eeprom@40002c00 { 501 compatible = "microchip,xec-eeprom"; 502 reg = <0x40002c00 0x400>; 503 interrupts = <155 2>; 504 size = <2048>; 505 girqs = <18 13>; 506 pcrs = <4 14>; 507 status = "disabled"; 508 }; 509 i2c_smb_0: i2c@40004000 { 510 compatible = "microchip,xec-i2c-v2"; 511 reg = <0x40004000 0x80>; 512 clock-frequency = <I2C_BITRATE_STANDARD>; 513 interrupts = <20 1>; 514 girqs = <13 0>; 515 pcrs = <1 10>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 status = "disabled"; 519 }; 520 i2c_smb_1: i2c@40004400 { 521 compatible = "microchip,xec-i2c-v2"; 522 reg = <0x40004400 0x80>; 523 clock-frequency = <I2C_BITRATE_STANDARD>; 524 interrupts = <21 1>; 525 girqs = <13 1>; 526 pcrs = <3 13>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 status = "disabled"; 530 }; 531 i2c_smb_2: i2c@40004800 { 532 compatible = "microchip,xec-i2c-v2"; 533 reg = <0x40004800 0x80>; 534 clock-frequency = <I2C_BITRATE_STANDARD>; 535 interrupts = <22 1>; 536 girqs = <13 2>; 537 pcrs = <3 14>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 i2c_smb_3: i2c@40004c00 { 543 compatible = "microchip,xec-i2c-v2"; 544 reg = <0x40004C00 0x80>; 545 clock-frequency = <I2C_BITRATE_STANDARD>; 546 interrupts = <23 1>; 547 girqs = <13 3>; 548 pcrs = <3 15>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 i2c_smb_4: i2c@40005000 { 554 compatible = "microchip,xec-i2c-v2"; 555 reg = <0x40005000 0x80>; 556 clock-frequency = <I2C_BITRATE_STANDARD>; 557 interrupts = <158 1>; 558 girqs = <13 4>; 559 pcrs = <3 20>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 status = "disabled"; 563 }; 564 ps2_0: ps2@40009000 { 565 compatible = "microchip,xec-ps2"; 566 reg = <0x40009000 0x40>; 567 interrupts = <100 1>; 568 girqs = <18 10>; 569 pcrs = <3 5>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 status = "disabled"; 573 }; 574 pwm0: pwm@40005800 { 575 compatible = "microchip,xec-pwm"; 576 reg = <0x40005800 0x20>; 577 pcrs = <1 4>; 578 status = "disabled"; 579 #pwm-cells = <3>; 580 }; 581 pwm1: pwm@40005810 { 582 compatible = "microchip,xec-pwm"; 583 reg = <0x40005810 0x20>; 584 pcrs = <1 20>; 585 status = "disabled"; 586 #pwm-cells = <3>; 587 }; 588 pwm2: pwm@40005820 { 589 compatible = "microchip,xec-pwm"; 590 reg = <0x40005820 0x20>; 591 pcrs = <1 21>; 592 status = "disabled"; 593 #pwm-cells = <3>; 594 }; 595 pwm3: pwm@40005830 { 596 compatible = "microchip,xec-pwm"; 597 reg = <0x40005830 0x20>; 598 pcrs = <1 22>; 599 status = "disabled"; 600 #pwm-cells = <3>; 601 }; 602 pwm4: pwm@40005840 { 603 compatible = "microchip,xec-pwm"; 604 reg = <0x40005840 0x20>; 605 pcrs = <1 23>; 606 status = "disabled"; 607 #pwm-cells = <3>; 608 }; 609 pwm5: pwm@40005850 { 610 compatible = "microchip,xec-pwm"; 611 reg = <0x40005850 0x20>; 612 pcrs = <1 24>; 613 status = "disabled"; 614 #pwm-cells = <3>; 615 }; 616 pwm6: pwm@40005860 { 617 compatible = "microchip,xec-pwm"; 618 reg = <0x40005860 0x20>; 619 pcrs = <1 25>; 620 status = "disabled"; 621 #pwm-cells = <3>; 622 }; 623 pwm7: pwm@40005870 { 624 compatible = "microchip,xec-pwm"; 625 reg = <0x40005870 0x20>; 626 pcrs = <1 26>; 627 status = "disabled"; 628 #pwm-cells = <3>; 629 }; 630 pwm8: pwm@40005880 { 631 compatible = "microchip,xec-pwm"; 632 reg = <0x40005880 0x20>; 633 pcrs = <1 27>; 634 status = "disabled"; 635 #pwm-cells = <3>; 636 }; 637 tach0: tach@40006000 { 638 compatible = "microchip,xec-tach"; 639 reg = <0x40006000 0x10>; 640 interrupts = <71 4>; 641 girqs = <17 1>; 642 pcrs = <1 2>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 status = "disabled"; 646 }; 647 tach1: tach@40006010 { 648 compatible = "microchip,xec-tach"; 649 reg = <0x40006010 0x10>; 650 interrupts = <72 4>; 651 girqs = <17 2>; 652 pcrs = <1 11>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 status = "disabled"; 656 }; 657 tach2: tach@40006020 { 658 compatible = "microchip,xec-tach"; 659 reg = <0x40006020 0x10>; 660 interrupts = <73 4>; 661 girqs = <17 3>; 662 pcrs = <1 12>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 status = "disabled"; 666 }; 667 tach3: tach@40006030 { 668 compatible = "microchip,xec-tach"; 669 reg = <0x40006030 0x10>; 670 interrupts = <159 4>; 671 girqs = <17 4>; 672 pcrs = <1 13>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 status = "disabled"; 676 }; 677 rpmfan0: rpmfan@4000a000 { 678 reg = <0x4000a000 0x80>; 679 interrupts = <74 1>, <75 1>; 680 girqs = <17 20>, <17 21>; 681 pcrs = <3 12>; 682 status = "disabled"; 683 }; 684 rpmfan1: rpmfan@4000a080 { 685 reg = <0x4000a080 0x80>; 686 interrupts = <76 1>, <77 1>; 687 girqs = <17 22>, <17 23>; 688 pcrs = <4 7>; 689 status = "disabled"; 690 }; 691 adc0: adc@40007c00 { 692 compatible = "microchip,xec-adc"; 693 reg = <0x40007c00 0x90>; 694 interrupts = <78 0>, <79 0>; 695 girqs = <17 8>, <17 9>; 696 pcrs = <3 3>; 697 status = "disabled"; 698 #io-channel-cells = <1>; 699 clktime = <32>; 700 }; 701 kscan0: kscan@40009c00 { 702 compatible = "microchip,xec-kscan"; 703 reg = <0x40009c00 0x18>; 704 interrupts = <135 0>; 705 girqs = <21 25>; 706 pcrs = <3 11>; 707 status = "disabled"; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 }; 711 peci0: peci@40006400 { 712 compatible = "microchip,xec-peci"; 713 reg = <0x40006400 0x80>; 714 interrupts = <70 4>; 715 girqs = <17 0>; 716 pcrs = <1 1>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 }; 720 spi0: spi@40070000 { 721 reg = <0x40070000 0x400>; 722 interrupts = <91 2>; 723 girqs = < MCHP_XEC_ECIA(18, 1, 10, 91) >; 724 clocks = <&pcr 4 8 MCHP_XEC_PCR_CLK_PERIPH>; 725 clock-frequency = <12000000>; 726 lines = <1>; 727 chip-select = <0>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 status = "disabled"; 731 }; 732 spi1: spi@40009400 { 733 reg = <0x40009400 0x80>; 734 interrupts = <92 2>, <93 2>; 735 girqs = <18 2>, <18 3>; 736 pcrs = <3 9>; 737 status = "disabled"; 738 }; 739 spi2: spi@40009480 { 740 reg = <0x40009480 0x80>; 741 interrupts = <94 2>, <95 2>; 742 girqs = <18 4>, <18 5>; 743 pcrs = <4 22>; 744 status = "disabled"; 745 }; 746 prochot0: prochot@40003400 { 747 reg = <0x40003400 0x20>; 748 interrupts = <87 0>; 749 girqs = <17 17>; 750 pcrs = <4 13>; 751 status = "disabled"; 752 }; 753 rcid0: rcid@40001400 { 754 reg = <0x40001400 0x80>; 755 interrupts = <80 0>; 756 girqs = <17 10>; 757 pcrs = <4 10>; 758 status = "disabled"; 759 }; 760 rcid1: rcid@40001480 { 761 reg = <0x40001480 0x80>; 762 interrupts = <81 0>; 763 girqs = <17 11>; 764 pcrs = <4 11>; 765 status = "disabled"; 766 }; 767 rcid2: rcid@40001500 { 768 reg = <0x40001500 0x80>; 769 interrupts = <82 0>; 770 girqs = <17 12>; 771 pcrs = <4 12>; 772 status = "disabled"; 773 }; 774 spip0: spip@40007000 { 775 reg = <0x40007000 0x100>; 776 interrupts = <90 0>; 777 girqs = <18 0>; 778 pcrs = <4 16>; 779 status = "disabled"; 780 }; 781 bbled0: bbled@4000b800 { 782 reg = <0x4000b800 0x100>; 783 interrupts = <83 0>; 784 girqs = <17 13>; 785 pcrs = <3 16>; 786 status = "disabled"; 787 }; 788 bbled1: bbled@4000b900 { 789 reg = <0x4000b900 0x100>; 790 interrupts = <84 0>; 791 girqs = <17 14>; 792 pcrs = <3 17>; 793 status = "disabled"; 794 }; 795 bbled2: bbled@4000ba00 { 796 reg = <0x4000ba00 0x100>; 797 interrupts = <85 0>; 798 girqs = <17 15>; 799 pcrs = <3 18>; 800 status = "disabled"; 801 }; 802 bbled3: bbled@4000bb00 { 803 reg = <0x4000bb00 0x100>; 804 interrupts = <86 0>; 805 girqs = <17 16>; 806 pcrs = <3 25>; 807 status = "disabled"; 808 }; 809 bclink0: bclink@4000cd00 { 810 reg = <0x4000cd00 0x20>; 811 interrupts = <96 0>, <97 0>; 812 girqs = <18 7>, <18 6>; 813 pcrs = <3 19>; 814 status = "disabled"; 815 }; 816 tfdp0: tfdp@40008c00 { 817 reg = <0x40008c00 0x10>; 818 pcrs = <1 7>; 819 status = "disabled"; 820 }; 821 glblcfg0: glblcfg@400fff00 { 822 reg = <0x400fff00 0x40>; 823 pcrs = <2 12>; 824 status = "disabled"; 825 }; 826 uart0: uart@400f2400 { 827 compatible = "microchip,xec-uart"; 828 reg = <0x400f2400 0x400>; 829 interrupts = <40 1>; 830 clock-frequency = <1843200>; 831 current-speed = <38400>; 832 girqs = <15 0>; 833 pcrs = <2 1>; 834 ldn = <9>; 835 status = "disabled"; 836 }; 837 uart1: uart@400f2800 { 838 compatible = "microchip,xec-uart"; 839 reg = <0x400f2800 0x400>; 840 interrupts = <41 1>; 841 clock-frequency = <1843200>; 842 current-speed = <38400>; 843 girqs = <15 1>; 844 pcrs = <2 2>; 845 ldn = <10>; 846 status = "disabled"; 847 }; 848 espi0: espi@400f3400 { 849 compatible = "microchip,xec-espi-v2"; 850 /* reg tuple contains one 32-bit address cell and one 851 * 32-bit length(size) cell. 852 */ 853 #address-cells = <1>; 854 #size-cells = <1>; 855 reg = < 0x400f3400 0x400 856 0x400f3800 0x400 857 0x400f9c00 0x400>; 858 reg-names = "io", "mem", "vw"; 859 interrupts = <103 3>, <104 3>, <105 3>, <106 3>, 860 <107 3>, <108 3>, <109 3>, <110 2>, 861 <156 3>; 862 interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up", 863 "oob_dn", "fc", "rst", "vw_chan_en"; 864 girqs = < MCHP_XEC_ECIA(19, 0, 11, 103) 865 MCHP_XEC_ECIA(19, 1, 11, 104) 866 MCHP_XEC_ECIA(19, 2, 11, 105) 867 MCHP_XEC_ECIA(19, 3, 11, 106) 868 MCHP_XEC_ECIA(19, 4, 11, 107) 869 MCHP_XEC_ECIA(19, 5, 11, 108) 870 MCHP_XEC_ECIA(19, 6, 11, 109) 871 MCHP_XEC_ECIA(19, 7, 11, 110) 872 MCHP_XEC_ECIA(19, 8, 11, 156) >; 873 pcrs = <2 19>; 874 status = "disabled"; 875 876 espi_saf0: espi_saf@40008000 { 877 compatible = "microchip,xec-espi-saf-v2"; 878 reg = <0x40008000 0x400>, <0x40070000 0x400>, 879 <0x40071000 0x400>; 880 reg-names = "safbr", "safqspi", "safcomm"; 881 interrupts = <166 3>, <167 3>; 882 interrupt-names = "done", "err"; 883 girqs = < MCHP_XEC_ECIA(19, 9, 11, 166) >, 884 < MCHP_XEC_ECIA(19, 10, 11, 167) >; 885 pcrs = <2 27>; 886 status = "disabled"; 887 }; 888 889 mbox0: mbox@400f0000 { 890 compatible = "microchip,xec-espi-host-dev"; 891 reg = <0x400f0000 0x200>; 892 interrupts = <60 3>; 893 girqs = < MCHP_XEC_ECIA(15, 20, 7, 60) >; 894 pcrs = <2 17>; 895 ldn = <0>; 896 status = "disabled"; 897 }; 898 kbc0: kbc@400f0400 { 899 compatible = "microchip,xec-espi-host-dev"; 900 reg = <0x400f0400 0x400>; 901 interrupts = <58 3>, <59 3>; 902 interrupt-names = "kbc_obe", "kbc_ibf"; 903 girqs = < MCHP_XEC_ECIA(15, 18, 7, 58) 904 MCHP_XEC_ECIA(15, 19, 7, 59) >; 905 ldn = <1>; 906 status = "disabled"; 907 }; 908 acpi_ec0: acpi_ec@400f0800 { 909 compatible = "microchip,xec-espi-host-dev"; 910 reg = <0x400f0800 0x400>; 911 interrupts = <45 3>, <46 3>; 912 interrupt-names = "acpi_ibf", "acpi_obe"; 913 girqs = < MCHP_XEC_ECIA(15, 5, 7, 45) 914 MCHP_XEC_ECIA(15, 6, 7, 46) >; 915 ldn = <2>; 916 status = "disabled"; 917 }; 918 acpi_ec1: acpi_ec@400f0c00 { 919 compatible = "microchip,xec-espi-host-dev"; 920 reg = <0x400f0c00 0x400>; 921 interrupts = <47 3>, <48 3>; 922 interrupt-names = "acpi_ibf", "acpi_obe"; 923 girqs = < MCHP_XEC_ECIA(15, 7, 7, 47) 924 MCHP_XEC_ECIA(15, 8, 7, 48) >; 925 ldn = <3>; 926 status = "disabled"; 927 }; 928 acpi_ec2: acpi_ec@400f1000 { 929 compatible = "microchip,xec-espi-host-dev"; 930 reg = <0x400f1000 0x400>; 931 interrupts = <49 3>, <50 3>; 932 interrupt-names = "acpi_ibf", "acpi_obe"; 933 girqs = < MCHP_XEC_ECIA(15, 9, 7, 49) 934 MCHP_XEC_ECIA(15, 10, 7, 50) >; 935 ldn = <4>; 936 status = "disabled"; 937 }; 938 acpi_ec3: acpi_ec@400f1400 { 939 compatible = "microchip,xec-espi-host-dev"; 940 reg = <0x400f1400 0x400>; 941 interrupts = <51 3>, <52 3>; 942 interrupt-names = "acpi_ibf", "acpi_obe"; 943 girqs = < MCHP_XEC_ECIA(15, 11, 7, 51) 944 MCHP_XEC_ECIA(15, 12, 7, 52) >; 945 ldn = <5>; 946 status = "disabled"; 947 }; 948 acpi_ec4: acpi_ec@400f1800 { 949 compatible = "microchip,xec-espi-host-dev"; 950 reg = <0x400f1800 0x400>; 951 interrupts = <53 3>, <54 3>; 952 interrupt-names = "acpi_ibf", "acpi_obe"; 953 girqs = < MCHP_XEC_ECIA(15, 13, 7, 53) 954 MCHP_XEC_ECIA(15, 14, 7, 54) >; 955 ldn = <6>; 956 status = "disabled"; 957 }; 958 acpi_pm1: acpi_pm1@400f1c00 { 959 compatible = "microchip,xec-espi-host-dev"; 960 reg = <0x400f1c00 0x400>; 961 interrupts = <55 3>, <56 3>, <57 3>; 962 interrupt-names = "pm1_ctl", "pm1_en", "pm1_sts"; 963 girqs = < MCHP_XEC_ECIA(15, 15, 7, 55) 964 MCHP_XEC_ECIA(15, 16, 7, 56) 965 MCHP_XEC_ECIA(15, 17, 7, 57) >; 966 ldn = <7>; 967 status = "disabled"; 968 }; 969 port92: port92@400f2000 { 970 compatible = "microchip,xec-espi-host-dev"; 971 reg = <0x400f2000 0x400>; 972 ldn = <8>; 973 status = "disabled"; 974 }; 975 emi0: emi@400f4000 { 976 compatible = "microchip,xec-espi-host-dev"; 977 reg = <0x400f4000 0x400>; 978 interrupts = <42 3>; 979 girqs = < MCHP_XEC_ECIA(15, 2, 7, 42) >; 980 ldn = <16>; 981 status = "disabled"; 982 }; 983 emi1: emi@400f4400 { 984 compatible = "microchip,xec-espi-host-dev"; 985 reg = <0x400f4400 0x400>; 986 interrupts = <43 3>; 987 girqs = < MCHP_XEC_ECIA(15, 3, 7, 43) >; 988 ldn = <17>; 989 status = "disabled"; 990 }; 991 emi2: emi@400f4800 { 992 compatible = "microchip,xec-espi-host-dev"; 993 reg = <0x400f4800 0x400>; 994 interrupts = <44 3>; 995 girqs = < MCHP_XEC_ECIA(15, 4, 7, 44) >; 996 ldn = <18>; 997 status = "disabled"; 998 }; 999 rtc0: rtc@400f5000 { 1000 compatible = "microchip,xec-espi-host-dev"; 1001 reg = <0x400f5000 0x100>; 1002 interrupts = <119 3>, <120 3>; 1003 girqs = < MCHP_XEC_ECIA(21, 8, 13, 119) 1004 MCHP_XEC_ECIA(21, 9, 13, 120) >; 1005 pcrs = <2 18>; 1006 ldn = <20>; 1007 status = "disabled"; 1008 }; 1009 /* Capture writes to host I/O 0x80 - 0x83 */ 1010 p80bd0: p80bd@400f8000 { 1011 compatible = "microchip,xec-espi-host-dev"; 1012 reg = <0x400f8000 0x400>; 1013 interrupts = <62 0>; 1014 girqs = < MCHP_XEC_ECIA(15, 22, 7, 62) >; 1015 pcrs = <2 25>; 1016 ldn = <32>; 1017 status = "disabled"; 1018 }; 1019 /* Capture writes to an 8-bit I/O and map to one of 0x80 to 0x83 */ 1020 p80bd0_alias: p80bd@400f8400 { 1021 compatible = "microchip,xec-espi-host-dev"; 1022 reg = <0x400f8400 0x400>; 1023 ldn = <33>; 1024 host-io = <0x90>; 1025 /* map 0x90 to 0x80 */ 1026 host-io-addr-mask = <0x01>; 1027 status = "disabled"; 1028 }; 1029 }; 1030 1031 symcr: symcr@40100000 { 1032 compatible = "microchip,xec-symcr"; 1033 reg = <0x40100000 0x1000>; 1034 interrupts = <68 1>; 1035 clocks = <&pcr 3 26 MCHP_XEC_PCR_CLK_PERIPH>; 1036 girqs = <16 3>; 1037 status = "disabled"; 1038 #address-cells = <1>; 1039 #size-cells = <1>; 1040 }; 1041 1042 rom_api: rom_api@1f000 { 1043 reg = <0x1f000 0x1000>; 1044 status = "disabled"; 1045 }; 1046 }; 1047}; 1048 1049&nvic { 1050 arm,num-irq-priority-bits = <3>; 1051}; 1052 1053&systick { 1054 status = "disabled"; 1055}; 1056
