1 /*
2 * Copyright 2022-2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_s32_netc_emdio
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/drivers/mdio.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/logging/log.h>
13 LOG_MODULE_REGISTER(nxp_s32_emdio, CONFIG_MDIO_LOG_LEVEL);
14
15 #include <Netc_EthSwt_Ip.h>
16
17 struct nxp_s32_mdio_config {
18 const struct pinctrl_dev_config *pincfg;
19 uint8_t instance;
20 };
21
22 struct nxp_s32_mdio_data {
23 struct k_mutex rw_mutex;
24 };
25
nxp_s32_mdio_read(const struct device * dev,uint8_t prtad,uint8_t regad,uint16_t * regval)26 static int nxp_s32_mdio_read(const struct device *dev, uint8_t prtad,
27 uint8_t regad, uint16_t *regval)
28 {
29 const struct nxp_s32_mdio_config *cfg = dev->config;
30 struct nxp_s32_mdio_data *data = dev->data;
31 Std_ReturnType status;
32
33 k_mutex_lock(&data->rw_mutex, K_FOREVER);
34 status = Netc_EthSwt_Ip_ReadTrcvRegister(cfg->instance, prtad, regad, regval);
35 k_mutex_unlock(&data->rw_mutex);
36
37 return status == E_OK ? 0 : -EIO;
38 }
39
nxp_s32_mdio_write(const struct device * dev,uint8_t prtad,uint8_t regad,uint16_t regval)40 static int nxp_s32_mdio_write(const struct device *dev, uint8_t prtad,
41 uint8_t regad, uint16_t regval)
42 {
43 const struct nxp_s32_mdio_config *cfg = dev->config;
44 struct nxp_s32_mdio_data *data = dev->data;
45 Std_ReturnType status;
46
47 k_mutex_lock(&data->rw_mutex, K_FOREVER);
48 status = Netc_EthSwt_Ip_WriteTrcvRegister(cfg->instance, prtad, regad, regval);
49 k_mutex_unlock(&data->rw_mutex);
50
51 return status == E_OK ? 0 : -EIO;
52 }
53
nxp_s32_mdio_initialize(const struct device * dev)54 static int nxp_s32_mdio_initialize(const struct device *dev)
55 {
56 struct nxp_s32_mdio_data *data = dev->data;
57 const struct nxp_s32_mdio_config *cfg = dev->config;
58 int err;
59
60 err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
61 if (err != 0) {
62 return err;
63 }
64
65 k_mutex_init(&data->rw_mutex);
66
67 return 0;
68 }
69
70 static DEVICE_API(mdio, nxp_s32_mdio_api) = {
71 .read = nxp_s32_mdio_read,
72 .write = nxp_s32_mdio_write,
73 };
74
75 #define NXP_S32_MDIO_HW_INSTANCE_CHECK(i, n) \
76 ((DT_INST_REG_ADDR(n) == IP_NETC_EMDIO_##n##_BASE) ? i : 0)
77
78 #define NXP_S32_MDIO_HW_INSTANCE(n) \
79 LISTIFY(__DEBRACKET NETC_F1_INSTANCE_COUNT, NXP_S32_MDIO_HW_INSTANCE_CHECK, (|), n)
80
81 #define NXP_S32_MDIO_INSTANCE_DEFINE(n) \
82 PINCTRL_DT_INST_DEFINE(n); \
83 static struct nxp_s32_mdio_data nxp_s32_mdio##n##_data; \
84 static const struct nxp_s32_mdio_config nxp_s32_mdio##n##_cfg = { \
85 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
86 .instance = NXP_S32_MDIO_HW_INSTANCE(n), \
87 }; \
88 DEVICE_DT_INST_DEFINE(n, \
89 &nxp_s32_mdio_initialize, \
90 NULL, \
91 &nxp_s32_mdio##n##_data, \
92 &nxp_s32_mdio##n##_cfg, \
93 POST_KERNEL, \
94 CONFIG_MDIO_INIT_PRIORITY, \
95 &nxp_s32_mdio_api);
96
97 DT_INST_FOREACH_STATUS_OKAY(NXP_S32_MDIO_INSTANCE_DEFINE)
98
