1 /*
2  * Copyright 2024 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/devicetree.h>
8 #include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
9 
10 #define REGION_FLEXSPI2_BASE_ADDRESS   0x14000000
11 #define REGION_FLEXSPI2_SIZE           0x04000000
12 #define REGION_DTCM_BASE_ADDRESS       0x30000000
13 #define REGION_DTCM_SIZE               0x00020000
14 #define REGION_FLEXSPI_BASE_ADDRESS    0x38000000
15 #define REGION_FLEXSPI_SIZE            0x08000000
16 #define REGION_PERIPHERAL_BASE_ADDRESS 0x50000000
17 #define REGION_PERIPHERAL_SIZE         0x40000000
18 
19 static const struct arm_mpu_region mpu_regions[] = {
20 	MPU_REGION_ENTRY("FLEXSPI2", REGION_FLEXSPI2_BASE_ADDRESS,
21 			 REGION_RAM_ATTR(REGION_FLEXSPI2_BASE_ADDRESS, REGION_FLEXSPI2_SIZE)),
22 	MPU_REGION_ENTRY("FLEXSPI", REGION_FLEXSPI_BASE_ADDRESS,
23 			 REGION_FLASH_ATTR(REGION_FLEXSPI_BASE_ADDRESS, REGION_FLEXSPI_SIZE)),
24 	MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS,
25 			 REGION_RAM_NOCACHE_ATTR(REGION_DTCM_BASE_ADDRESS, REGION_DTCM_SIZE)),
26 	MPU_REGION_ENTRY(
27 		"PERIPHERAL", REGION_PERIPHERAL_BASE_ADDRESS,
28 		REGION_DEVICE_ATTR(REGION_PERIPHERAL_BASE_ADDRESS, REGION_PERIPHERAL_SIZE)),
29 };
30 
31 const struct arm_mpu_config mpu_config = {
32 	.num_regions = ARRAY_SIZE(mpu_regions),
33 	.mpu_regions = mpu_regions,
34 };
35