1 /*
2 * Copyright (c) 2017-2024 IAR Systems
3 * Copyright (c) 2017-2024 Arm Limited. All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Licensed under the Apache License, Version 2.0 (the License); you may
8 * not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 */
19
20 /*
21 * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File
22 */
23
24 #ifndef __CMSIS_ICCARM_M_H__
25 #define __CMSIS_ICCARM_M_H__
26
27 #ifndef __ICCARM__
28 #error This file should only be compiled by ICCARM
29 #endif
30
31 #pragma system_include
32
33 /* Define compiler macros for CPU architecture, used in CMSIS 5.
34 */
35 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__
36 /* Macros already defined */
37 #else
38 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
39 #define __ARM_ARCH_8M_MAIN__ 1
40 #elif defined(__ARM8M_BASELINE__)
41 #define __ARM_ARCH_8M_BASE__ 1
42 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
43 #if __ARM_ARCH == 6
44 #define __ARM_ARCH_6M__ 1
45 #elif __ARM_ARCH == 7
46 #if __ARM_FEATURE_DSP
47 #define __ARM_ARCH_7EM__ 1
48 #else
49 #define __ARM_ARCH_7M__ 1
50 #endif
51 #elif __ARM_ARCH == 801
52 #define __ARM_ARCH_8_1M_MAIN__ 1
53 #endif /* __ARM_ARCH */
54 #endif /* __ARM_ARCH_PROFILE == 'M' */
55 #endif
56
57 /* Alternativ core deduction for older ICCARM's */
58 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
59 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__)
60 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
61 #define __ARM_ARCH_6M__ 1
62 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
63 #define __ARM_ARCH_7M__ 1
64 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
65 #define __ARM_ARCH_7EM__ 1
66 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
67 #define __ARM_ARCH_8M_BASE__ 1
68 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
69 #define __ARM_ARCH_8M_MAIN__ 1
70 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
71 #define __ARM_ARCH_8M_MAIN__ 1
72 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801
73 #define __ARM_ARCH_8_1M_MAIN__ 1
74 #else
75 #error "Unknown target."
76 #endif
77 #endif
78
79
80
81 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
82 #define __IAR_M0_FAMILY 1
83 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
84 #define __IAR_M0_FAMILY 1
85 #else
86 #define __IAR_M0_FAMILY 0
87 #endif
88
89 #ifndef __PROGRAM_START
90 #define __PROGRAM_START __iar_program_start
91 #endif
92
93 #ifndef __INITIAL_SP
94 #define __INITIAL_SP CSTACK$$Limit
95 #endif
96
97 #ifndef __STACK_LIMIT
98 #define __STACK_LIMIT CSTACK$$Base
99 #endif
100
101 #ifndef __VECTOR_TABLE
102 #define __VECTOR_TABLE __vector_table
103 #endif
104
105 #ifndef __VECTOR_TABLE_ATTRIBUTE
106 #define __VECTOR_TABLE_ATTRIBUTE @".intvec"
107 #endif
108
109 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
110 #ifndef __STACK_SEAL
111 #define __STACK_SEAL STACKSEAL$$Base
112 #endif
113
114 #ifndef __TZ_STACK_SEAL_SIZE
115 #define __TZ_STACK_SEAL_SIZE 8U
116 #endif
117
118 #ifndef __TZ_STACK_SEAL_VALUE
119 #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
120 #endif
121
__TZ_set_STACKSEAL_S(uint32_t * stackTop)122 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
123 *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
124 }
125 #endif
126
127 #define __get_APSR() (__arm_rsr("APSR"))
128 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
129 #define __get_CONTROL() (__arm_rsr("CONTROL"))
130 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
131
132 #define __get_IPSR() (__arm_rsr("IPSR"))
133 #define __get_MSP() (__arm_rsr("MSP"))
134 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
135 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
136 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
137 // without main extensions, the non-secure MSPLIM is RAZ/WI
138 #define __get_MSPLIM() (0U)
139 #else
140 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
141 #endif
142 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
143 #define __get_PSP() (__arm_rsr("PSP"))
144
145 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
146 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
147 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
148 // without main extensions, the non-secure PSPLIM is RAZ/WI
149 #define __get_PSPLIM() (0U)
150 #else
151 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
152 #endif
153
154 #define __get_xPSR() (__arm_rsr("xPSR"))
155
156 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
157 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
158
__set_CONTROL(uint32_t control)159 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
160 {
161 __arm_wsr("CONTROL", control);
162 __iar_builtin_ISB();
163 }
164
165 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
166 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
167
168 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
169 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
170 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
171 // without main extensions, the non-secure MSPLIM is RAZ/WI
172 #define __set_MSPLIM(VALUE) ((void)(VALUE))
173 #else
174 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
175 #endif
176 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
177 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
178 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
179 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
180 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
181 // without main extensions, the non-secure PSPLIM is RAZ/WI
182 #define __set_PSPLIM(VALUE) ((void)(VALUE))
183 #else
184 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
185 #endif
186
187 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
188
__TZ_set_CONTROL_NS(uint32_t control)189 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
190 {
191 __arm_wsr("CONTROL_NS", control);
192 __iar_builtin_ISB();
193 }
194
195 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
196 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
197 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
198 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
199 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
200 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
201 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
202 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
203 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
204 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
205 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
206 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
207
208 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
209 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
210 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
211 // without main extensions, the non-secure PSPLIM is RAZ/WI
212 #define __TZ_get_PSPLIM_NS() (0U)
213 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
214 #else
215 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
216 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
217 #endif
218
219 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
220 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
221
222 #undef __IAR_FT
223 #undef __IAR_M0_FAMILY
224 #undef __ICCARM_V8
225
226 #pragma diag_default=Pe940
227 #pragma diag_default=Pe177
228
229
230 #endif /* __CMSIS_ICCARM_M_H__ */
231
