1 /* sensor_lps25hb.h - header file for LPS25HB pressure and temperature 2 * sensor driver 3 */ 4 5 /* 6 * Copyright (c) 2016 Intel Corporation 7 * 8 * SPDX-License-Identifier: Apache-2.0 9 */ 10 11 #ifndef ZEPHYR_DRIVERS_SENSOR_LPS25HB_LPS25HB_H_ 12 #define ZEPHYR_DRIVERS_SENSOR_LPS25HB_LPS25HB_H_ 13 14 #include <zephyr/types.h> 15 #include <zephyr/drivers/i2c.h> 16 #include <zephyr/sys/util.h> 17 18 #define LPS25HB_REG_WHO_AM_I 0x0F 19 #define LPS25HB_VAL_WHO_AM_I 0xBD 20 21 #define LPS25HB_REG_REF_P_XL 0x08 22 #define LPS25HB_REG_REF_P_L 0x09 23 #define LPS25HB_REG_REF_P_H 0x0A 24 25 #define LPS25HB_REG_RES_CONF 0x10 26 #define LPS25HB_MASK_RES_CONF_AVGT (BIT(3) | BIT(2)) 27 #define LPS25HB_SHIFT_RES_CONF_AVGT 2 28 #define LPS25HB_MASK_RES_CONF_AVGP (BIT(1) | BIT(0)) 29 #define LPS25HB_SHIFT_RES_CONF_AVGP 0 30 31 #define LPS25HB_REG_CTRL_REG1 0x20 32 #define LPS25HB_MASK_CTRL_REG1_PD BIT(7) 33 #define LPS25HB_SHIFT_CTRL_REG1_PD 7 34 #define LPS25HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4)) 35 #define LPS25HB_SHIFT_CTRL_REG1_ODR 4 36 #define LPS25HB_MASK_CTRL_REG1_DIFF_EN BIT(3) 37 #define LPS25HB_SHIFT_CTRL_REG1_DIFF_EN 3 38 #define LPS25HB_MASK_CTRL_REG1_BDU BIT(2) 39 #define LPS25HB_SHIFT_CTRL_REG1_BDU 2 40 #define LPS25HB_MASK_CTRL_REG1_RESET_AZ BIT(1) 41 #define LPS25HB_SHIFT_CTRL_REG1_RESET_AZ 1 42 #define LPS25HB_MASK_CTRL_REG1_SIM BIT(0) 43 #define LPS25HB_SHIFT_CTRL_REG1_SIM 0 44 45 #define LPS25HB_REG_CTRL_REG2 0x21 46 #define LPS25HB_MASK_CTRL_REG2_BOOT BIT(7) 47 #define LPS25HB_SHIFT_CTRL_REG2_BOOT 7 48 #define LPS25HB_MASK_CTRL_REG2_FIFO_EN BIT(6) 49 #define LPS25HB_SHIFT_CTRL_REG2_FIFO_EN 6 50 #define LPS25HB_MASK_CTRL_REG2_STOP_ON_FTH BIT(5) 51 #define LPS25HB_SHIFT_CTRL_REG2_STOP_ON_FTH 5 52 #define LPS25HB_MASK_CTRL_REG2_FIFO_MEAN_DEC BIT(4) 53 #define LPS25HB_SHIFT_CTRL_REG2_FIFO_MEAN_DEC 4 54 #define LPS25HB_MASK_CTRL_REG2_I2C_EN BIT(3) 55 #define LPS25HB_SHIFT_CTRL_REG2_I2C_EN 3 56 #define LPS25HB_MASK_CTRL_REG2_SWRESET BIT(2) 57 #define LPS25HB_SHIFT_CTRL_REG2_SWRESET 2 58 #define LPS25HB_MASK_CTRL_REG2_AUTOZERO BIT(1) 59 #define LPS25HB_SHIFT_CTRL_REG2_AUTOZERO 1 60 #define LPS25HB_MASK_CTRL_REG2_ONE_SHOT BIT(0) 61 #define LPS25HB_SHIFT_CTRL_REG2_ONE_SHOT 0 62 63 #define LPS25HB_REG_CTRL_REG3 0x22 64 #define LPS25HB_MASK_CTRL_REG3_INT_H_L BIT(7) 65 #define LPS25HB_SHIFT_CTRL_REG3_INT_H_L 7 66 #define LPS25HB_MASK_CTRL_REG3_PP_OD BIT(6) 67 #define LPS25HB_SHIFT_CTRL_REG3_PP_OD 6 68 #define LPS25HB_MASK_CTRL_REG3_INT_S (BIT(1) | BIT(0)) 69 #define LPS25HB_SHIFT_CTRL_REG_INT_S 0 70 71 #define LPS25HB_REG_CTRL_REG4 0x23 72 #define LPS25HB_MASK_CTRL_REG4_F_EMPTY BIT(3) 73 #define LPS25HB_SHIFT_CTRL_REG4_F_EMPTY 3 74 #define LPS25HB_MASK_CTRL_REG4_F_FTH BIT(2) 75 #define LPS25HB_SHIFT_CTRL_REG4_F_FTH 2 76 #define LPS25HB_MASK_CTRL_REG4_F_OVR BIT(1) 77 #define LPS25HB_SHIFT_CTRL_REG4_F_OVR 1 78 #define LPS25HB_MASK_CTRL_REG4_DRDY BIT(0) 79 #define LPS25HB_SHIFT_CTRL_REG4_DRDY 0 80 81 #define LPS25HB_REG_INTERRUPT_CFG 0x24 82 #define LPS25HB_MASK_INTERRUPT_CFG_LIR BIT(2) 83 #define LPS25HB_SHIFT_INTERRUPT_CFG_LIR 2 84 #define LPS25HB_MASK_INTERRUPT_CFG_PL_E BIT(1) 85 #define LPS25HB_SHIFT_INTERRUPT_CFG_PL_E 1 86 #define LPS25HB_MASK_INTERRUPT_CFG_PH_E BIT(0) 87 #define LPS25HB_SHIFT_INTERRUPT_CFG_PH_E 0 88 89 #define LPS25HB_REG_INT_SOURCE 0x25 90 #define LPS25HB_MASK_INT_SOURCE_IA BIT(2) 91 #define LPS25HB_SHIFT_INT_SOURCE_IA 2 92 #define LPS25HB_MASK_INT_SOURCE_PL BIT(1) 93 #define LPS25HB_SHIFT_INT_SOURCE_PL 1 94 #define LPS25HB_MASK_INT_SOURCE_PH BIT(0) 95 #define LPS25HB_SHIFT_INT_SOURCE_PH 0 96 97 #define LPS25HB_REG_STATUS_REG 0x27 98 #define LPS25HB_MASK_STATUS_REG_P_OR BIT(5) 99 #define LPS25HB_SHIFT_STATUS_REG_P_OR 5 100 #define LPS25HB_MASK_STATUS_REG_T_OR BIT(4) 101 #define LPS25HB_SHIFT_STATUS_REG_T_OR 4 102 #define LPS25HB_MASK_STATUS_REG_P_DA BIT(1) 103 #define LPS25HB_SHIFT_STATUS_REG_P_DA 1 104 #define LPS25HB_MASK_STATUS_REG_T_DA BIT(0) 105 #define LPS25HB_SHIFT_STATUS_REG_T_DA 0 106 107 #define LPS25HB_REG_PRESS_OUT_XL 0x28 108 #define LPS25HB_REG_PRESS_OUT_L 0x29 109 #define LPS25HB_REG_PRESS_OUT_H 0x2A 110 111 #define LPS25HB_REG_TEMP_OUT_L 0x2B 112 #define LPS25HB_REG_TEMP_OUT_H 0x2C 113 114 #define LPS25HB_REG_FIFO_CTRL 0x2E 115 #define LPS25HB_MASK_FIFO_CTRL_F_MODE (BIT(7) | BIT(6) | BIT(5)) 116 #define LPS25HB_SHIFT_FIFO_CTRL_F_MODE 5 117 #define LPS25HB_MASK_FIFO_CTRL_WTM_POINT (BIT(4) | BIT(3) | BIT(2) | \ 118 BIT(2) | BIT(1) | BIT(0)) 119 #define LPS25HB_SHIFT_FIFO_CTRL_WTM_POINT 0 120 121 #define LPS25HB_REG_FIFO_STATUS 0x2F 122 #define LPS25HB_MASK_FIFO_STATUS_FTH_FIFO BIT(7) 123 #define LPS25HB_SHIFT_FIFO_STATUS_FTH_FIFO 7 124 #define LPS25HB_MASK_FIFO_STATUS_OVR BIT(6) 125 #define LPS25HB_SHIFT_FIFO_STATUS_OVR 6 126 #define LPS25HB_MASK_FIFO_STATUS_EMPTY_FIFO BIT(5) 127 #define LPS25HB_SHIFT_FIFO_STATUS_EMPTY_FIFO 5 128 #define LPS25HB_MASK_FIFO_STATUS_FSS (BIT(4) | BIT(3) | BIT(2) | \ 129 BIT(1) | BIT(0)) 130 #define LPS25HB_SHIFT_FIFO_STATUS_FSS 0 131 132 #define LPS25HB_REG_THS_P_L 0x30 133 #define LPS25HB_REG_THS_P_H 0x31 134 135 #define LPS25HB_REG_RPDS_L 0x39 136 #define LPS25HB_REG_RPDS_H 0x3A 137 138 #if CONFIG_LPS25HB_SAMPLING_RATE == 1 139 #define LPS25HB_DEFAULT_SAMPLING_RATE 1 140 #elif CONFIG_LPS25HB_SAMPLING_RATE == 7 141 #define LPS25HB_DEFAULT_SAMPLING_RATE 2 142 #elif CONFIG_LPS25HB_SAMPLING_RATE == 13 143 #define LPS25HB_DEFAULT_SAMPLING_RATE 3 144 #elif CONFIG_LPS25HB_SAMPLING_RATE == 25 145 #define LPS25HB_DEFAULT_SAMPLING_RATE 4 146 #endif 147 148 149 struct lps25hb_config { 150 struct i2c_dt_spec i2c; 151 }; 152 153 struct lps25hb_data { 154 int32_t sample_press; 155 int16_t sample_temp; 156 }; 157 158 #endif /* ZEPHYR_DRIVERS_SENSOR_LPS25HB_LPS25HB_H_ */ 159
