1 /** 2 ****************************************************************************** 3 * @file lis3mdl_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis3mdl_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS3MDL_REGS_H 23 #define LIS3MDL_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS3MDL 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS3MDL_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0x39 if SA0=1 -> 0x3D **/ 172 #define LIS3MDL_I2C_ADD_L 0x39U 173 #define LIS3MDL_I2C_ADD_H 0x3DU 174 175 /** Device Identification (Who am I) **/ 176 #define LIS3MDL_ID 0x3DU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS3MDL_WHO_AM_I 0x0FU 184 #define LIS3MDL_CTRL_REG1 0x20U 185 typedef struct 186 { 187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 188 uint8_t st : 1; 189 uint8_t om : 6; /* om + do + fast_odr -> om */ 190 uint8_t temp_en : 1; 191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 192 uint8_t temp_en : 1; 193 uint8_t om : 6; /* om + do + fast_odr -> om */ 194 uint8_t st : 1; 195 #endif /* DRV_BYTE_ORDER */ 196 } lis3mdl_ctrl_reg1_t; 197 198 #define LIS3MDL_CTRL_REG2 0x21U 199 typedef struct 200 { 201 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 202 uint8_t not_used_01 : 2; 203 uint8_t soft_rst : 1; 204 uint8_t reboot : 1; 205 uint8_t not_used_02 : 1; 206 uint8_t fs : 2; 207 uint8_t not_used_03 : 1; 208 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 209 uint8_t not_used_03 : 1; 210 uint8_t fs : 2; 211 uint8_t not_used_02 : 1; 212 uint8_t reboot : 1; 213 uint8_t soft_rst : 1; 214 uint8_t not_used_01 : 2; 215 #endif /* DRV_BYTE_ORDER */ 216 } lis3mdl_ctrl_reg2_t; 217 218 #define LIS3MDL_CTRL_REG3 0x22U 219 typedef struct 220 { 221 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 222 uint8_t md : 2; 223 uint8_t sim : 1; 224 uint8_t not_used_01 : 2; 225 uint8_t lp : 1; 226 uint8_t not_used_02 : 2; 227 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 228 uint8_t not_used_02 : 2; 229 uint8_t lp : 1; 230 uint8_t not_used_01 : 2; 231 uint8_t sim : 1; 232 uint8_t md : 2; 233 #endif /* DRV_BYTE_ORDER */ 234 } lis3mdl_ctrl_reg3_t; 235 236 #define LIS3MDL_CTRL_REG4 0x23U 237 typedef struct 238 { 239 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 240 uint8_t not_used_01 : 1; 241 uint8_t ble : 1; 242 uint8_t omz : 2; 243 uint8_t not_used_02 : 4; 244 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 245 uint8_t not_used_02 : 4; 246 uint8_t omz : 2; 247 uint8_t ble : 1; 248 uint8_t not_used_01 : 1; 249 #endif /* DRV_BYTE_ORDER */ 250 } lis3mdl_ctrl_reg4_t; 251 252 #define LIS3MDL_CTRL_REG5 0x24U 253 typedef struct 254 { 255 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 256 uint8_t not_used_01 : 6; 257 uint8_t bdu : 1; 258 uint8_t fast_read : 1; 259 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 260 uint8_t fast_read : 1; 261 uint8_t bdu : 1; 262 uint8_t not_used_01 : 6; 263 #endif /* DRV_BYTE_ORDER */ 264 } lis3mdl_ctrl_reg5_t; 265 266 #define LIS3MDL_STATUS_REG 0x27U 267 typedef struct 268 { 269 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 270 uint8_t xda : 1; 271 uint8_t yda : 1; 272 uint8_t zda : 1; 273 uint8_t zyxda : 1; 274 uint8_t _xor : 1; 275 uint8_t yor : 1; 276 uint8_t zor : 1; 277 uint8_t zyxor : 1; 278 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 279 uint8_t zyxor : 1; 280 uint8_t zor : 1; 281 uint8_t yor : 1; 282 uint8_t _xor : 1; 283 uint8_t zyxda : 1; 284 uint8_t zda : 1; 285 uint8_t yda : 1; 286 uint8_t xda : 1; 287 #endif /* DRV_BYTE_ORDER */ 288 } lis3mdl_status_reg_t; 289 290 #define LIS3MDL_OUT_X_L 0x28U 291 #define LIS3MDL_OUT_X_H 0x29U 292 #define LIS3MDL_OUT_Y_L 0x2AU 293 #define LIS3MDL_OUT_Y_H 0x2BU 294 #define LIS3MDL_OUT_Z_L 0x2CU 295 #define LIS3MDL_OUT_Z_H 0x2DU 296 #define LIS3MDL_TEMP_OUT_L 0x2EU 297 #define LIS3MDL_TEMP_OUT_H 0x2FU 298 #define LIS3MDL_INT_CFG 0x30U 299 typedef struct 300 { 301 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 302 uint8_t ien : 1; 303 uint8_t lir : 1; 304 uint8_t iea : 1; 305 uint8_t not_used_01 : 2; 306 uint8_t zien : 1; 307 uint8_t yien : 1; 308 uint8_t xien : 1; 309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 310 uint8_t xien : 1; 311 uint8_t yien : 1; 312 uint8_t zien : 1; 313 uint8_t not_used_01 : 2; 314 uint8_t iea : 1; 315 uint8_t lir : 1; 316 uint8_t ien : 1; 317 #endif /* DRV_BYTE_ORDER */ 318 } lis3mdl_int_cfg_t; 319 320 #define LIS3MDL_INT_SRC 0x31U 321 typedef struct 322 { 323 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 324 uint8_t int_ : 1; 325 uint8_t mroi : 1; 326 uint8_t nth_z : 1; 327 uint8_t nth_y : 1; 328 uint8_t nth_x : 1; 329 uint8_t pth_z : 1; 330 uint8_t pth_y : 1; 331 uint8_t pth_x : 1; 332 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 333 uint8_t pth_x : 1; 334 uint8_t pth_y : 1; 335 uint8_t pth_z : 1; 336 uint8_t nth_x : 1; 337 uint8_t nth_y : 1; 338 uint8_t nth_z : 1; 339 uint8_t mroi : 1; 340 uint8_t int_ : 1; 341 #endif /* DRV_BYTE_ORDER */ 342 } lis3mdl_int_src_t; 343 344 #define LIS3MDL_INT_THS_L 0x32U 345 #define LIS3MDL_INT_THS_H 0x33U 346 347 /** 348 * @defgroup LIS3MDL_Register_Union 349 * @brief This union group all the registers having a bit-field 350 * description. 351 * This union is useful but it's not needed by the driver. 352 * 353 * REMOVING this union you are compliant with: 354 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 355 * 356 * @{ 357 * 358 */ 359 typedef union 360 { 361 lis3mdl_ctrl_reg1_t ctrl_reg1; 362 lis3mdl_ctrl_reg2_t ctrl_reg2; 363 lis3mdl_ctrl_reg3_t ctrl_reg3; 364 lis3mdl_ctrl_reg4_t ctrl_reg4; 365 lis3mdl_ctrl_reg5_t ctrl_reg5; 366 lis3mdl_status_reg_t status_reg; 367 lis3mdl_int_cfg_t int_cfg; 368 lis3mdl_int_src_t int_src; 369 bitwise_t bitwise; 370 uint8_t byte; 371 } lis3mdl_reg_t; 372 373 /** 374 * @} 375 * 376 */ 377 378 #ifndef __weak 379 #define __weak __attribute__((weak)) 380 #endif /* __weak */ 381 382 /* 383 * These are the basic platform dependent I/O routines to read 384 * and write device registers connected on a standard bus. 385 * The driver keeps offering a default implementation based on function 386 * pointers to read/write routines for backward compatibility. 387 * The __weak directive allows the final application to overwrite 388 * them with a custom implementation. 389 */ 390 391 int32_t lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 392 uint8_t *data, 393 uint16_t len); 394 int32_t lis3mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 395 uint8_t *data, 396 uint16_t len); 397 398 float_t lis3mdl_from_fs4_to_gauss(int16_t lsb); 399 float_t lis3mdl_from_fs8_to_gauss(int16_t lsb); 400 float_t lis3mdl_from_fs12_to_gauss(int16_t lsb); 401 float_t lis3mdl_from_fs16_to_gauss(int16_t lsb); 402 403 float_t lis3mdl_from_lsb_to_celsius(int16_t lsb); 404 405 typedef enum 406 { 407 LIS3MDL_LP_Hz625 = 0x00, 408 LIS3MDL_LP_1kHz = 0x01, 409 LIS3MDL_MP_560Hz = 0x11, 410 LIS3MDL_HP_300Hz = 0x21, 411 LIS3MDL_UHP_155Hz = 0x31, 412 413 LIS3MDL_LP_1Hz25 = 0x02, 414 LIS3MDL_LP_2Hz5 = 0x04, 415 LIS3MDL_LP_5Hz = 0x06, 416 LIS3MDL_LP_10Hz = 0x08, 417 LIS3MDL_LP_20Hz = 0x0A, 418 LIS3MDL_LP_40Hz = 0x0C, 419 LIS3MDL_LP_80Hz = 0x0E, 420 421 LIS3MDL_MP_1Hz25 = 0x12, 422 LIS3MDL_MP_2Hz5 = 0x14, 423 LIS3MDL_MP_5Hz = 0x16, 424 LIS3MDL_MP_10Hz = 0x18, 425 LIS3MDL_MP_20Hz = 0x1A, 426 LIS3MDL_MP_40Hz = 0x1C, 427 LIS3MDL_MP_80Hz = 0x1E, 428 429 LIS3MDL_HP_1Hz25 = 0x22, 430 LIS3MDL_HP_2Hz5 = 0x24, 431 LIS3MDL_HP_5Hz = 0x26, 432 LIS3MDL_HP_10Hz = 0x28, 433 LIS3MDL_HP_20Hz = 0x2A, 434 LIS3MDL_HP_40Hz = 0x2C, 435 LIS3MDL_HP_80Hz = 0x2E, 436 437 LIS3MDL_UHP_1Hz25 = 0x32, 438 LIS3MDL_UHP_2Hz5 = 0x34, 439 LIS3MDL_UHP_5Hz = 0x36, 440 LIS3MDL_UHP_10Hz = 0x38, 441 LIS3MDL_UHP_20Hz = 0x3A, 442 LIS3MDL_UHP_40Hz = 0x3C, 443 LIS3MDL_UHP_80Hz = 0x3E, 444 445 } lis3mdl_om_t; 446 int32_t lis3mdl_data_rate_set(stmdev_ctx_t *ctx, lis3mdl_om_t val); 447 int32_t lis3mdl_data_rate_get(stmdev_ctx_t *ctx, lis3mdl_om_t *val); 448 449 int32_t lis3mdl_temperature_meas_set(stmdev_ctx_t *ctx, uint8_t val); 450 int32_t lis3mdl_temperature_meas_get(stmdev_ctx_t *ctx, uint8_t *val); 451 452 typedef enum 453 { 454 LIS3MDL_4_GAUSS = 0, 455 LIS3MDL_8_GAUSS = 1, 456 LIS3MDL_12_GAUSS = 2, 457 LIS3MDL_16_GAUSS = 3, 458 } lis3mdl_fs_t; 459 int32_t lis3mdl_full_scale_set(stmdev_ctx_t *ctx, lis3mdl_fs_t val); 460 int32_t lis3mdl_full_scale_get(stmdev_ctx_t *ctx, lis3mdl_fs_t *val); 461 462 typedef enum 463 { 464 LIS3MDL_CONTINUOUS_MODE = 0, 465 LIS3MDL_SINGLE_TRIGGER = 1, 466 LIS3MDL_POWER_DOWN = 2, 467 } lis3mdl_md_t; 468 int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx, 469 lis3mdl_md_t val); 470 int32_t lis3mdl_operating_mode_get(stmdev_ctx_t *ctx, 471 lis3mdl_md_t *val); 472 473 int32_t lis3mdl_fast_low_power_set(stmdev_ctx_t *ctx, uint8_t val); 474 int32_t lis3mdl_fast_low_power_get(stmdev_ctx_t *ctx, uint8_t *val); 475 476 int32_t lis3mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 477 int32_t lis3mdl_block_data_update_get(stmdev_ctx_t *ctx, 478 uint8_t *val); 479 480 int32_t lis3mdl_high_part_cycle_set(stmdev_ctx_t *ctx, uint8_t val); 481 int32_t lis3mdl_high_part_cycle_get(stmdev_ctx_t *ctx, uint8_t *val); 482 483 int32_t lis3mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 484 485 int32_t lis3mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 486 487 int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val); 488 489 int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 490 491 int32_t lis3mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 492 493 int32_t lis3mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val); 494 int32_t lis3mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); 495 496 int32_t lis3mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val); 497 int32_t lis3mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 498 499 int32_t lis3mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val); 500 int32_t lis3mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 501 502 typedef enum 503 { 504 LIS3MDL_LSB_AT_LOW_ADD = 0, 505 LIS3MDL_MSB_AT_LOW_ADD = 1, 506 } lis3mdl_ble_t; 507 int32_t lis3mdl_data_format_set(stmdev_ctx_t *ctx, lis3mdl_ble_t val); 508 int32_t lis3mdl_data_format_get(stmdev_ctx_t *ctx, 509 lis3mdl_ble_t *val); 510 511 int32_t lis3mdl_status_get(stmdev_ctx_t *ctx, 512 lis3mdl_status_reg_t *val); 513 514 int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx, 515 lis3mdl_int_cfg_t *val); 516 int32_t lis3mdl_int_config_get(stmdev_ctx_t *ctx, 517 lis3mdl_int_cfg_t *val); 518 519 int32_t lis3mdl_int_generation_set(stmdev_ctx_t *ctx, uint8_t val); 520 int32_t lis3mdl_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val); 521 522 typedef enum 523 { 524 LIS3MDL_INT_PULSED = 0, 525 LIS3MDL_INT_LATCHED = 1, 526 } lis3mdl_lir_t; 527 int32_t lis3mdl_int_notification_mode_set(stmdev_ctx_t *ctx, 528 lis3mdl_lir_t val); 529 int32_t lis3mdl_int_notification_mode_get(stmdev_ctx_t *ctx, 530 lis3mdl_lir_t *val); 531 532 typedef enum 533 { 534 LIS3MDL_ACTIVE_HIGH = 0, 535 LIS3MDL_ACTIVE_LOW = 1, 536 } lis3mdl_iea_t; 537 int32_t lis3mdl_int_polarity_set(stmdev_ctx_t *ctx, 538 lis3mdl_iea_t val); 539 int32_t lis3mdl_int_polarity_get(stmdev_ctx_t *ctx, 540 lis3mdl_iea_t *val); 541 542 int32_t lis3mdl_int_on_z_ax_set(stmdev_ctx_t *ctx, uint8_t val); 543 int32_t lis3mdl_int_on_z_ax_get(stmdev_ctx_t *ctx, uint8_t *val); 544 545 int32_t lis3mdl_int_on_y_ax_set(stmdev_ctx_t *ctx, uint8_t val); 546 int32_t lis3mdl_int_on_y_ax_get(stmdev_ctx_t *ctx, uint8_t *val); 547 548 int32_t lis3mdl_int_on_x_ax_set(stmdev_ctx_t *ctx, uint8_t val); 549 int32_t lis3mdl_int_on_x_ax_get(stmdev_ctx_t *ctx, uint8_t *val); 550 551 int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx, 552 lis3mdl_int_src_t *val); 553 554 int32_t lis3mdl_interrupt_event_flag_get(stmdev_ctx_t *ctx, 555 uint8_t *val); 556 557 int32_t lis3mdl_int_mag_over_range_flag_get(stmdev_ctx_t *ctx, 558 uint8_t *val); 559 560 int32_t lis3mdl_int_neg_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 561 562 int32_t lis3mdl_int_neg_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 563 564 int32_t lis3mdl_int_neg_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 565 566 int32_t lis3mdl_int_pos_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 567 568 int32_t lis3mdl_int_pos_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 569 570 int32_t lis3mdl_int_pos_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 571 572 int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val); 573 int32_t lis3mdl_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); 574 575 typedef enum 576 { 577 LIS3MDL_SPI_4_WIRE = 0, 578 LIS3MDL_SPI_3_WIRE = 1, 579 } lis3mdl_sim_t; 580 int32_t lis3mdl_spi_mode_set(stmdev_ctx_t *ctx, lis3mdl_sim_t val); 581 int32_t lis3mdl_spi_mode_get(stmdev_ctx_t *ctx, lis3mdl_sim_t *val); 582 583 /** 584 *@} 585 * 586 */ 587 588 #ifdef __cplusplus 589 } 590 #endif 591 592 #endif /* LIS3MDL_REGS_H */ 593 594 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 595
