1 /**
2 ******************************************************************************
3 * @file lis2de12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DE12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2de12_reg.h"
21
22 /**
23 * @defgroup LIS2DE12
24 * @brief This file provides a set of functions needed to drive the
25 * lis2de12 enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DE12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2de12_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2de12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lis2de12_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lis2de12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LIS2DE12_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lis2de12_from_fs2_to_mg(int16_t lsb)103 float_t lis2de12_from_fs2_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb / 256.0f) * 15.6f;
106 }
107
lis2de12_from_fs4_to_mg(int16_t lsb)108 float_t lis2de12_from_fs4_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb / 256.0f) * 31.2f;
111 }
112
lis2de12_from_fs8_to_mg(int16_t lsb)113 float_t lis2de12_from_fs8_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb / 256.0f) * 62.5f;
116 }
117
lis2de12_from_fs16_to_mg(int16_t lsb)118 float_t lis2de12_from_fs16_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb / 256.0f) * 187.5f;
121 }
122
lis2de12_from_lsb_to_celsius(int16_t lsb)123 float_t lis2de12_from_lsb_to_celsius(int16_t lsb)
124 {
125 return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
126 }
127
128 /**
129 * @}
130 *
131 */
132
133 /**
134 * @defgroup LIS2DE12_Data_generation
135 * @brief This section group all the functions concerning data generation.
136 * @{
137 *
138 */
139
140 /**
141 * @brief Temperature status register.[get]
142 *
143 * @param ctx read / write interface definitions
144 * @param buff buffer that stores data read
145 * @retval interface status (MANDATORY: return 0 -> no Error)
146 *
147 */
lis2de12_temp_status_reg_get(const stmdev_ctx_t * ctx,uint8_t * buff)148 int32_t lis2de12_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff)
149 {
150 int32_t ret;
151
152 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX, buff, 1);
153
154 return ret;
155 }
156 /**
157 * @brief Temperature data available.[get]
158 *
159 * @param ctx read / write interface definitions
160 * @param val change the values of tda in reg STATUS_REG_AUX
161 * @retval interface status (MANDATORY: return 0 -> no Error)
162 *
163 */
lis2de12_temp_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)164 int32_t lis2de12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
165 {
166 lis2de12_status_reg_aux_t status_reg_aux;
167 int32_t ret;
168
169 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX,
170 (uint8_t *)&status_reg_aux, 1);
171 *val = status_reg_aux.tda;
172
173 return ret;
174 }
175 /**
176 * @brief Temperature data overrun.[get]
177 *
178 * @param ctx read / write interface definitions
179 * @param val change the values of tor in reg STATUS_REG_AUX
180 * @retval interface status (MANDATORY: return 0 -> no Error)
181 *
182 */
lis2de12_temp_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)183 int32_t lis2de12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
184 {
185 lis2de12_status_reg_aux_t status_reg_aux;
186 int32_t ret;
187
188 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX,
189 (uint8_t *)&status_reg_aux, 1);
190 *val = status_reg_aux.tor;
191
192 return ret;
193 }
194 /**
195 * @brief Temperature output value.[get]
196 *
197 * @param ctx read / write interface definitions
198 * @param buff buffer that stores data read
199 * @retval interface status (MANDATORY: return 0 -> no Error)
200 *
201 */
lis2de12_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)202 int32_t lis2de12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
203 {
204 uint8_t buff[2];
205 int32_t ret;
206
207 ret = lis2de12_read_reg(ctx, LIS2DE12_OUT_TEMP_L, buff, 2);
208 *val = (int16_t)buff[1];
209 *val = (*val * 256) + (int16_t)buff[0];
210
211 return ret;
212 }
213 /**
214 * @brief Temperature sensor enable.[set]
215 *
216 * @param ctx read / write interface definitions
217 * @param val change the values of temp_en in reg TEMP_CFG_REG
218 * @retval interface status (MANDATORY: return 0 -> no Error)
219 *
220 */
lis2de12_temperature_meas_set(const stmdev_ctx_t * ctx,lis2de12_temp_en_t val)221 int32_t lis2de12_temperature_meas_set(const stmdev_ctx_t *ctx,
222 lis2de12_temp_en_t val)
223 {
224 lis2de12_temp_cfg_reg_t temp_cfg_reg;
225 int32_t ret;
226
227 ret = lis2de12_read_reg(ctx, LIS2DE12_TEMP_CFG_REG,
228 (uint8_t *)&temp_cfg_reg, 1);
229
230 if (ret == 0)
231 {
232 temp_cfg_reg.temp_en = (uint8_t) val;
233 ret = lis2de12_write_reg(ctx, LIS2DE12_TEMP_CFG_REG,
234 (uint8_t *)&temp_cfg_reg, 1);
235 }
236
237 return ret;
238 }
239
240 /**
241 * @brief Temperature sensor enable.[get]
242 *
243 * @param ctx read / write interface definitions
244 * @param val get the values of temp_en in reg TEMP_CFG_REG
245 * @retval interface status (MANDATORY: return 0 -> no Error)
246 *
247 */
lis2de12_temperature_meas_get(const stmdev_ctx_t * ctx,lis2de12_temp_en_t * val)248 int32_t lis2de12_temperature_meas_get(const stmdev_ctx_t *ctx,
249 lis2de12_temp_en_t *val)
250 {
251 lis2de12_temp_cfg_reg_t temp_cfg_reg;
252 int32_t ret;
253
254 ret = lis2de12_read_reg(ctx, LIS2DE12_TEMP_CFG_REG,
255 (uint8_t *)&temp_cfg_reg, 1);
256
257 switch (temp_cfg_reg.temp_en)
258 {
259 case LIS2DE12_TEMP_DISABLE:
260 *val = LIS2DE12_TEMP_DISABLE;
261 break;
262
263 case LIS2DE12_TEMP_ENABLE:
264 *val = LIS2DE12_TEMP_ENABLE;
265 break;
266
267 default:
268 *val = LIS2DE12_TEMP_DISABLE;
269 break;
270 }
271
272 return ret;
273 }
274
275 /**
276 * @brief Output data rate selection.[set]
277 *
278 * @param ctx read / write interface definitions
279 * @param val change the values of odr in reg CTRL_REG1
280 * @retval interface status (MANDATORY: return 0 -> no Error)
281 *
282 */
lis2de12_data_rate_set(const stmdev_ctx_t * ctx,lis2de12_odr_t val)283 int32_t lis2de12_data_rate_set(const stmdev_ctx_t *ctx, lis2de12_odr_t val)
284 {
285 lis2de12_ctrl_reg1_t ctrl_reg1;
286 int32_t ret;
287
288 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG1,
289 (uint8_t *)&ctrl_reg1, 1);
290
291 if (ret == 0)
292 {
293 ctrl_reg1.lpen = PROPERTY_ENABLE;
294 ctrl_reg1.odr = (uint8_t)val;
295 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG1,
296 (uint8_t *)&ctrl_reg1, 1);
297 }
298
299 return ret;
300 }
301
302 /**
303 * @brief Output data rate selection.[get]
304 *
305 * @param ctx read / write interface definitions
306 * @param val get the values of odr in reg CTRL_REG1
307 * @retval interface status (MANDATORY: return 0 -> no Error)
308 *
309 */
lis2de12_data_rate_get(const stmdev_ctx_t * ctx,lis2de12_odr_t * val)310 int32_t lis2de12_data_rate_get(const stmdev_ctx_t *ctx, lis2de12_odr_t *val)
311 {
312 lis2de12_ctrl_reg1_t ctrl_reg1;
313 int32_t ret;
314
315 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG1,
316 (uint8_t *)&ctrl_reg1, 1);
317
318 switch (ctrl_reg1.odr)
319 {
320 case LIS2DE12_POWER_DOWN:
321 *val = LIS2DE12_POWER_DOWN;
322 break;
323
324 case LIS2DE12_ODR_1Hz:
325 *val = LIS2DE12_ODR_1Hz;
326 break;
327
328 case LIS2DE12_ODR_10Hz:
329 *val = LIS2DE12_ODR_10Hz;
330 break;
331
332 case LIS2DE12_ODR_25Hz:
333 *val = LIS2DE12_ODR_25Hz;
334 break;
335
336 case LIS2DE12_ODR_50Hz:
337 *val = LIS2DE12_ODR_50Hz;
338 break;
339
340 case LIS2DE12_ODR_100Hz:
341 *val = LIS2DE12_ODR_100Hz;
342 break;
343
344 case LIS2DE12_ODR_200Hz:
345 *val = LIS2DE12_ODR_200Hz;
346 break;
347
348 case LIS2DE12_ODR_400Hz:
349 *val = LIS2DE12_ODR_400Hz;
350 break;
351
352 case LIS2DE12_ODR_1kHz620_LP:
353 *val = LIS2DE12_ODR_1kHz620_LP;
354 break;
355
356 case LIS2DE12_ODR_5kHz376_LP_1kHz344_NM_HP:
357 *val = LIS2DE12_ODR_5kHz376_LP_1kHz344_NM_HP;
358 break;
359
360 default:
361 *val = LIS2DE12_POWER_DOWN;
362 break;
363 }
364
365 return ret;
366 }
367
368 /**
369 * @brief High pass data from internal filter sent to output register
370 * and FIFO.
371 *
372 * @param ctx read / write interface definitions
373 * @param val change the values of fds in reg CTRL_REG2
374 * @retval interface status (MANDATORY: return 0 -> no Error)
375 *
376 */
lis2de12_high_pass_on_outputs_set(const stmdev_ctx_t * ctx,uint8_t val)377 int32_t lis2de12_high_pass_on_outputs_set(const stmdev_ctx_t *ctx,
378 uint8_t val)
379 {
380 lis2de12_ctrl_reg2_t ctrl_reg2;
381 int32_t ret;
382
383 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
384 (uint8_t *)&ctrl_reg2, 1);
385
386 if (ret == 0)
387 {
388 ctrl_reg2.fds = val;
389 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
390 (uint8_t *)&ctrl_reg2, 1);
391 }
392
393 return ret;
394 }
395
396 /**
397 * @brief High pass data from internal filter sent to output register
398 * and FIFO.[get]
399 *
400 * @param ctx read / write interface definitions
401 * @param val change the values of fds in reg CTRL_REG2
402 * @retval interface status (MANDATORY: return 0 -> no Error)
403 *
404 */
lis2de12_high_pass_on_outputs_get(const stmdev_ctx_t * ctx,uint8_t * val)405 int32_t lis2de12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx,
406 uint8_t *val)
407 {
408 lis2de12_ctrl_reg2_t ctrl_reg2;
409 int32_t ret;
410
411 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
412 (uint8_t *)&ctrl_reg2, 1);
413 *val = (uint8_t)ctrl_reg2.fds;
414
415 return ret;
416 }
417
418 /**
419 * @brief High-pass filter cutoff frequency selection.[set]
420 *
421 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
422 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
423 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
424 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
425 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
426 *
427 * @param ctx read / write interface definitions
428 * @param val change the values of hpcf in reg CTRL_REG2
429 * @retval interface status (MANDATORY: return 0 -> no Error)
430 *
431 */
lis2de12_high_pass_bandwidth_set(const stmdev_ctx_t * ctx,lis2de12_hpcf_t val)432 int32_t lis2de12_high_pass_bandwidth_set(const stmdev_ctx_t *ctx,
433 lis2de12_hpcf_t val)
434 {
435 lis2de12_ctrl_reg2_t ctrl_reg2;
436 int32_t ret;
437
438 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
439 (uint8_t *)&ctrl_reg2, 1);
440
441 if (ret == 0)
442 {
443 ctrl_reg2.hpcf = (uint8_t)val;
444 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
445 (uint8_t *)&ctrl_reg2, 1);
446 }
447
448 return ret;
449 }
450
451 /**
452 * @brief High-pass filter cutoff frequency selection.[get]
453 *
454 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
455 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
456 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
457 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
458 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
459 *
460 * @param ctx read / write interface definitions
461 * @param val get the values of hpcf in reg CTRL_REG2
462 * @retval interface status (MANDATORY: return 0 -> no Error)
463 *
464 */
lis2de12_high_pass_bandwidth_get(const stmdev_ctx_t * ctx,lis2de12_hpcf_t * val)465 int32_t lis2de12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx,
466 lis2de12_hpcf_t *val)
467 {
468 lis2de12_ctrl_reg2_t ctrl_reg2;
469 int32_t ret;
470
471 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
472 (uint8_t *)&ctrl_reg2, 1);
473
474 switch (ctrl_reg2.hpcf)
475 {
476 case LIS2DE12_AGGRESSIVE:
477 *val = LIS2DE12_AGGRESSIVE;
478 break;
479
480 case LIS2DE12_STRONG:
481 *val = LIS2DE12_STRONG;
482 break;
483
484 case LIS2DE12_MEDIUM:
485 *val = LIS2DE12_MEDIUM;
486 break;
487
488 case LIS2DE12_LIGHT:
489 *val = LIS2DE12_LIGHT;
490 break;
491
492 default:
493 *val = LIS2DE12_LIGHT;
494 break;
495 }
496
497 return ret;
498 }
499
500 /**
501 * @brief High-pass filter mode selection.[set]
502 *
503 * @param ctx read / write interface definitions
504 * @param val change the values of hpm in reg CTRL_REG2
505 * @retval interface status (MANDATORY: return 0 -> no Error)
506 *
507 */
lis2de12_high_pass_mode_set(const stmdev_ctx_t * ctx,lis2de12_hpm_t val)508 int32_t lis2de12_high_pass_mode_set(const stmdev_ctx_t *ctx,
509 lis2de12_hpm_t val)
510 {
511 lis2de12_ctrl_reg2_t ctrl_reg2;
512 int32_t ret;
513
514 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
515 (uint8_t *)&ctrl_reg2, 1);
516
517 if (ret == 0)
518 {
519 ctrl_reg2.hpm = (uint8_t)val;
520 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
521 (uint8_t *)&ctrl_reg2, 1);
522 }
523
524 return ret;
525 }
526
527 /**
528 * @brief High-pass filter mode selection.[get]
529 *
530 * @param ctx read / write interface definitions
531 * @param val get the values of hpm in reg CTRL_REG2
532 * @retval interface status (MANDATORY: return 0 -> no Error)
533 *
534 */
lis2de12_high_pass_mode_get(const stmdev_ctx_t * ctx,lis2de12_hpm_t * val)535 int32_t lis2de12_high_pass_mode_get(const stmdev_ctx_t *ctx,
536 lis2de12_hpm_t *val)
537 {
538 lis2de12_ctrl_reg2_t ctrl_reg2;
539 int32_t ret;
540
541 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
542 (uint8_t *)&ctrl_reg2, 1);
543
544 switch (ctrl_reg2.hpm)
545 {
546 case LIS2DE12_NORMAL_WITH_RST:
547 *val = LIS2DE12_NORMAL_WITH_RST;
548 break;
549
550 case LIS2DE12_REFERENCE_MODE:
551 *val = LIS2DE12_REFERENCE_MODE;
552 break;
553
554 case LIS2DE12_NORMAL:
555 *val = LIS2DE12_NORMAL;
556 break;
557
558 case LIS2DE12_AUTORST_ON_INT:
559 *val = LIS2DE12_AUTORST_ON_INT;
560 break;
561
562 default:
563 *val = LIS2DE12_NORMAL_WITH_RST;
564 break;
565 }
566
567 return ret;
568 }
569
570 /**
571 * @brief Full-scale configuration.[set]
572 *
573 * @param ctx read / write interface definitions
574 * @param val change the values of fs in reg CTRL_REG4
575 * @retval interface status (MANDATORY: return 0 -> no Error)
576 *
577 */
lis2de12_full_scale_set(const stmdev_ctx_t * ctx,lis2de12_fs_t val)578 int32_t lis2de12_full_scale_set(const stmdev_ctx_t *ctx, lis2de12_fs_t val)
579 {
580 lis2de12_ctrl_reg4_t ctrl_reg4;
581 int32_t ret;
582
583 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
584 (uint8_t *)&ctrl_reg4, 1);
585
586 if (ret == 0)
587 {
588 ctrl_reg4.fs = (uint8_t)val;
589 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
590 (uint8_t *)&ctrl_reg4, 1);
591 }
592
593 return ret;
594 }
595
596 /**
597 * @brief Full-scale configuration.[get]
598 *
599 * @param ctx read / write interface definitions
600 * @param val get the values of fs in reg CTRL_REG4
601 * @retval interface status (MANDATORY: return 0 -> no Error)
602 *
603 */
lis2de12_full_scale_get(const stmdev_ctx_t * ctx,lis2de12_fs_t * val)604 int32_t lis2de12_full_scale_get(const stmdev_ctx_t *ctx, lis2de12_fs_t *val)
605 {
606 lis2de12_ctrl_reg4_t ctrl_reg4;
607 int32_t ret;
608
609 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
610 (uint8_t *)&ctrl_reg4, 1);
611
612 switch (ctrl_reg4.fs)
613 {
614 case LIS2DE12_2g:
615 *val = LIS2DE12_2g;
616 break;
617
618 case LIS2DE12_4g:
619 *val = LIS2DE12_4g;
620 break;
621
622 case LIS2DE12_8g:
623 *val = LIS2DE12_8g;
624 break;
625
626 case LIS2DE12_16g:
627 *val = LIS2DE12_16g;
628 break;
629
630 default:
631 *val = LIS2DE12_2g;
632 break;
633 }
634
635 return ret;
636 }
637
638 /**
639 * @brief Block Data Update.[set]
640 *
641 * @param ctx read / write interface definitions
642 * @param val change the values of bdu in reg CTRL_REG4
643 * @retval interface status (MANDATORY: return 0 -> no Error)
644 *
645 */
lis2de12_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)646 int32_t lis2de12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
647 {
648 lis2de12_ctrl_reg4_t ctrl_reg4;
649 int32_t ret;
650
651 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
652 (uint8_t *)&ctrl_reg4, 1);
653
654 if (ret == 0)
655 {
656 ctrl_reg4.bdu = val;
657 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
658 (uint8_t *)&ctrl_reg4, 1);
659 }
660
661 return ret;
662 }
663
664 /**
665 * @brief Block Data Update.[get]
666 *
667 * @param ctx read / write interface definitions
668 * @param val change the values of bdu in reg CTRL_REG4
669 * @retval interface status (MANDATORY: return 0 -> no Error)
670 *
671 */
lis2de12_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)672 int32_t lis2de12_block_data_update_get(const stmdev_ctx_t *ctx,
673 uint8_t *val)
674 {
675 lis2de12_ctrl_reg4_t ctrl_reg4;
676 int32_t ret;
677
678 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
679 (uint8_t *)&ctrl_reg4, 1);
680 *val = (uint8_t)ctrl_reg4.bdu;
681
682 return ret;
683 }
684
685 /**
686 * @brief Reference value for interrupt generation.[set]
687 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
688 *
689 * @param ctx read / write interface definitions
690 * @param buff buffer that contains data to write
691 * @retval interface status (MANDATORY: return 0 -> no Error)
692 *
693 */
lis2de12_filter_reference_set(const stmdev_ctx_t * ctx,uint8_t * buff)694 int32_t lis2de12_filter_reference_set(const stmdev_ctx_t *ctx,
695 uint8_t *buff)
696 {
697 int32_t ret;
698
699 ret = lis2de12_write_reg(ctx, LIS2DE12_REFERENCE, buff, 1);
700
701 return ret;
702 }
703
704 /**
705 * @brief Reference value for interrupt generation.[get]
706 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
707 *
708 * @param ctx read / write interface definitions
709 * @param buff buffer that stores data read
710 * @retval interface status (MANDATORY: return 0 -> no Error)
711 *
712 */
lis2de12_filter_reference_get(const stmdev_ctx_t * ctx,uint8_t * buff)713 int32_t lis2de12_filter_reference_get(const stmdev_ctx_t *ctx,
714 uint8_t *buff)
715 {
716 int32_t ret;
717
718 ret = lis2de12_read_reg(ctx, LIS2DE12_REFERENCE, buff, 1);
719
720 return ret;
721 }
722 /**
723 * @brief Acceleration set of data available.[get]
724 *
725 * @param ctx read / write interface definitions
726 * @param val change the values of zyxda in reg STATUS_REG
727 * @retval interface status (MANDATORY: return 0 -> no Error)
728 *
729 */
lis2de12_xl_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)730 int32_t lis2de12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
731 {
732 lis2de12_status_reg_t status_reg;
733 int32_t ret;
734
735 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG,
736 (uint8_t *)&status_reg, 1);
737 *val = status_reg.zyxda;
738
739 return ret;
740 }
741 /**
742 * @brief Acceleration set of data overrun.[get]
743 *
744 * @param ctx read / write interface definitions
745 * @param val change the values of zyxor in reg STATUS_REG
746 * @retval interface status (MANDATORY: return 0 -> no Error)
747 *
748 */
lis2de12_xl_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)749 int32_t lis2de12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
750 {
751 lis2de12_status_reg_t status_reg;
752 int32_t ret;
753
754 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG,
755 (uint8_t *)&status_reg, 1);
756 *val = status_reg.zyxor;
757
758 return ret;
759 }
760 /**
761 * @brief Acceleration output value.[get]
762 *
763 * @param ctx read / write interface definitions
764 * @param buff buffer that stores data read
765 * @retval interface status (MANDATORY: return 0 -> no Error)
766 *
767 */
lis2de12_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)768 int32_t lis2de12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
769 {
770 uint8_t buff[6];
771 int32_t ret;
772
773 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_READ_START, buff, 6);
774 val[0] = (int16_t)buff[1];
775 val[0] = (val[0] * 256) + (int16_t)buff[0];
776 val[1] = (int16_t)buff[3];
777 val[1] = (val[1] * 256) + (int16_t)buff[2];
778 val[2] = (int16_t)buff[5];
779 val[2] = (val[2] * 256) + (int16_t)buff[4];
780
781 return ret;
782 }
783 /**
784 * @}
785 *
786 */
787
788 /**
789 * @defgroup LIS2DE12_Common
790 * @brief This section group common useful functions
791 * @{
792 *
793 */
794
795 /**
796 * @brief DeviceWhoamI .[get]
797 *
798 * @param ctx read / write interface definitions
799 * @param buff buffer that stores data read
800 * @retval interface status (MANDATORY: return 0 -> no Error)
801 *
802 */
lis2de12_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)803 int32_t lis2de12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
804 {
805 int32_t ret;
806
807 ret = lis2de12_read_reg(ctx, LIS2DE12_WHO_AM_I, buff, 1);
808
809 return ret;
810 }
811 /**
812 * @brief Self Test.[set]
813 *
814 * @param ctx read / write interface definitions
815 * @param val change the values of st in reg CTRL_REG4
816 * @retval interface status (MANDATORY: return 0 -> no Error)
817 *
818 */
lis2de12_self_test_set(const stmdev_ctx_t * ctx,lis2de12_st_t val)819 int32_t lis2de12_self_test_set(const stmdev_ctx_t *ctx, lis2de12_st_t val)
820 {
821 lis2de12_ctrl_reg4_t ctrl_reg4;
822 int32_t ret;
823
824 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
825 (uint8_t *)&ctrl_reg4, 1);
826
827 if (ret == 0)
828 {
829 ctrl_reg4.st = (uint8_t)val;
830 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
831 (uint8_t *)&ctrl_reg4, 1);
832 }
833
834 return ret;
835 }
836
837 /**
838 * @brief Self Test.[get]
839 *
840 * @param ctx read / write interface definitions
841 * @param val Get the values of st in reg CTRL_REG4
842 * @retval interface status (MANDATORY: return 0 -> no Error)
843 *
844 */
lis2de12_self_test_get(const stmdev_ctx_t * ctx,lis2de12_st_t * val)845 int32_t lis2de12_self_test_get(const stmdev_ctx_t *ctx, lis2de12_st_t *val)
846 {
847 lis2de12_ctrl_reg4_t ctrl_reg4;
848 int32_t ret;
849
850 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
851 (uint8_t *)&ctrl_reg4, 1);
852
853 switch (ctrl_reg4.st)
854 {
855 case LIS2DE12_ST_DISABLE:
856 *val = LIS2DE12_ST_DISABLE;
857 break;
858
859 case LIS2DE12_ST_POSITIVE:
860 *val = LIS2DE12_ST_POSITIVE;
861 break;
862
863 case LIS2DE12_ST_NEGATIVE:
864 *val = LIS2DE12_ST_NEGATIVE;
865 break;
866
867 default:
868 *val = LIS2DE12_ST_DISABLE;
869 break;
870 }
871
872 return ret;
873 }
874
875 /**
876 * @brief Reboot memory content. Reload the calibration parameters.[set]
877 *
878 * @param ctx read / write interface definitions
879 * @param val change the values of boot in reg CTRL_REG5
880 * @retval interface status (MANDATORY: return 0 -> no Error)
881 *
882 */
lis2de12_boot_set(const stmdev_ctx_t * ctx,uint8_t val)883 int32_t lis2de12_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
884 {
885 lis2de12_ctrl_reg5_t ctrl_reg5;
886 int32_t ret;
887
888 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
889 (uint8_t *)&ctrl_reg5, 1);
890
891 if (ret == 0)
892 {
893 ctrl_reg5.boot = val;
894 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
895 (uint8_t *)&ctrl_reg5, 1);
896 }
897
898 return ret;
899 }
900
901 /**
902 * @brief Reboot memory content. Reload the calibration parameters.[get]
903 *
904 * @param ctx read / write interface definitions
905 * @param val change the values of boot in reg CTRL_REG5
906 * @retval interface status (MANDATORY: return 0 -> no Error)
907 *
908 */
lis2de12_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)909 int32_t lis2de12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
910 {
911 lis2de12_ctrl_reg5_t ctrl_reg5;
912 int32_t ret;
913
914 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
915 (uint8_t *)&ctrl_reg5, 1);
916 *val = (uint8_t)ctrl_reg5.boot;
917
918 return ret;
919 }
920
921 /**
922 * @brief Info about device status.[get]
923 *
924 * @param ctx read / write interface definitions
925 * @param val register STATUS_REG
926 * @retval interface status (MANDATORY: return 0 -> no Error)
927 *
928 */
lis2de12_status_get(const stmdev_ctx_t * ctx,lis2de12_status_reg_t * val)929 int32_t lis2de12_status_get(const stmdev_ctx_t *ctx,
930 lis2de12_status_reg_t *val)
931 {
932 int32_t ret;
933
934 ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG, (uint8_t *) val, 1);
935
936 return ret;
937 }
938 /**
939 * @}
940 *
941 */
942
943 /**
944 * @defgroup LIS2DE12_Interrupts_generator_1
945 * @brief This section group all the functions that manage the first
946 * interrupts generator
947 * @{
948 *
949 */
950
951 /**
952 * @brief Interrupt generator 1 configuration register.[set]
953 *
954 * @param ctx read / write interface definitions
955 * @param val register INT1_CFG
956 * @retval interface status (MANDATORY: return 0 -> no Error)
957 *
958 */
lis2de12_int1_gen_conf_set(const stmdev_ctx_t * ctx,lis2de12_int1_cfg_t * val)959 int32_t lis2de12_int1_gen_conf_set(const stmdev_ctx_t *ctx,
960 lis2de12_int1_cfg_t *val)
961 {
962 int32_t ret;
963
964 ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_CFG, (uint8_t *) val, 1);
965
966 return ret;
967 }
968
969 /**
970 * @brief Interrupt generator 1 configuration register.[get]
971 *
972 * @param ctx read / write interface definitions
973 * @param val register INT1_CFG
974 * @retval interface status (MANDATORY: return 0 -> no Error)
975 *
976 */
lis2de12_int1_gen_conf_get(const stmdev_ctx_t * ctx,lis2de12_int1_cfg_t * val)977 int32_t lis2de12_int1_gen_conf_get(const stmdev_ctx_t *ctx,
978 lis2de12_int1_cfg_t *val)
979 {
980 int32_t ret;
981
982 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_CFG, (uint8_t *) val, 1);
983
984 return ret;
985 }
986
987 /**
988 * @brief Interrupt generator 1 source register.[get]
989 *
990 * @param ctx read / write interface definitions
991 * @param val Registers INT1_SRC
992 * @retval interface status (MANDATORY: return 0 -> no Error)
993 *
994 */
lis2de12_int1_gen_source_get(const stmdev_ctx_t * ctx,lis2de12_int1_src_t * val)995 int32_t lis2de12_int1_gen_source_get(const stmdev_ctx_t *ctx,
996 lis2de12_int1_src_t *val)
997 {
998 int32_t ret;
999
1000 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_SRC, (uint8_t *) val, 1);
1001
1002 return ret;
1003 }
1004 /**
1005 * @brief User-defined threshold value for xl interrupt event on
1006 * generator 1.[set]
1007 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1008 *
1009 * @param ctx read / write interface definitions
1010 * @param val change the values of ths in reg INT1_THS
1011 * @retval interface status (MANDATORY: return 0 -> no Error)
1012 *
1013 */
lis2de12_int1_gen_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1014 int32_t lis2de12_int1_gen_threshold_set(const stmdev_ctx_t *ctx,
1015 uint8_t val)
1016 {
1017 lis2de12_int1_ths_t int1_ths;
1018 int32_t ret;
1019
1020 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1);
1021
1022 if (ret == 0)
1023 {
1024 int1_ths.ths = val;
1025 ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1);
1026 }
1027
1028 return ret;
1029 }
1030
1031 /**
1032 * @brief User-defined threshold value for xl interrupt event on
1033 * generator 1.[get]
1034 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1035 *
1036 * @param ctx read / write interface definitions
1037 * @param val change the values of ths in reg INT1_THS
1038 * @retval interface status (MANDATORY: return 0 -> no Error)
1039 *
1040 */
lis2de12_int1_gen_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1041 int32_t lis2de12_int1_gen_threshold_get(const stmdev_ctx_t *ctx,
1042 uint8_t *val)
1043 {
1044 lis2de12_int1_ths_t int1_ths;
1045 int32_t ret;
1046
1047 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1);
1048 *val = (uint8_t)int1_ths.ths;
1049
1050 return ret;
1051 }
1052
1053 /**
1054 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1055 * recognized.[set]
1056 *
1057 * @param ctx read / write interface definitions
1058 * @param val change the values of d in reg INT1_DURATION
1059 * @retval interface status (MANDATORY: return 0 -> no Error)
1060 *
1061 */
lis2de12_int1_gen_duration_set(const stmdev_ctx_t * ctx,uint8_t val)1062 int32_t lis2de12_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
1063 {
1064 lis2de12_int1_duration_t int1_duration;
1065 int32_t ret;
1066
1067 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_DURATION,
1068 (uint8_t *)&int1_duration, 1);
1069
1070 if (ret == 0)
1071 {
1072 int1_duration.d = val;
1073 ret = lis2de12_write_reg(ctx, LIS2DE12_INT1_DURATION,
1074 (uint8_t *)&int1_duration, 1);
1075 }
1076
1077 return ret;
1078 }
1079
1080 /**
1081 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1082 * recognized.[get]
1083 *
1084 * @param ctx read / write interface definitions
1085 * @param val change the values of d in reg INT1_DURATION
1086 * @retval interface status (MANDATORY: return 0 -> no Error)
1087 *
1088 */
lis2de12_int1_gen_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)1089 int32_t lis2de12_int1_gen_duration_get(const stmdev_ctx_t *ctx,
1090 uint8_t *val)
1091 {
1092 lis2de12_int1_duration_t int1_duration;
1093 int32_t ret;
1094
1095 ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_DURATION,
1096 (uint8_t *)&int1_duration, 1);
1097 *val = (uint8_t)int1_duration.d;
1098
1099 return ret;
1100 }
1101
1102 /**
1103 * @}
1104 *
1105 */
1106
1107 /**
1108 * @defgroup LIS2DE12_Interrupts_generator_2
1109 * @brief This section group all the functions that manage the second
1110 * interrupts generator
1111 * @{
1112 *
1113 */
1114
1115 /**
1116 * @brief Interrupt generator 2 configuration register.[set]
1117 *
1118 * @param ctx read / write interface definitions
1119 * @param val registers INT2_CFG
1120 * @retval interface status (MANDATORY: return 0 -> no Error)
1121 *
1122 */
lis2de12_int2_gen_conf_set(const stmdev_ctx_t * ctx,lis2de12_int2_cfg_t * val)1123 int32_t lis2de12_int2_gen_conf_set(const stmdev_ctx_t *ctx,
1124 lis2de12_int2_cfg_t *val)
1125 {
1126 int32_t ret;
1127
1128 ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_CFG, (uint8_t *) val, 1);
1129
1130 return ret;
1131 }
1132
1133 /**
1134 * @brief Interrupt generator 2 configuration register.[get]
1135 *
1136 * @param ctx read / write interface definitions
1137 * @param val registers INT2_CFG
1138 * @retval interface status (MANDATORY: return 0 -> no Error)
1139 *
1140 */
lis2de12_int2_gen_conf_get(const stmdev_ctx_t * ctx,lis2de12_int2_cfg_t * val)1141 int32_t lis2de12_int2_gen_conf_get(const stmdev_ctx_t *ctx,
1142 lis2de12_int2_cfg_t *val)
1143 {
1144 int32_t ret;
1145
1146 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_CFG, (uint8_t *) val, 1);
1147
1148 return ret;
1149 }
1150 /**
1151 * @brief Interrupt generator 2 source register.[get]
1152 *
1153 * @param ctx read / write interface definitions
1154 * @param val registers INT2_SRC
1155 * @retval interface status (MANDATORY: return 0 -> no Error)
1156 *
1157 */
lis2de12_int2_gen_source_get(const stmdev_ctx_t * ctx,lis2de12_int2_src_t * val)1158 int32_t lis2de12_int2_gen_source_get(const stmdev_ctx_t *ctx,
1159 lis2de12_int2_src_t *val)
1160 {
1161 int32_t ret;
1162
1163 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_SRC, (uint8_t *) val, 1);
1164
1165 return ret;
1166 }
1167 /**
1168 * @brief User-defined threshold value for xl interrupt event on
1169 * generator 2.[set]
1170 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1171 *
1172 * @param ctx read / write interface definitions
1173 * @param val change the values of ths in reg INT2_THS
1174 * @retval interface status (MANDATORY: return 0 -> no Error)
1175 *
1176 */
lis2de12_int2_gen_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1177 int32_t lis2de12_int2_gen_threshold_set(const stmdev_ctx_t *ctx,
1178 uint8_t val)
1179 {
1180 lis2de12_int2_ths_t int2_ths;
1181 int32_t ret;
1182
1183 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1);
1184
1185 if (ret == 0)
1186 {
1187 int2_ths.ths = val;
1188 ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1);
1189 }
1190
1191 return ret;
1192 }
1193
1194 /**
1195 * @brief User-defined threshold value for xl interrupt event on
1196 * generator 2.[get]
1197 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1198 *
1199 * @param ctx read / write interface definitions
1200 * @param val change the values of ths in reg INT2_THS
1201 * @retval interface status (MANDATORY: return 0 -> no Error)
1202 *
1203 */
lis2de12_int2_gen_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1204 int32_t lis2de12_int2_gen_threshold_get(const stmdev_ctx_t *ctx,
1205 uint8_t *val)
1206 {
1207 lis2de12_int2_ths_t int2_ths;
1208 int32_t ret;
1209
1210 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1);
1211 *val = (uint8_t)int2_ths.ths;
1212
1213 return ret;
1214 }
1215
1216 /**
1217 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1218 * recognized .[set]
1219 *
1220 * @param ctx read / write interface definitions
1221 * @param val change the values of d in reg INT2_DURATION
1222 * @retval interface status (MANDATORY: return 0 -> no Error)
1223 *
1224 */
lis2de12_int2_gen_duration_set(const stmdev_ctx_t * ctx,uint8_t val)1225 int32_t lis2de12_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
1226 {
1227 lis2de12_int2_duration_t int2_duration;
1228 int32_t ret;
1229
1230 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_DURATION,
1231 (uint8_t *)&int2_duration, 1);
1232
1233 if (ret == 0)
1234 {
1235 int2_duration.d = val;
1236 ret = lis2de12_write_reg(ctx, LIS2DE12_INT2_DURATION,
1237 (uint8_t *)&int2_duration, 1);
1238 }
1239
1240 return ret;
1241 }
1242
1243 /**
1244 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1245 * recognized.[get]
1246 *
1247 * @param ctx read / write interface definitions
1248 * @param val change the values of d in reg INT2_DURATION
1249 * @retval interface status (MANDATORY: return 0 -> no Error)
1250 *
1251 */
lis2de12_int2_gen_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)1252 int32_t lis2de12_int2_gen_duration_get(const stmdev_ctx_t *ctx,
1253 uint8_t *val)
1254 {
1255 lis2de12_int2_duration_t int2_duration;
1256 int32_t ret;
1257
1258 ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_DURATION,
1259 (uint8_t *)&int2_duration, 1);
1260 *val = (uint8_t)int2_duration.d;
1261
1262 return ret;
1263 }
1264
1265 /**
1266 * @}
1267 *
1268 */
1269
1270 /**
1271 * @defgroup LIS2DE12_Interrupt_pins
1272 * @brief This section group all the functions that manage interrupt pins
1273 * @{
1274 *
1275 */
1276
1277 /**
1278 * @brief High-pass filter on interrupts/tap generator.[set]
1279 *
1280 * @param ctx read / write interface definitions
1281 * @param val change the values of hp in reg CTRL_REG2
1282 * @retval interface status (MANDATORY: return 0 -> no Error)
1283 *
1284 */
lis2de12_high_pass_int_conf_set(const stmdev_ctx_t * ctx,lis2de12_hp_t val)1285 int32_t lis2de12_high_pass_int_conf_set(const stmdev_ctx_t *ctx,
1286 lis2de12_hp_t val)
1287 {
1288 lis2de12_ctrl_reg2_t ctrl_reg2;
1289 int32_t ret;
1290
1291 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
1292 (uint8_t *)&ctrl_reg2, 1);
1293
1294 if (ret == 0)
1295 {
1296 ctrl_reg2.hp = (uint8_t)val;
1297 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG2,
1298 (uint8_t *)&ctrl_reg2, 1);
1299 }
1300
1301 return ret;
1302 }
1303
1304 /**
1305 * @brief High-pass filter on interrupts/tap generator.[get]
1306 *
1307 * @param ctx read / write interface definitions
1308 * @param val Get the values of hp in reg CTRL_REG2
1309 * @retval interface status (MANDATORY: return 0 -> no Error)
1310 *
1311 */
lis2de12_high_pass_int_conf_get(const stmdev_ctx_t * ctx,lis2de12_hp_t * val)1312 int32_t lis2de12_high_pass_int_conf_get(const stmdev_ctx_t *ctx,
1313 lis2de12_hp_t *val)
1314 {
1315 lis2de12_ctrl_reg2_t ctrl_reg2;
1316 int32_t ret;
1317
1318 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2,
1319 (uint8_t *)&ctrl_reg2, 1);
1320
1321 switch (ctrl_reg2.hp)
1322 {
1323 case LIS2DE12_DISC_FROM_INT_GENERATOR:
1324 *val = LIS2DE12_DISC_FROM_INT_GENERATOR;
1325 break;
1326
1327 case LIS2DE12_ON_INT1_GEN:
1328 *val = LIS2DE12_ON_INT1_GEN;
1329 break;
1330
1331 case LIS2DE12_ON_INT2_GEN:
1332 *val = LIS2DE12_ON_INT2_GEN;
1333 break;
1334
1335 case LIS2DE12_ON_TAP_GEN:
1336 *val = LIS2DE12_ON_TAP_GEN;
1337 break;
1338
1339 case LIS2DE12_ON_INT1_INT2_GEN:
1340 *val = LIS2DE12_ON_INT1_INT2_GEN;
1341 break;
1342
1343 case LIS2DE12_ON_INT1_TAP_GEN:
1344 *val = LIS2DE12_ON_INT1_TAP_GEN;
1345 break;
1346
1347 case LIS2DE12_ON_INT2_TAP_GEN:
1348 *val = LIS2DE12_ON_INT2_TAP_GEN;
1349 break;
1350
1351 case LIS2DE12_ON_INT1_INT2_TAP_GEN:
1352 *val = LIS2DE12_ON_INT1_INT2_TAP_GEN;
1353 break;
1354
1355 default:
1356 *val = LIS2DE12_DISC_FROM_INT_GENERATOR;
1357 break;
1358 }
1359
1360 return ret;
1361 }
1362
1363 /**
1364 * @brief Int1 pin routing configuration register.[set]
1365 *
1366 * @param ctx read / write interface definitions
1367 * @param val registers CTRL_REG3
1368 * @retval interface status (MANDATORY: return 0 -> no Error)
1369 *
1370 */
lis2de12_pin_int1_config_set(const stmdev_ctx_t * ctx,lis2de12_ctrl_reg3_t * val)1371 int32_t lis2de12_pin_int1_config_set(const stmdev_ctx_t *ctx,
1372 lis2de12_ctrl_reg3_t *val)
1373 {
1374 int32_t ret;
1375
1376 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG3, (uint8_t *) val, 1);
1377
1378 return ret;
1379 }
1380
1381 /**
1382 * @brief Int1 pin routing configuration register.[get]
1383 *
1384 * @param ctx read / write interface definitions
1385 * @param val registers CTRL_REG3
1386 * @retval interface status (MANDATORY: return 0 -> no Error)
1387 *
1388 */
lis2de12_pin_int1_config_get(const stmdev_ctx_t * ctx,lis2de12_ctrl_reg3_t * val)1389 int32_t lis2de12_pin_int1_config_get(const stmdev_ctx_t *ctx,
1390 lis2de12_ctrl_reg3_t *val)
1391 {
1392 int32_t ret;
1393
1394 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG3, (uint8_t *) val, 1);
1395
1396 return ret;
1397 }
1398 /**
1399 * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled
1400 * on INT2 pin when 6D bit on
1401 * INT2_CFG (34h) is set to 1.
1402 *
1403 * @param ctx read / write interface definitions
1404 * @param val change the values of d4d_int2 in reg CTRL_REG5
1405 * @retval interface status (MANDATORY: return 0 -> no Error)
1406 *
1407 */
lis2de12_int2_pin_detect_4d_set(const stmdev_ctx_t * ctx,uint8_t val)1408 int32_t lis2de12_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx,
1409 uint8_t val)
1410 {
1411 lis2de12_ctrl_reg5_t ctrl_reg5;
1412 int32_t ret;
1413
1414 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1415 (uint8_t *)&ctrl_reg5, 1);
1416
1417 if (ret == 0)
1418 {
1419 ctrl_reg5.d4d_int2 = val;
1420 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1421 (uint8_t *)&ctrl_reg5, 1);
1422 }
1423
1424 return ret;
1425 }
1426
1427 /**
1428 * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on
1429 * INT2_CFG (34h) is set to 1.[get]
1430 *
1431 * @param ctx read / write interface definitions
1432 * @param val change the values of d4d_int2 in reg CTRL_REG5
1433 * @retval interface status (MANDATORY: return 0 -> no Error)
1434 *
1435 */
lis2de12_int2_pin_detect_4d_get(const stmdev_ctx_t * ctx,uint8_t * val)1436 int32_t lis2de12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx,
1437 uint8_t *val)
1438 {
1439 lis2de12_ctrl_reg5_t ctrl_reg5;
1440 int32_t ret;
1441
1442 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1443 (uint8_t *)&ctrl_reg5, 1);
1444 *val = (uint8_t)ctrl_reg5.d4d_int2;
1445
1446 return ret;
1447 }
1448
1449 /**
1450 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1451 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1452 * itself.[set]
1453 *
1454 * @param ctx read / write interface definitions
1455 * @param val change the values of lir_int2 in reg CTRL_REG5
1456 * @retval interface status (MANDATORY: return 0 -> no Error)
1457 *
1458 */
lis2de12_int2_pin_notification_mode_set(const stmdev_ctx_t * ctx,lis2de12_lir_int2_t val)1459 int32_t lis2de12_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx,
1460 lis2de12_lir_int2_t val)
1461 {
1462 lis2de12_ctrl_reg5_t ctrl_reg5;
1463 int32_t ret;
1464
1465 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1466 (uint8_t *)&ctrl_reg5, 1);
1467
1468 if (ret == 0)
1469 {
1470 ctrl_reg5.lir_int2 = (uint8_t)val;
1471 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1472 (uint8_t *)&ctrl_reg5, 1);
1473 }
1474
1475 return ret;
1476 }
1477
1478 /**
1479 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1480 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1481 * itself.[get]
1482 *
1483 * @param ctx read / write interface definitions
1484 * @param val Get the values of lir_int2 in reg CTRL_REG5
1485 * @retval interface status (MANDATORY: return 0 -> no Error)
1486 *
1487 */
lis2de12_int2_pin_notification_mode_get(const stmdev_ctx_t * ctx,lis2de12_lir_int2_t * val)1488 int32_t lis2de12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx,
1489 lis2de12_lir_int2_t *val)
1490 {
1491 lis2de12_ctrl_reg5_t ctrl_reg5;
1492 int32_t ret;
1493
1494 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1495 (uint8_t *)&ctrl_reg5, 1);
1496
1497 switch (ctrl_reg5.lir_int2)
1498 {
1499 case LIS2DE12_INT2_PULSED:
1500 *val = LIS2DE12_INT2_PULSED;
1501 break;
1502
1503 case LIS2DE12_INT2_LATCHED:
1504 *val = LIS2DE12_INT2_LATCHED;
1505 break;
1506
1507 default:
1508 *val = LIS2DE12_INT2_PULSED;
1509 break;
1510 }
1511
1512 return ret;
1513 }
1514
1515 /**
1516 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit
1517 * on INT1_CFG(30h) is set to 1.[set]
1518 *
1519 * @param ctx read / write interface definitions
1520 * @param val change the values of d4d_int1 in reg CTRL_REG5
1521 * @retval interface status (MANDATORY: return 0 -> no Error)
1522 *
1523 */
lis2de12_int1_pin_detect_4d_set(const stmdev_ctx_t * ctx,uint8_t val)1524 int32_t lis2de12_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx,
1525 uint8_t val)
1526 {
1527 lis2de12_ctrl_reg5_t ctrl_reg5;
1528 int32_t ret;
1529
1530 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1531 (uint8_t *)&ctrl_reg5, 1);
1532
1533 if (ret == 0)
1534 {
1535 ctrl_reg5.d4d_int1 = val;
1536 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1537 (uint8_t *)&ctrl_reg5, 1);
1538 }
1539
1540 return ret;
1541 }
1542
1543 /**
1544 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on
1545 * INT1_CFG(30h) is set to 1.[get]
1546 *
1547 * @param ctx read / write interface definitions
1548 * @param val change the values of d4d_int1 in reg CTRL_REG5
1549 * @retval interface status (MANDATORY: return 0 -> no Error)
1550 *
1551 */
lis2de12_int1_pin_detect_4d_get(const stmdev_ctx_t * ctx,uint8_t * val)1552 int32_t lis2de12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx,
1553 uint8_t *val)
1554 {
1555 lis2de12_ctrl_reg5_t ctrl_reg5;
1556 int32_t ret;
1557
1558 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1559 (uint8_t *)&ctrl_reg5, 1);
1560 *val = (uint8_t)ctrl_reg5.d4d_int1;
1561
1562 return ret;
1563 }
1564
1565 /**
1566 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1567 * register cleared by reading INT1_SRC (31h) itself.[set]
1568 *
1569 * @param ctx read / write interface definitions
1570 * @param val change the values of lir_int1 in reg CTRL_REG5
1571 * @retval interface status (MANDATORY: return 0 -> no Error)
1572 *
1573 */
lis2de12_int1_pin_notification_mode_set(const stmdev_ctx_t * ctx,lis2de12_lir_int1_t val)1574 int32_t lis2de12_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx,
1575 lis2de12_lir_int1_t val)
1576 {
1577 lis2de12_ctrl_reg5_t ctrl_reg5;
1578 int32_t ret;
1579
1580 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1581 (uint8_t *)&ctrl_reg5, 1);
1582
1583 if (ret == 0)
1584 {
1585 ctrl_reg5.lir_int1 = (uint8_t)val;
1586 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1587 (uint8_t *)&ctrl_reg5, 1);
1588 }
1589
1590 return ret;
1591 }
1592
1593 /**
1594 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1595 * register cleared by reading INT1_SRC (31h) itself.[get]
1596 *
1597 * @param ctx read / write interface definitions
1598 * @param val Get the values of lir_int1 in reg CTRL_REG5
1599 * @retval interface status (MANDATORY: return 0 -> no Error)
1600 *
1601 */
lis2de12_int1_pin_notification_mode_get(const stmdev_ctx_t * ctx,lis2de12_lir_int1_t * val)1602 int32_t lis2de12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx,
1603 lis2de12_lir_int1_t *val)
1604 {
1605 lis2de12_ctrl_reg5_t ctrl_reg5;
1606 int32_t ret;
1607
1608 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1609 (uint8_t *)&ctrl_reg5, 1);
1610
1611 switch (ctrl_reg5.lir_int1)
1612 {
1613 case LIS2DE12_INT1_PULSED:
1614 *val = LIS2DE12_INT1_PULSED;
1615 break;
1616
1617 case LIS2DE12_INT1_LATCHED:
1618 *val = LIS2DE12_INT1_LATCHED;
1619 break;
1620
1621 default:
1622 *val = LIS2DE12_INT1_PULSED;
1623 break;
1624 }
1625
1626 return ret;
1627 }
1628
1629 /**
1630 * @brief Int2 pin routing configuration register.[set]
1631 *
1632 * @param ctx read / write interface definitions
1633 * @param val registers CTRL_REG6
1634 * @retval interface status (MANDATORY: return 0 -> no Error)
1635 *
1636 */
lis2de12_pin_int2_config_set(const stmdev_ctx_t * ctx,lis2de12_ctrl_reg6_t * val)1637 int32_t lis2de12_pin_int2_config_set(const stmdev_ctx_t *ctx,
1638 lis2de12_ctrl_reg6_t *val)
1639 {
1640 int32_t ret;
1641
1642 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG6, (uint8_t *) val, 1);
1643
1644 return ret;
1645 }
1646
1647 /**
1648 * @brief Int2 pin routing configuration register.[get]
1649 *
1650 * @param ctx read / write interface definitions
1651 * @param val registers CTRL_REG6
1652 * @retval interface status (MANDATORY: return 0 -> no Error)
1653 *
1654 */
lis2de12_pin_int2_config_get(const stmdev_ctx_t * ctx,lis2de12_ctrl_reg6_t * val)1655 int32_t lis2de12_pin_int2_config_get(const stmdev_ctx_t *ctx,
1656 lis2de12_ctrl_reg6_t *val)
1657 {
1658 int32_t ret;
1659
1660 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG6, (uint8_t *) val, 1);
1661
1662 return ret;
1663 }
1664 /**
1665 * @}
1666 *
1667 */
1668
1669 /**
1670 * @defgroup LIS2DE12_Fifo
1671 * @brief This section group all the functions concerning the fifo usage
1672 * @{
1673 *
1674 */
1675
1676 /**
1677 * @brief FIFO enable.[set]
1678 *
1679 * @param ctx read / write interface definitions
1680 * @param val change the values of fifo_en in reg CTRL_REG5
1681 * @retval interface status (MANDATORY: return 0 -> no Error)
1682 *
1683 */
lis2de12_fifo_set(const stmdev_ctx_t * ctx,uint8_t val)1684 int32_t lis2de12_fifo_set(const stmdev_ctx_t *ctx, uint8_t val)
1685 {
1686 lis2de12_ctrl_reg5_t ctrl_reg5;
1687 int32_t ret;
1688
1689 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1690 (uint8_t *)&ctrl_reg5, 1);
1691
1692 if (ret == 0)
1693 {
1694 ctrl_reg5.fifo_en = val;
1695 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG5,
1696 (uint8_t *)&ctrl_reg5, 1);
1697 }
1698
1699 return ret;
1700 }
1701
1702 /**
1703 * @brief FIFO enable.[get]
1704 *
1705 * @param ctx read / write interface definitions
1706 * @param val change the values of fifo_en in reg CTRL_REG5
1707 * @retval interface status (MANDATORY: return 0 -> no Error)
1708 *
1709 */
lis2de12_fifo_get(const stmdev_ctx_t * ctx,uint8_t * val)1710 int32_t lis2de12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val)
1711 {
1712 lis2de12_ctrl_reg5_t ctrl_reg5;
1713 int32_t ret;
1714
1715 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5,
1716 (uint8_t *)&ctrl_reg5, 1);
1717 *val = (uint8_t)ctrl_reg5.fifo_en;
1718
1719 return ret;
1720 }
1721
1722 /**
1723 * @brief FIFO watermark level selection.[set]
1724 *
1725 * @param ctx read / write interface definitions
1726 * @param val change the values of fth in reg FIFO_CTRL_REG
1727 * @retval interface status (MANDATORY: return 0 -> no Error)
1728 *
1729 */
lis2de12_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1730 int32_t lis2de12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1731 {
1732 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1733 int32_t ret;
1734
1735 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1736 (uint8_t *)&fifo_ctrl_reg, 1);
1737
1738 if (ret == 0)
1739 {
1740 fifo_ctrl_reg.fth = val;
1741 ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1742 (uint8_t *)&fifo_ctrl_reg, 1);
1743 }
1744
1745 return ret;
1746 }
1747
1748 /**
1749 * @brief FIFO watermark level selection.[get]
1750 *
1751 * @param ctx read / write interface definitions
1752 * @param val change the values of fth in reg FIFO_CTRL_REG
1753 * @retval interface status (MANDATORY: return 0 -> no Error)
1754 *
1755 */
lis2de12_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1756 int32_t lis2de12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1757 {
1758 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1759 int32_t ret;
1760
1761 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1762 (uint8_t *)&fifo_ctrl_reg, 1);
1763 *val = (uint8_t)fifo_ctrl_reg.fth;
1764
1765 return ret;
1766 }
1767
1768 /**
1769 * @brief Trigger FIFO selection.[set]
1770 *
1771 * @param ctx read / write interface definitions
1772 * @param val change the values of tr in reg FIFO_CTRL_REG
1773 * @retval interface status (MANDATORY: return 0 -> no Error)
1774 *
1775 */
lis2de12_fifo_trigger_event_set(const stmdev_ctx_t * ctx,lis2de12_tr_t val)1776 int32_t lis2de12_fifo_trigger_event_set(const stmdev_ctx_t *ctx,
1777 lis2de12_tr_t val)
1778 {
1779 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1780 int32_t ret;
1781
1782 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1783 (uint8_t *)&fifo_ctrl_reg, 1);
1784
1785 if (ret == 0)
1786 {
1787 fifo_ctrl_reg.tr = (uint8_t)val;
1788 ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1789 (uint8_t *)&fifo_ctrl_reg, 1);
1790 }
1791
1792 return ret;
1793 }
1794
1795 /**
1796 * @brief Trigger FIFO selection.[get]
1797 *
1798 * @param ctx read / write interface definitions
1799 * @param val Get the values of tr in reg FIFO_CTRL_REG
1800 * @retval interface status (MANDATORY: return 0 -> no Error)
1801 *
1802 */
lis2de12_fifo_trigger_event_get(const stmdev_ctx_t * ctx,lis2de12_tr_t * val)1803 int32_t lis2de12_fifo_trigger_event_get(const stmdev_ctx_t *ctx,
1804 lis2de12_tr_t *val)
1805 {
1806 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1807 int32_t ret;
1808
1809 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1810 (uint8_t *)&fifo_ctrl_reg, 1);
1811
1812 switch (fifo_ctrl_reg.tr)
1813 {
1814 case LIS2DE12_INT1_GEN:
1815 *val = LIS2DE12_INT1_GEN;
1816 break;
1817
1818 case LIS2DE12_INT2_GEN:
1819 *val = LIS2DE12_INT2_GEN;
1820 break;
1821
1822 default:
1823 *val = LIS2DE12_INT1_GEN;
1824 break;
1825 }
1826
1827 return ret;
1828 }
1829
1830 /**
1831 * @brief FIFO mode selection.[set]
1832 *
1833 * @param ctx read / write interface definitions
1834 * @param val change the values of fm in reg FIFO_CTRL_REG
1835 * @retval interface status (MANDATORY: return 0 -> no Error)
1836 *
1837 */
lis2de12_fifo_mode_set(const stmdev_ctx_t * ctx,lis2de12_fm_t val)1838 int32_t lis2de12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2de12_fm_t val)
1839 {
1840 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1841 int32_t ret;
1842
1843 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1844 (uint8_t *)&fifo_ctrl_reg, 1);
1845
1846 if (ret == 0)
1847 {
1848 fifo_ctrl_reg.fm = (uint8_t)val;
1849 ret = lis2de12_write_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1850 (uint8_t *)&fifo_ctrl_reg, 1);
1851 }
1852
1853 return ret;
1854 }
1855
1856 /**
1857 * @brief FIFO mode selection.[get]
1858 *
1859 * @param ctx read / write interface definitions
1860 * @param val Get the values of fm in reg FIFO_CTRL_REG
1861 * @retval interface status (MANDATORY: return 0 -> no Error)
1862 *
1863 */
lis2de12_fifo_mode_get(const stmdev_ctx_t * ctx,lis2de12_fm_t * val)1864 int32_t lis2de12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2de12_fm_t *val)
1865 {
1866 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg;
1867 int32_t ret;
1868
1869 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG,
1870 (uint8_t *)&fifo_ctrl_reg, 1);
1871
1872 switch (fifo_ctrl_reg.fm)
1873 {
1874 case LIS2DE12_BYPASS_MODE:
1875 *val = LIS2DE12_BYPASS_MODE;
1876 break;
1877
1878 case LIS2DE12_FIFO_MODE:
1879 *val = LIS2DE12_FIFO_MODE;
1880 break;
1881
1882 case LIS2DE12_DYNAMIC_STREAM_MODE:
1883 *val = LIS2DE12_DYNAMIC_STREAM_MODE;
1884 break;
1885
1886 case LIS2DE12_STREAM_TO_FIFO_MODE:
1887 *val = LIS2DE12_STREAM_TO_FIFO_MODE;
1888 break;
1889
1890 default:
1891 *val = LIS2DE12_BYPASS_MODE;
1892 break;
1893 }
1894
1895 return ret;
1896 }
1897
1898 /**
1899 * @brief FIFO status register.[get]
1900 *
1901 * @param ctx read / write interface definitions
1902 * @param val registers FIFO_SRC_REG
1903 * @retval interface status (MANDATORY: return 0 -> no Error)
1904 *
1905 */
lis2de12_fifo_status_get(const stmdev_ctx_t * ctx,lis2de12_fifo_src_reg_t * val)1906 int32_t lis2de12_fifo_status_get(const stmdev_ctx_t *ctx,
1907 lis2de12_fifo_src_reg_t *val)
1908 {
1909 int32_t ret;
1910
1911 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t *) val, 1);
1912
1913 return ret;
1914 }
1915 /**
1916 * @brief FIFO stored data level.[get]
1917 *
1918 * @param ctx read / write interface definitions
1919 * @param val change the values of fss in reg FIFO_SRC_REG
1920 * @retval interface status (MANDATORY: return 0 -> no Error)
1921 *
1922 */
lis2de12_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)1923 int32_t lis2de12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
1924 {
1925 lis2de12_fifo_src_reg_t fifo_src_reg;
1926 int32_t ret;
1927
1928 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
1929 (uint8_t *)&fifo_src_reg, 1);
1930 *val = (uint8_t)fifo_src_reg.fss;
1931
1932 return ret;
1933 }
1934 /**
1935 * @brief Empty FIFO status flag.[get]
1936 *
1937 * @param ctx read / write interface definitions
1938 * @param val change the values of empty in reg FIFO_SRC_REG
1939 * @retval interface status (MANDATORY: return 0 -> no Error)
1940 *
1941 */
lis2de12_fifo_empty_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1942 int32_t lis2de12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1943 {
1944 lis2de12_fifo_src_reg_t fifo_src_reg;
1945 int32_t ret;
1946
1947 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
1948 (uint8_t *)&fifo_src_reg, 1);
1949 *val = (uint8_t)fifo_src_reg.empty;
1950
1951 return ret;
1952 }
1953 /**
1954 * @brief FIFO overrun status flag.[get]
1955 *
1956 * @param ctx read / write interface definitions
1957 * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG
1958 * @retval interface status (MANDATORY: return 0 -> no Error)
1959 *
1960 */
lis2de12_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1961 int32_t lis2de12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1962 {
1963 lis2de12_fifo_src_reg_t fifo_src_reg;
1964 int32_t ret;
1965
1966 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
1967 (uint8_t *)&fifo_src_reg, 1);
1968 *val = (uint8_t)fifo_src_reg.ovrn_fifo;
1969
1970 return ret;
1971 }
1972 /**
1973 * @brief FIFO watermark status.[get]
1974 *
1975 * @param ctx read / write interface definitions
1976 * @param val change the values of wtm in reg FIFO_SRC_REG
1977 * @retval interface status (MANDATORY: return 0 -> no Error)
1978 *
1979 */
lis2de12_fifo_fth_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1980 int32_t lis2de12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1981 {
1982 lis2de12_fifo_src_reg_t fifo_src_reg;
1983 int32_t ret;
1984
1985 ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG,
1986 (uint8_t *)&fifo_src_reg, 1);
1987 *val = (uint8_t)fifo_src_reg.wtm;
1988
1989 return ret;
1990 }
1991 /**
1992 * @}
1993 *
1994 */
1995
1996 /**
1997 * @defgroup LIS2DE12_Tap_generator
1998 * @brief This section group all the functions that manage the tap and
1999 * double tap event generation
2000 * @{
2001 *
2002 */
2003
2004 /**
2005 * @brief Tap/Double Tap generator configuration register.[set]
2006 *
2007 * @param ctx read / write interface definitions
2008 * @param val registers CLICK_CFG
2009 * @retval interface status (MANDATORY: return 0 -> no Error)
2010 *
2011 */
lis2de12_tap_conf_set(const stmdev_ctx_t * ctx,lis2de12_click_cfg_t * val)2012 int32_t lis2de12_tap_conf_set(const stmdev_ctx_t *ctx,
2013 lis2de12_click_cfg_t *val)
2014 {
2015 int32_t ret;
2016
2017 ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_CFG, (uint8_t *) val, 1);
2018
2019 return ret;
2020 }
2021
2022 /**
2023 * @brief Tap/Double Tap generator configuration register.[get]
2024 *
2025 * @param ctx read / write interface definitions
2026 * @param val registers CLICK_CFG
2027 * @retval interface status (MANDATORY: return 0 -> no Error)
2028 *
2029 */
lis2de12_tap_conf_get(const stmdev_ctx_t * ctx,lis2de12_click_cfg_t * val)2030 int32_t lis2de12_tap_conf_get(const stmdev_ctx_t *ctx,
2031 lis2de12_click_cfg_t *val)
2032 {
2033 int32_t ret;
2034
2035 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_CFG, (uint8_t *) val, 1);
2036
2037 return ret;
2038 }
2039 /**
2040 * @brief Tap/Double Tap generator source register.[get]
2041 *
2042 * @param ctx read / write interface definitions
2043 * @param val registers CLICK_SRC
2044 * @retval interface status (MANDATORY: return 0 -> no Error)
2045 *
2046 */
lis2de12_tap_source_get(const stmdev_ctx_t * ctx,lis2de12_click_src_t * val)2047 int32_t lis2de12_tap_source_get(const stmdev_ctx_t *ctx,
2048 lis2de12_click_src_t *val)
2049 {
2050 int32_t ret;
2051
2052 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_SRC, (uint8_t *) val, 1);
2053
2054 return ret;
2055 }
2056 /**
2057 * @brief User-defined threshold value for Tap/Double Tap event.[set]
2058 * 1 LSB = full scale/128
2059 *
2060 * @param ctx read / write interface definitions
2061 * @param val change the values of ths in reg CLICK_THS
2062 * @retval interface status (MANDATORY: return 0 -> no Error)
2063 *
2064 */
lis2de12_tap_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2065 int32_t lis2de12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2066 {
2067 lis2de12_click_ths_t click_ths;
2068 int32_t ret;
2069
2070 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
2071 (uint8_t *)&click_ths, 1);
2072
2073 if (ret == 0)
2074 {
2075 click_ths.ths = val;
2076 ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_THS,
2077 (uint8_t *)&click_ths, 1);
2078 }
2079
2080 return ret;
2081 }
2082
2083 /**
2084 * @brief User-defined threshold value for Tap/Double Tap event.[get]
2085 * 1 LSB = full scale/128
2086 *
2087 * @param ctx read / write interface definitions
2088 * @param val change the values of ths in reg CLICK_THS
2089 * @retval interface status (MANDATORY: return 0 -> no Error)
2090 *
2091 */
lis2de12_tap_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2092 int32_t lis2de12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2093 {
2094 lis2de12_click_ths_t click_ths;
2095 int32_t ret;
2096
2097 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
2098 (uint8_t *)&click_ths, 1);
2099 *val = (uint8_t)click_ths.ths;
2100
2101 return ret;
2102 }
2103
2104 /**
2105 * @brief If the LIR_Click bit is not set, the interrupt is kept high
2106 * for the duration of the latency window.
2107 * If the LIR_Click bit is set, the interrupt is kept high until the
2108 * CLICK_SRC(39h) register is read.[set]
2109 *
2110 * @param ctx read / write interface definitions
2111 * @param val change the values of lir_click in reg CLICK_THS
2112 * @retval interface status (MANDATORY: return 0 -> no Error)
2113 *
2114 */
lis2de12_tap_notification_mode_set(const stmdev_ctx_t * ctx,lis2de12_lir_click_t val)2115 int32_t lis2de12_tap_notification_mode_set(const stmdev_ctx_t *ctx,
2116 lis2de12_lir_click_t val)
2117 {
2118 lis2de12_click_ths_t click_ths;
2119 int32_t ret;
2120
2121 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
2122 (uint8_t *)&click_ths, 1);
2123
2124 if (ret == 0)
2125 {
2126 click_ths.lir_click = (uint8_t)val;
2127 ret = lis2de12_write_reg(ctx, LIS2DE12_CLICK_THS,
2128 (uint8_t *)&click_ths, 1);
2129 }
2130
2131 return ret;
2132 }
2133
2134 /**
2135 * @brief If the LIR_Click bit is not set, the interrupt is kept high
2136 * for the duration of the latency window.
2137 * If the LIR_Click bit is set, the interrupt is kept high until the
2138 * CLICK_SRC(39h) register is read.[get]
2139 *
2140 * @param ctx read / write interface definitions
2141 * @param val Get the values of lir_click in reg CLICK_THS
2142 * @retval interface status (MANDATORY: return 0 -> no Error)
2143 *
2144 */
lis2de12_tap_notification_mode_get(const stmdev_ctx_t * ctx,lis2de12_lir_click_t * val)2145 int32_t lis2de12_tap_notification_mode_get(const stmdev_ctx_t *ctx,
2146 lis2de12_lir_click_t *val)
2147 {
2148 lis2de12_click_ths_t click_ths;
2149 int32_t ret;
2150
2151 ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS,
2152 (uint8_t *)&click_ths, 1);
2153
2154 switch (click_ths.lir_click)
2155 {
2156 case LIS2DE12_TAP_PULSED:
2157 *val = LIS2DE12_TAP_PULSED;
2158 break;
2159
2160 case LIS2DE12_TAP_LATCHED:
2161 *val = LIS2DE12_TAP_LATCHED;
2162 break;
2163
2164 default:
2165 *val = LIS2DE12_TAP_PULSED;
2166 break;
2167 }
2168
2169 return ret;
2170 }
2171
2172 /**
2173 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse
2174 * between the start of the click-detection procedure and when the
2175 * acceleration falls back below the threshold.[set]
2176 *
2177 * @param ctx read / write interface definitions
2178 * @param val change the values of tli in reg TIME_LIMIT
2179 * @retval interface status (MANDATORY: return 0 -> no Error)
2180 *
2181 */
lis2de12_shock_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2182 int32_t lis2de12_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2183 {
2184 lis2de12_time_limit_t time_limit;
2185 int32_t ret;
2186
2187 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LIMIT,
2188 (uint8_t *)&time_limit, 1);
2189
2190 if (ret == 0)
2191 {
2192 time_limit.tli = val;
2193 ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_LIMIT,
2194 (uint8_t *)&time_limit, 1);
2195 }
2196
2197 return ret;
2198 }
2199
2200 /**
2201 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between
2202 * the start of the click-detection procedure and when the
2203 * acceleration falls back below the threshold.[get]
2204 *
2205 * @param ctx read / write interface definitions
2206 * @param val change the values of tli in reg TIME_LIMIT
2207 * @retval interface status (MANDATORY: return 0 -> no Error)
2208 *
2209 */
lis2de12_shock_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2210 int32_t lis2de12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2211 {
2212 lis2de12_time_limit_t time_limit;
2213 int32_t ret;
2214
2215 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LIMIT,
2216 (uint8_t *)&time_limit, 1);
2217 *val = (uint8_t)time_limit.tli;
2218
2219 return ret;
2220 }
2221
2222 /**
2223 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2224 * click detection where the click-detection procedure is
2225 * disabled, in cases where the device is configured for
2226 * double-click detection.[set]
2227 *
2228 * @param ctx read / write interface definitions
2229 * @param val change the values of tla in reg TIME_LATENCY
2230 * @retval interface status (MANDATORY: return 0 -> no Error)
2231 *
2232 */
lis2de12_quiet_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2233 int32_t lis2de12_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2234 {
2235 lis2de12_time_latency_t time_latency;
2236 int32_t ret;
2237
2238 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LATENCY,
2239 (uint8_t *)&time_latency, 1);
2240
2241 if (ret == 0)
2242 {
2243 time_latency.tla = val;
2244 ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_LATENCY,
2245 (uint8_t *)&time_latency, 1);
2246 }
2247
2248 return ret;
2249 }
2250
2251 /**
2252 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2253 * click detection where the click-detection procedure is
2254 * disabled, in cases where the device is configured for
2255 * double-click detection.[get]
2256 *
2257 * @param ctx read / write interface definitions
2258 * @param val change the values of tla in reg TIME_LATENCY
2259 * @retval interface status (MANDATORY: return 0 -> no Error)
2260 *
2261 */
lis2de12_quiet_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2262 int32_t lis2de12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2263 {
2264 lis2de12_time_latency_t time_latency;
2265 int32_t ret;
2266
2267 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LATENCY,
2268 (uint8_t *)&time_latency, 1);
2269 *val = (uint8_t)time_latency.tla;
2270
2271 return ret;
2272 }
2273
2274 /**
2275 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2276 * after the end of the latency interval in which the click-detection
2277 * procedure can start, in cases where the device is configured
2278 * for double-click detection.[set]
2279 *
2280 * @param ctx read / write interface definitions
2281 * @param val change the values of tw in reg TIME_WINDOW
2282 * @retval interface status (MANDATORY: return 0 -> no Error)
2283 *
2284 */
lis2de12_double_tap_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)2285 int32_t lis2de12_double_tap_timeout_set(const stmdev_ctx_t *ctx,
2286 uint8_t val)
2287 {
2288 lis2de12_time_window_t time_window;
2289 int32_t ret;
2290
2291 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_WINDOW,
2292 (uint8_t *)&time_window, 1);
2293
2294 if (ret == 0)
2295 {
2296 time_window.tw = val;
2297 ret = lis2de12_write_reg(ctx, LIS2DE12_TIME_WINDOW,
2298 (uint8_t *)&time_window, 1);
2299 }
2300
2301 return ret;
2302 }
2303
2304 /**
2305 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2306 * after the end of the latency interval in which the
2307 * click-detection procedure can start, in cases where the device
2308 * is configured for double-click detection.[get]
2309 *
2310 * @param ctx read / write interface definitions
2311 * @param val change the values of tw in reg TIME_WINDOW
2312 * @retval interface status (MANDATORY: return 0 -> no Error)
2313 *
2314 */
lis2de12_double_tap_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)2315 int32_t lis2de12_double_tap_timeout_get(const stmdev_ctx_t *ctx,
2316 uint8_t *val)
2317 {
2318 lis2de12_time_window_t time_window;
2319 int32_t ret;
2320
2321 ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_WINDOW,
2322 (uint8_t *)&time_window, 1);
2323 *val = (uint8_t)time_window.tw;
2324
2325 return ret;
2326 }
2327
2328 /**
2329 * @}
2330 *
2331 */
2332
2333 /**
2334 * @defgroup LIS2DE12_Activity_inactivity
2335 * @brief This section group all the functions concerning activity
2336 * inactivity functionality
2337 * @{
2338 *
2339 */
2340
2341 /**
2342 * @brief Sleep-to-wake, return-to-sleep activation threshold in
2343 * low-power mode.[set]
2344 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2345 *
2346 * @param ctx read / write interface definitions
2347 * @param val change the values of acth in reg ACT_THS
2348 * @retval interface status (MANDATORY: return 0 -> no Error)
2349 *
2350 */
lis2de12_act_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2351 int32_t lis2de12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2352 {
2353 lis2de12_act_ths_t act_ths;
2354 int32_t ret;
2355
2356 ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1);
2357
2358 if (ret == 0)
2359 {
2360 act_ths.acth = val;
2361 ret = lis2de12_write_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1);
2362 }
2363
2364 return ret;
2365 }
2366
2367 /**
2368 * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power
2369 * mode.[get]
2370 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2371 *
2372 * @param ctx read / write interface definitions
2373 * @param val change the values of acth in reg ACT_THS
2374 * @retval interface status (MANDATORY: return 0 -> no Error)
2375 *
2376 */
lis2de12_act_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2377 int32_t lis2de12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2378 {
2379 lis2de12_act_ths_t act_ths;
2380 int32_t ret;
2381
2382 ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1);
2383 *val = (uint8_t)act_ths.acth;
2384
2385 return ret;
2386 }
2387
2388 /**
2389 * @brief Sleep-to-wake, return-to-sleep.[set]
2390 * duration = (8*1[LSb]+1)/ODR
2391 *
2392 * @param ctx read / write interface definitions
2393 * @param val change the values of actd in reg ACT_DUR
2394 * @retval interface status (MANDATORY: return 0 -> no Error)
2395 *
2396 */
lis2de12_act_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)2397 int32_t lis2de12_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val)
2398 {
2399 lis2de12_act_dur_t act_dur;
2400 int32_t ret;
2401
2402 ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1);
2403
2404 if (ret == 0)
2405 {
2406 act_dur.actd = val;
2407 ret = lis2de12_write_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1);
2408 }
2409
2410 return ret;
2411 }
2412
2413 /**
2414 * @brief Sleep-to-wake, return-to-sleep.[get]
2415 * duration = (8*1[LSb]+1)/ODR
2416 *
2417 * @param ctx read / write interface definitions
2418 * @param val change the values of actd in reg ACT_DUR
2419 * @retval interface status (MANDATORY: return 0 -> no Error)
2420 *
2421 */
lis2de12_act_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)2422 int32_t lis2de12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val)
2423 {
2424 lis2de12_act_dur_t act_dur;
2425 int32_t ret;
2426
2427 ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1);
2428 *val = (uint8_t)act_dur.actd;
2429
2430 return ret;
2431 }
2432
2433 /**
2434 * @}
2435 *
2436 */
2437
2438 /**
2439 * @defgroup LIS2DE12_Serial_interface
2440 * @brief This section group all the functions concerning serial
2441 * interface management
2442 * @{
2443 *
2444 */
2445
2446 /**
2447 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2448 *
2449 * @param ctx read / write interface definitions
2450 * @param val change the values of sdo_pu_disc in reg CTRL_REG0
2451 * @retval interface status (MANDATORY: return 0 -> no Error)
2452 *
2453 */
lis2de12_pin_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lis2de12_sdo_pu_disc_t val)2454 int32_t lis2de12_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
2455 lis2de12_sdo_pu_disc_t val)
2456 {
2457 lis2de12_ctrl_reg0_t ctrl_reg0;
2458 int32_t ret;
2459
2460 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG0,
2461 (uint8_t *)&ctrl_reg0, 1);
2462
2463 if (ret == 0)
2464 {
2465 ctrl_reg0.sdo_pu_disc = (uint8_t)val;
2466 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG0,
2467 (uint8_t *)&ctrl_reg0, 1);
2468 }
2469
2470 return ret;
2471 }
2472
2473 /**
2474 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2475 *
2476 * @param ctx read / write interface definitions
2477 * @param val Get the values of sdo_pu_disc in reg CTRL_REG0
2478 * @retval interface status (MANDATORY: return 0 -> no Error)
2479 *
2480 */
lis2de12_pin_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lis2de12_sdo_pu_disc_t * val)2481 int32_t lis2de12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
2482 lis2de12_sdo_pu_disc_t *val)
2483 {
2484 lis2de12_ctrl_reg0_t ctrl_reg0;
2485 int32_t ret;
2486
2487 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG0,
2488 (uint8_t *)&ctrl_reg0, 1);
2489
2490 switch (ctrl_reg0.sdo_pu_disc)
2491 {
2492 case LIS2DE12_PULL_UP_DISCONNECT:
2493 *val = LIS2DE12_PULL_UP_DISCONNECT;
2494 break;
2495
2496 case LIS2DE12_PULL_UP_CONNECT:
2497 *val = LIS2DE12_PULL_UP_CONNECT;
2498 break;
2499
2500 default:
2501 *val = LIS2DE12_PULL_UP_DISCONNECT;
2502 break;
2503 }
2504
2505 return ret;
2506 }
2507
2508 /**
2509 * @brief SPI Serial Interface Mode selection.[set]
2510 *
2511 * @param ctx read / write interface definitions
2512 * @param val change the values of sim in reg CTRL_REG4
2513 * @retval interface status (MANDATORY: return 0 -> no Error)
2514 *
2515 */
lis2de12_spi_mode_set(const stmdev_ctx_t * ctx,lis2de12_sim_t val)2516 int32_t lis2de12_spi_mode_set(const stmdev_ctx_t *ctx, lis2de12_sim_t val)
2517 {
2518 lis2de12_ctrl_reg4_t ctrl_reg4;
2519 int32_t ret;
2520
2521 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
2522 (uint8_t *)&ctrl_reg4, 1);
2523
2524 if (ret == 0)
2525 {
2526 ctrl_reg4.sim = (uint8_t)val;
2527 ret = lis2de12_write_reg(ctx, LIS2DE12_CTRL_REG4,
2528 (uint8_t *)&ctrl_reg4, 1);
2529 }
2530
2531 return ret;
2532 }
2533
2534 /**
2535 * @brief SPI Serial Interface Mode selection.[get]
2536 *
2537 * @param ctx read / write interface definitions
2538 * @param val Get the values of sim in reg CTRL_REG4
2539 * @retval interface status (MANDATORY: return 0 -> no Error)
2540 *
2541 */
lis2de12_spi_mode_get(const stmdev_ctx_t * ctx,lis2de12_sim_t * val)2542 int32_t lis2de12_spi_mode_get(const stmdev_ctx_t *ctx, lis2de12_sim_t *val)
2543 {
2544 lis2de12_ctrl_reg4_t ctrl_reg4;
2545 int32_t ret;
2546
2547 ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4,
2548 (uint8_t *)&ctrl_reg4, 1);
2549
2550 switch (ctrl_reg4.sim)
2551 {
2552 case LIS2DE12_SPI_4_WIRE:
2553 *val = LIS2DE12_SPI_4_WIRE;
2554 break;
2555
2556 case LIS2DE12_SPI_3_WIRE:
2557 *val = LIS2DE12_SPI_3_WIRE;
2558 break;
2559
2560 default:
2561 *val = LIS2DE12_SPI_4_WIRE;
2562 break;
2563 }
2564
2565 return ret;
2566 }
2567
2568 /**
2569 * @}
2570 *
2571 */
2572
2573 /**
2574 * @}
2575 *
2576 */
2577
2578 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2579
