1#! cpp
2
3/*
4 * SPDX-FileCopyrightText: Copyright 2019-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21#ifndef STACK_SIZE
22#define STACK_SIZE 0x8000
23#endif
24
25#ifndef HEAP_SIZE
26#define HEAP_SIZE 0x10000
27#endif
28
29#define LR_START   0x10000000
30#define LR_SIZE    0x01000000
31
32#define ITCM_START 0x10000000
33#define ITCM_SIZE  0x00080000
34
35#define BRAM_START 0x11000000
36#define BRAM_SIZE  0x00200000
37
38#define DTCM_START 0x30000000
39#define DTCM_SIZE  0x00080000
40
41#define SRAM_START 0x31000000
42#define SRAM_SIZE  0x00200000
43
44#define DDR_START  0x70000000
45#define DDR_SIZE   0x02000000
46
47#define STACK_HEAP 0x30080000
48
49APP_IMAGE LR_START LR_SIZE
50{
51    ; ITCM 512kB
52    rom_exec ITCM_START ITCM_SIZE
53    {
54        *.o (RESET, +First)
55        *(InRoot$$Sections)
56        ; Make sure reset_handler ends up in root segment, when split across
57        ; ITCM and DTCM
58        startup_ARMCM55.o
59        .ANY (+RO)
60    }
61
62    ; MPS3 BRAM
63    BRAM BRAM_START UNINIT BRAM_SIZE
64    {
65    }
66
67    ; DTCM 512kB
68    ; Only accessible from the Cortex-M
69    DTCM DTCM_START (DTCM_SIZE - STACK_SIZE - HEAP_SIZE)
70    {
71        .ANY1 (+RW +ZI)
72    }
73
74    ; SSE-300 SRAM (3 cycles read latency) from M55/U55
75    ; 2x2MB - only first part mapped
76    SRAM SRAM_START UNINIT SRAM_SIZE
77    {
78    }
79
80    ARM_LIB_HEAP  (STACK_HEAP - STACK_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {}
81    ARM_LIB_STACK (STACK_HEAP - STACK_SIZE) EMPTY ALIGN 8 STACK_SIZE {}
82}
83
84LOAD_REGION_1 DDR_START DDR_SIZE
85{
86    ; 2GB DDR4 available
87    rom_dram DDR_START
88    {
89        unity_test_arm_ds_cnn_l_s8.o
90        unity_test_arm_ds_cnn_s_s8.o
91    }
92}
93