1/*
2 * SPDX-FileCopyrightText: Copyright 2009-2021, 2023-2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/*
20 *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
21 */
22
23/*---------------------- ITCM Configuration ----------------------------------
24  <h> Flash Configuration
25    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
26    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
27  </h>
28  -----------------------------------------------------------------------------*/
29__ROM_BASE = 0x00000000;
30__ROM_SIZE = 0x00080000;
31
32/*--------------------- DTCM RAM Configuration ----------------------------
33  <h> RAM Configuration
34    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
35    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
36  </h>
37 -----------------------------------------------------------------------------*/
38__RAM_BASE = 0x20000000;
39__RAM_SIZE = 0x00080000;
40
41/*--------------------- Embedded SRAM Configuration ----------------------------
42  <h> SRAM Configuration
43    <o0> SRAM Base Address    <0x0-0xFFFFFFFF:8>
44    <o1> SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
45  </h>
46 -----------------------------------------------------------------------------*/
47__SRAM_BASE = 0x21000000;
48__SRAM_SIZE = 0x00200000;
49
50/*--------------------- Stack / Heap Configuration ----------------------------
51  <h> Stack / Heap Configuration
52    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
53    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
54  </h>
55  -----------------------------------------------------------------------------*/
56__STACK_SIZE = 0x00008000;
57__HEAP_SIZE  = 0x00010000;
58
59/*--------------------- Embedded RAM Configuration ----------------------------
60  <h> DDR Configuration
61    <o0> DDR Base Address    <0x0-0xFFFFFFFF:8>
62    <o1> DDR Size (in Bytes) <0x0-0xFFFFFFFF:8>
63  </h>
64 -----------------------------------------------------------------------------*/
65__DDR_BASE = 0x60000000;
66__DDR_SIZE = 0x02000000;
67
68/*
69 *-------------------- <<< end of configuration section >>> -------------------
70 */
71
72MEMORY
73{
74  ITCM  (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
75  DTCM  (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
76  SRAM  (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE
77  DDR   (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE
78}
79
80/* Linker script to place sections and symbol values. Should be used together
81 * with other linker script that defines memory regions ITCM and RAM.
82 * It references following symbols, which must be defined in code:
83 *   Reset_Handler : Entry of reset handler
84 *
85 * It defines following symbols, which code can use without definition:
86 *   __exidx_start
87 *   __exidx_end
88 *   __copy_table_start__
89 *   __copy_table_end__
90 *   __zero_table_start__
91 *   __zero_table_end__
92 *   __etext
93 *   __data_start__
94 *   __preinit_array_start
95 *   __preinit_array_end
96 *   __init_array_start
97 *   __init_array_end
98 *   __fini_array_start
99 *   __fini_array_end
100 *   __data_end__
101 *   __bss_start__
102 *   __bss_end__
103 *   __end__
104 *   end
105 *   __HeapLimit
106 *   __StackLimit
107 *   __StackTop
108 *   __stack
109 */
110ENTRY(Reset_Handler)
111
112SECTIONS
113{
114  .text :
115  {
116    KEEP(*(.vectors))
117    *(.text*)
118
119    KEEP(*(.init))
120    KEEP(*(.fini))
121
122    /* .ctors */
123    *crtbegin.o(.ctors)
124    *crtbegin?.o(.ctors)
125    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
126    *(SORT(.ctors.*))
127    *(.ctors)
128
129    /* .dtors */
130    *crtbegin.o(.dtors)
131    *crtbegin?.o(.dtors)
132    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
133    *(SORT(.dtors.*))
134    *(.dtors)
135
136    KEEP(*(.eh_frame*))
137  } > ITCM
138
139  /*
140   * SG veneers:
141   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
142   * must be set, either with the command line option �--section-start� or in a linker script,
143   * to indicate where to place these veneers in memory.
144   */
145/*
146  .gnu.sgstubs :
147  {
148    . = ALIGN(32);
149  } > ITCM
150*/
151  .ARM.extab :
152  {
153    *(.ARM.extab* .gnu.linkonce.armextab.*)
154  } > ITCM
155
156  __exidx_start = .;
157  .ARM.exidx :
158  {
159    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
160  } > ITCM
161  __exidx_end = .;
162
163  .copy.table :
164  {
165    . = ALIGN(4);
166    __copy_table_start__ = .;
167    LONG (__etext)
168    LONG (__data_start__)
169    LONG (__data_end__ - __data_start__)
170    /* Add each additional data section here */
171    __copy_table_end__ = .;
172  } > ITCM
173
174  .zero.table :
175  {
176    . = ALIGN(4);
177    __zero_table_start__ = .;
178    /* Add each additional bss section here */
179/*
180    LONG (__bss2_start__)
181    LONG (__bss2_end__ - __bss2_start__)
182*/
183    __zero_table_end__ = .;
184  } > ITCM
185
186  /**
187   * Location counter can end up 2byte aligned with narrow Thumb code but
188   * __etext is assumed by startup code to be the LMA of a section in DTCM
189   * which must be 4byte aligned
190   */
191  __etext = ALIGN (4);
192
193  .data : AT (__etext)
194  {
195    __data_start__ = .;
196    *(vtable)
197    *(.data)
198    *(.data.*)
199
200    . = ALIGN(4);
201    /* preinit data */
202    PROVIDE_HIDDEN (__preinit_array_start = .);
203    KEEP(*(.preinit_array))
204    PROVIDE_HIDDEN (__preinit_array_end = .);
205
206    . = ALIGN(4);
207    /* init data */
208    PROVIDE_HIDDEN (__init_array_start = .);
209    KEEP(*(SORT(.init_array.*)))
210    KEEP(*(.init_array))
211    PROVIDE_HIDDEN (__init_array_end = .);
212
213
214    . = ALIGN(4);
215    /* finit data */
216    PROVIDE_HIDDEN (__fini_array_start = .);
217    KEEP(*(SORT(.fini_array.*)))
218    KEEP(*(.fini_array))
219    PROVIDE_HIDDEN (__fini_array_end = .);
220
221    KEEP(*(.jcr*))
222    . = ALIGN(4);
223    /* All data end */
224    __data_end__ = .;
225
226  } > DTCM
227
228  /*
229   * Secondary data section, optional
230   *
231   * Remember to add each additional data section
232   * to the .copy.table above to asure proper
233   * initialization during startup.
234   */
235/*
236  __etext2 = ALIGN (4);
237
238  .data2 : AT (__etext2)
239  {
240    . = ALIGN(4);
241    __data2_start__ = .;
242    *(.data2)
243    *(.data2.*)
244    . = ALIGN(4);
245    __data2_end__ = .;
246
247  } > RAM2
248*/
249
250  .sram :
251  {
252    . = ALIGN(16);
253    *(.bss.NoInit)
254    . = ALIGN(16);
255  } > SRAM AT > SRAM
256
257  .ddr :
258  {
259    . = ALIGN(16);
260    *(.rodata*)
261  } > DDR AT > DDR
262
263  .bss :
264  {
265    . = ALIGN(4);
266    __bss_start__ = .;
267    *(.bss)
268    *(.bss.*)
269    *(COMMON)
270    . = ALIGN(4);
271    __bss_end__ = .;
272  } > DTCM AT > DTCM
273
274
275  /*
276   * Secondary bss section, optional
277   *
278   * Remember to add each additional bss section
279   * to the .zero.table above to asure proper
280   * initialization during startup.
281   */
282/*
283  .bss2 :
284  {
285    . = ALIGN(4);
286    __bss2_start__ = .;
287    *(.bss2)
288    *(.bss2.*)
289    . = ALIGN(4);
290    __bss2_end__ = .;
291  } > RAM2 AT > RAM2
292*/
293
294  .heap (COPY) :
295  {
296    . = ALIGN(8);
297    __end__ = .;
298    PROVIDE(end = .);
299    . = . + __HEAP_SIZE;
300    . = ALIGN(8);
301    __HeapLimit = .;
302  } > DTCM
303
304  .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) :
305  {
306    . = ALIGN(8);
307    __StackLimit = .;
308    . = . + __STACK_SIZE;
309    . = ALIGN(8);
310    __StackTop = .;
311  } > DTCM
312  PROVIDE(__stack = __StackTop);
313
314  /* Check if data + heap + stack exceeds DTCM limit */
315  ASSERT(__StackLimit >= __HeapLimit, "region DTCM overflowed with stack")
316}
317