1/***************************************************************************//**
2* \file cy8c6xxa_cm4_dual.ld
3* \version 2.60
4*
5* Linker file for the GNU C compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point location is fixed and starts at 0x10000000. The valid
12* application image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2019 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37#include <main.h>
38
39OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
40SEARCH_DIR(.)
41GROUP(-lgcc -lc -lnosys)
42ENTRY(Reset_Handler)
43
44/* Size of the stack section at the end of CM4 SRAM */
45STACK_SIZE = 0x1000;
46
47/* The size of the MCU boot header area at the start of FLASH */
48BOOT_HEADER_SIZE = 0x400;
49
50/* Force symbol to be entered in the output file as an undefined symbol. Doing
51* this may, for example, trigger linking of additional modules from standard
52* libraries. You may list several symbols for each EXTERN, and you may use
53* EXTERN multiple times. This command has the same effect as the -u command-line
54* option.
55*/
56EXTERN(Reset_Handler)
57
58/* The MEMORY section below describes the location and size of blocks of memory in the target.
59* Use this section to specify the memory regions available for allocation.
60*/
61MEMORY
62{
63    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
64     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
65     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
66     * Using this memory region for other purposes will lead to unexpected behavior.
67     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
68     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
69     */
70    ram               (rwx)   : ORIGIN = RAM_START, LENGTH = RAM_SIZE
71    flash             (rx)    : ORIGIN = USER_APP_START, LENGTH = USER_APP_SIZE
72
73    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
74     * You can assign sections to this memory region for only one of the cores.
75     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
76     * Therefore, repurposing this memory region will prevent such middleware from operation.
77     */
78    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
79
80    /* The following regions define device specific memory regions and must not be changed. */
81    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
82    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
83    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
84    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
85    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
86    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
87    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
88}
89
90/* Library configurations */
91GROUP(libgcc.a libc.a libm.a libnosys.a)
92
93/* Linker script to place sections and symbol values. Should be used together
94 * with other linker script that defines memory regions FLASH and RAM.
95 * It references following symbols, which must be defined in code:
96 *   Reset_Handler : Entry of reset handler
97 *
98 * It defines following symbols, which code can use without definition:
99 *   __exidx_start
100 *   __exidx_end
101 *   __copy_table_start__
102 *   __copy_table_end__
103 *   __zero_table_start__
104 *   __zero_table_end__
105 *   __etext
106 *   __data_start__
107 *   __preinit_array_start
108 *   __preinit_array_end
109 *   __init_array_start
110 *   __init_array_end
111 *   __fini_array_start
112 *   __fini_array_end
113 *   __data_end__
114 *   __bss_start__
115 *   __bss_end__
116 *   __end__
117 *   end
118 *   __HeapLimit
119 *   __StackLimit
120 *   __StackTop
121 *   __stack
122 *   __Vectors_End
123 *   __Vectors_Size
124 */
125
126
127SECTIONS
128{
129    /* Cortex-M4 application flash area */
130    .text ORIGIN(flash) + BOOT_HEADER_SIZE :
131    {
132        . = ALIGN(4);
133        __Vectors = . ;
134        KEEP(*(.vectors))
135        . = ALIGN(4);
136        __Vectors_End = .;
137        __Vectors_Size = __Vectors_End - __Vectors;
138        __end__ = .;
139
140        . = ALIGN(4);
141        *(.text*)
142
143        KEEP(*(.init))
144        KEEP(*(.fini))
145
146        /* .ctors */
147        *crtbegin.o(.ctors)
148        *crtbegin?.o(.ctors)
149        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
150        *(SORT(.ctors.*))
151        *(.ctors)
152
153        /* .dtors */
154        *crtbegin.o(.dtors)
155        *crtbegin?.o(.dtors)
156        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
157        *(SORT(.dtors.*))
158        *(.dtors)
159
160        /* Read-only code (constants). */
161        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
162
163        KEEP(*(.eh_frame*))
164    } > flash
165
166
167    .ARM.extab :
168    {
169        *(.ARM.extab* .gnu.linkonce.armextab.*)
170    } > flash
171
172    __exidx_start = .;
173
174    .ARM.exidx :
175    {
176        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
177    } > flash
178    __exidx_end = .;
179
180
181    /* To copy multiple ROM to RAM sections,
182     * uncomment .copy.table section and,
183     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
184    .copy.table :
185    {
186        . = ALIGN(4);
187        __copy_table_start__ = .;
188
189        /* Copy interrupt vectors from flash to RAM */
190        LONG (__Vectors)                                    /* From */
191        LONG (__ram_vectors_start__)                        /* To   */
192        LONG (__Vectors_End - __Vectors)                    /* Size */
193
194        /* Copy data section to RAM */
195        LONG (__etext)                                      /* From */
196        LONG (__data_start__)                               /* To   */
197        LONG (__data_end__ - __data_start__)                /* Size */
198
199        __copy_table_end__ = .;
200    } > flash
201
202
203    /* To clear multiple BSS sections,
204     * uncomment .zero.table section and,
205     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
206    .zero.table :
207    {
208        . = ALIGN(4);
209        __zero_table_start__ = .;
210        LONG (__bss_start__)
211        LONG (__bss_end__ - __bss_start__)
212        __zero_table_end__ = .;
213    } > flash
214
215    __etext =  . ;
216
217
218    .ramVectors (NOLOAD) : ALIGN(8)
219    {
220        __ram_vectors_start__ = .;
221        KEEP(*(.ram_vectors))
222        __ram_vectors_end__   = .;
223    } > ram
224
225
226    .data __ram_vectors_end__ : AT (__etext)
227    {
228        __data_start__ = .;
229
230        *(vtable)
231        *(.data*)
232
233        . = ALIGN(4);
234        /* preinit data */
235        PROVIDE_HIDDEN (__preinit_array_start = .);
236        KEEP(*(.preinit_array))
237        PROVIDE_HIDDEN (__preinit_array_end = .);
238
239        . = ALIGN(4);
240        /* init data */
241        PROVIDE_HIDDEN (__init_array_start = .);
242        KEEP(*(SORT(.init_array.*)))
243        KEEP(*(.init_array))
244        PROVIDE_HIDDEN (__init_array_end = .);
245
246        . = ALIGN(4);
247        /* finit data */
248        PROVIDE_HIDDEN (__fini_array_start = .);
249        KEEP(*(SORT(.fini_array.*)))
250        KEEP(*(.fini_array))
251        PROVIDE_HIDDEN (__fini_array_end = .);
252
253        KEEP(*(.jcr*))
254        . = ALIGN(4);
255
256        KEEP(*(.cy_ramfunc*))
257        . = ALIGN(4);
258
259        __data_end__ = .;
260
261    } > ram
262
263
264    /* Place variables in the section that should not be initialized during the
265    *  device startup.
266    */
267    .noinit (NOLOAD) : ALIGN(8)
268    {
269      KEEP(*(.noinit))
270    } > ram
271
272
273    /* The uninitialized global or static variables are placed in this section.
274    *
275    * The NOLOAD attribute tells linker that .bss section does not consume
276    * any space in the image. The NOLOAD attribute changes the .bss type to
277    * NOBITS, and that  makes linker to A) not allocate section in memory, and
278    * A) put information to clear the section with all zeros during application
279    * loading.
280    *
281    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
282    * This  makes linker to A) allocate zeroed section in memory, and B) copy
283    * this section to RAM during application loading.
284    */
285    .bss (NOLOAD):
286    {
287        . = ALIGN(4);
288        __bss_start__ = .;
289        *(.bss*)
290        *(COMMON)
291        . = ALIGN(4);
292        __bss_end__ = .;
293    } > ram
294
295
296    .heap (NOLOAD):
297    {
298        __HeapBase = .;
299        __end__ = .;
300        end = __end__;
301        KEEP(*(.heap*))
302        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
303        __HeapLimit = .;
304    } > ram
305
306
307    /* .stack_dummy section doesn't contains any symbols. It is only
308     * used for linker to calculate size of stack sections, and assign
309     * values to stack symbols later */
310    .stack_dummy (NOLOAD):
311    {
312        KEEP(*(.stack*))
313    } > ram
314
315
316    /* Set stack top to end of RAM, and stack limit move down by
317     * size of stack_dummy section */
318    __StackTop = ORIGIN(ram) + LENGTH(ram);
319    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
320    PROVIDE(__stack = __StackTop);
321
322    /* Check if data + heap + stack exceeds RAM limit */
323    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
324
325
326    /* Used for the digital signature of the secure application and the Bootloader SDK application.
327    * The size of the section depends on the required data size. */
328    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
329    {
330        KEEP(*(.cy_app_signature))
331    } > flash
332
333
334    /* Emulated EEPROM Flash area */
335    .cy_em_eeprom :
336    {
337        KEEP(*(.cy_em_eeprom))
338    } > em_eeprom
339
340
341    /* Supervisory Flash: User data */
342    .cy_sflash_user_data :
343    {
344        KEEP(*(.cy_sflash_user_data))
345    } > sflash_user_data
346
347
348    /* Supervisory Flash: Normal Access Restrictions (NAR) */
349    .cy_sflash_nar :
350    {
351        KEEP(*(.cy_sflash_nar))
352    } > sflash_nar
353
354
355    /* Supervisory Flash: Public Key */
356    .cy_sflash_public_key :
357    {
358        KEEP(*(.cy_sflash_public_key))
359    } > sflash_public_key
360
361
362    /* Supervisory Flash: Table of Content # 2 */
363    .cy_toc_part2 :
364    {
365        KEEP(*(.cy_toc_part2))
366    } > sflash_toc_2
367
368
369    /* Supervisory Flash: Table of Content # 2 Copy */
370    .cy_rtoc_part2 :
371    {
372        KEEP(*(.cy_rtoc_part2))
373    } > sflash_rtoc_2
374
375
376    /* Places the code in the Execute in Place (XIP) section. See the smif driver
377    *  documentation for details.
378    */
379    .cy_xip :
380    {
381        KEEP(*(.cy_xip))
382    } > xip
383
384
385    /* eFuse */
386    .cy_efuse :
387    {
388        KEEP(*(.cy_efuse))
389    } > efuse
390
391
392    /* These sections are used for additional metadata (silicon revision,
393    *  Silicon/JTAG ID, etc.) storage.
394    */
395    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
396}
397
398
399/* The following symbols used by the cymcuelftool. */
400/* Flash */
401__cy_memory_0_start    = 0x10000000;
402__cy_memory_0_length   = 0x00200000;
403__cy_memory_0_row_size = 0x200;
404
405/* Emulated EEPROM Flash area */
406__cy_memory_1_start    = 0x14000000;
407__cy_memory_1_length   = 0x8000;
408__cy_memory_1_row_size = 0x200;
409
410/* Supervisory Flash */
411__cy_memory_2_start    = 0x16000000;
412__cy_memory_2_length   = 0x8000;
413__cy_memory_2_row_size = 0x200;
414
415/* XIP */
416__cy_memory_3_start    = 0x18000000;
417__cy_memory_3_length   = 0x08000000;
418__cy_memory_3_row_size = 0x200;
419
420/* eFuse */
421__cy_memory_4_start    = 0x90700000;
422__cy_memory_4_length   = 0x100000;
423__cy_memory_4_row_size = 1;
424
425/* EOF */
426