1/* 2(C) Copyright IBM Corp. 2008 3 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9* Redistributions of source code must retain the above copyright notice, 10this list of conditions and the following disclaimer. 11* Redistributions in binary form must reproduce the above copyright 12notice, this list of conditions and the following disclaimer in the 13documentation and/or other materials provided with the distribution. 14* Neither the name of IBM nor the names of its contributors may be 15used to endorse or promote products derived from this software without 16specific prior written permission. 17 18THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 22LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28POSSIBILITY OF SUCH DAMAGE. 29*/ 30 31/* First-level interrupt handler. */ 32 33/* The following two convenience macros assist in the coding of the 34 saving and restoring the volatile register starting from register 35 2 up to register 79. 36 37 saveregs first, last Saves registers from first to the last. 38 restoreregs first, last Restores registers from last down to first. 39 40 Note: first must be less than or equal to last. */ 41 42#include <picolibc.h> 43 44.macro saveregs first, last 45 stqd $\first, -(STACK_SKIP+\first)*16($SP) 46.if \last-\first 47 saveregs "(\first+1)",\last 48.endif 49.endm 50 51 52.macro restoreregs first, last 53 lqd $\last, (82-\last)*16($SP) 54.if \last-\first 55 restoreregs \first,"(\last-1)" 56.endif 57.endm 58 59 .section .interrupt,"ax" 60 .align 3 61 .type spu_flih, @function 62spu_flih: 63 /* Adjust the stack pointer to skip the maximum register save area 64 (STACK_SKIP quadword registers) in case an interrupt occurred while 65 executing a leaf function that used the stack area without actually 66 allocating its own stack frame. */ 67 .set STACK_SKIP, 125 68 69 /* Save the current link register on a new stack frame for the 70 normal spu_flih() version of this file. */ 71 stqd $0, -(STACK_SKIP+80)*16($SP) 72 stqd $SP, -(STACK_SKIP+82)*16($SP) /* Save back chain pointer. */ 73 74 saveregs 2, 39 75 76 il $2, -(STACK_SKIP+82)*16 /* Stack frame size. */ 77 rdch $3, $SPU_RdEventStat /* Read event status. */ 78 79 rdch $6, $SPU_RdEventMask /* Read event mask. */ 80 hbrp /* Open a slot for instruction prefetch. */ 81 82 saveregs 40,59 83 84 clz $4, $3 /* Get first slih index. */ 85 stqd $6, -(STACK_SKIP+1)*16($SP) /* Save event mask on stack. */ 86 87 saveregs 60, 67 88 89 /* Do not disable/ack the decrementer event here. 90 The timer library manages this and expects it 91 to be enabled upon entry to the SLIH. */ 92 il $7, 0x20 93 andc $5, $3, $7 94 andc $7, $6, $5 /* Clear event bits. */ 95 saveregs 68, 69 96 97 wrch $SPU_WrEventAck, $3 /* Ack events(s) - include decrementer event. */ 98 wrch $SPU_WrEventMask, $7 /* Disable event(s) - exclude decrementer event. */ 99 100 saveregs 70, 79 101 102 a $SP, $SP, $2 /* Instantiate flih stack frame. */ 103next_event: 104 /* Fetch and dispatch the event handler for the first non-zero event. The 105 dispatch handler is indexed into the __spu_slih_handlers array using the 106 count of zero off the event status as an index. */ 107 ila $5, __spu_slih_handlers /* Slih array offset. */ 108 109 shli $4, $4, 2 /* Slih entry offset. */ 110 lqx $5, $4, $5 /* Load slih address. */ 111 rotqby $5, $5, $4 /* Rotate to word 0. */ 112 bisl $0, $5 /* Branch to slih. */ 113 114 clz $4, $3 /* Get next slih index. */ 115 brnz $3, next_event 116 117 118 lqd $2, 81*16($SP) /* Read event mask from stack. */ 119 120 restoreregs 40, 79 121 122 wrch $SPU_WrEventMask, $2 /* Restore event mask. */ 123 hbrp /* Open a slot for instruction pre-fetch. */ 124 125 restoreregs 2, 39 126 127 /* Restore the link register from the new stack frame for the 128 normal spu_flih() version of this file. */ 129 lqd $0, 2*16($SP) 130 131 lqd $SP, 0*16($SP) /* restore stack pointer from back chain ptr. */ 132 133 irete /* Return from interrupt and re-enable interrupts. */ 134 .size spu_flih, .-spu_flih 135/* spu_slih_handlers[] 136 Here we initialize 33 default event handlers. The first entry in this array 137 corresponds to the event handler for the event associated with bit 0 of 138 Channel 0 (External Event Status). The 32nd entry in this array corresponds 139 to bit 31 of Channel 0 (DMA Tag Status Update Event). The 33rd entry in 140 this array is a special case entry to handle "phantom events" which occur 141 when the channel count for Channel 0 is 1, causing an asynchronous SPU 142 interrupt, but the value returned for a read of Channel 0 is 0. The index 143 calculated into this array by spu_flih() for this case is 32, hence the 144 33rd entry. */ 145.data 146 .align 4 147 .extern __spu_default_slih 148 .global __spu_slih_handlers 149 .type __spu_slih_handlers, @object 150__spu_slih_handlers: 151 .rept 33 152 .long __spu_default_slih 153 .endr 154 .size __spu_slih_handlers, .-__spu_slih_handlers 155
