1/*
2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <cortex_a75.h>
10#include <cpuamu.h>
11#include <cpu_macros.S>
12
13/* Hardware handled coherency */
14#if HW_ASSISTED_COHERENCY == 0
15#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
16#endif
17
18workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081
19	sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT
20workaround_reset_end cortex_a75, ERRATUM(764081)
21
22check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0)
23
24workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748
25	sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13)
26workaround_reset_end cortex_a75, ERRATUM(790748)
27
28check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0)
29
30/* ERRATA_DSU_798953 :
31 * The errata is defined in dsu_helpers.S but applies to cortex_a75
32 * as well. Henceforth creating symbolic names to the already existing errata
33 * workaround functions to get them registered under the Errata Framework.
34 */
35.equ check_erratum_cortex_a75_798953, check_errata_dsu_798953
36.equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa
37add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
38
39/* ERRATA_DSU_936184 :
40 * The errata is defined in dsu_helpers.S but applies to cortex_a75
41 * as well. Henceforth creating symbolic names to the already existing errata
42 * workaround functions to get them registered under the Errata Framework.
43 */
44.equ check_erratum_cortex_a75_936184, check_errata_dsu_936184
45.equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa
46add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
47
48workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
49#if IMAGE_BL31
50	override_vector_table wa_cve_2017_5715_bpiall_vbar
51#endif /* IMAGE_BL31 */
52workaround_reset_end cortex_a75, CVE(2017, 5715)
53
54check_erratum_custom_start cortex_a75, CVE(2017, 5715)
55	cpu_check_csv2	x0, 1f
56#if WORKAROUND_CVE_2017_5715
57	mov	x0, #ERRATA_APPLIES
58#else
59	mov	x0, #ERRATA_MISSING
60#endif
61	ret
621:
63	mov	x0, #ERRATA_NOT_APPLIES
64	ret
65check_erratum_custom_end cortex_a75, CVE(2017, 5715)
66
67workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
68	sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE
69workaround_reset_end cortex_a75, CVE(2018, 3639)
70
71check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
72
73workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
74#if IMAGE_BL31
75	/* Skip installing vector table again if already done for CVE(2017, 5715) */
76	adr	x0, wa_cve_2017_5715_bpiall_vbar
77	mrs	x1, vbar_el3
78	cmp	x0, x1
79	b.eq	1f
80	msr	vbar_el3, x0
811:
82#endif /* IMAGE_BL31 */
83workaround_reset_end cortex_a75, CVE(2022, 23960)
84
85check_erratum_custom_start cortex_a75, CVE(2022, 23960)
86#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
87	cpu_check_csv2	x0, 1f
88	mov	x0, #ERRATA_APPLIES
89	ret
901:
91# if WORKAROUND_CVE_2022_23960
92	mov	x0, #ERRATA_APPLIES
93# else
94	mov	x0, #ERRATA_MISSING
95# endif /* WORKAROUND_CVE_2022_23960 */
96	ret
97#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
98	mov	x0, #ERRATA_MISSING
99	ret
100check_erratum_custom_end cortex_a75, CVE(2022, 23960)
101
102	/* -------------------------------------------------
103	 * The CPU Ops reset function for Cortex-A75.
104	 * -------------------------------------------------
105	 */
106
107cpu_reset_func_start cortex_a75
108#if ENABLE_FEAT_AMU
109	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
110	sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT
111	isb
112
113	/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
114	sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT
115	isb
116
117	/* Enable group0 counters */
118	mov	x0, #CORTEX_A75_AMU_GROUP0_MASK
119	msr	CPUAMCNTENSET_EL0, x0
120	isb
121
122	/* Enable group1 counters */
123	mov	x0, #CORTEX_A75_AMU_GROUP1_MASK
124	msr	CPUAMCNTENSET_EL0, x0
125	/* isb included in cpu_reset_func_end macro */
126#endif
127cpu_reset_func_end cortex_a75
128
129func check_smccc_arch_workaround_3
130	mov	x0, #ERRATA_APPLIES
131	ret
132endfunc check_smccc_arch_workaround_3
133
134	/* ---------------------------------------------
135	 * HW will do the cache maintenance while powering down
136	 * ---------------------------------------------
137	 */
138func cortex_a75_core_pwr_dwn
139	/* ---------------------------------------------
140	 * Enable CPU power down bit in power control register
141	 * ---------------------------------------------
142	 */
143	sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \
144		CORTEX_A75_CORE_PWRDN_EN_MASK
145	isb
146	ret
147endfunc cortex_a75_core_pwr_dwn
148
149errata_report_shim cortex_a75
150
151	/* ---------------------------------------------
152	 * This function provides cortex_a75 specific
153	 * register information for crash reporting.
154	 * It needs to return with x6 pointing to
155	 * a list of register names in ascii and
156	 * x8 - x15 having values of registers to be
157	 * reported.
158	 * ---------------------------------------------
159	 */
160.section .rodata.cortex_a75_regs, "aS"
161cortex_a75_regs:  /* The ascii list of register names to be reported */
162	.asciz	"cpuectlr_el1", ""
163
164func cortex_a75_cpu_reg_dump
165	adr	x6, cortex_a75_regs
166	mrs	x8, CORTEX_A75_CPUECTLR_EL1
167	ret
168endfunc cortex_a75_cpu_reg_dump
169
170declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
171	cortex_a75_reset_func, \
172	check_erratum_cortex_a75_5715, \
173	CPU_NO_EXTRA2_FUNC, \
174	check_smccc_arch_workaround_3, \
175	cortex_a75_core_pwr_dwn
176