1/* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14#if WORKAROUND_CVE_2022_23960 15 wa_cve_2022_23960_bhb_vector_table CORTEX_A72_BHB_LOOP_COUNT, cortex_a72 16#endif /* WORKAROUND_CVE_2022_23960 */ 17 18 /* --------------------------------------------- 19 * Disable L1 data cache and unified L2 cache 20 * --------------------------------------------- 21 */ 22func cortex_a72_disable_dcache 23 mrs x1, sctlr_el3 24 bic x1, x1, #SCTLR_C_BIT 25 msr sctlr_el3, x1 26 isb 27 ret 28endfunc cortex_a72_disable_dcache 29 30 /* --------------------------------------------- 31 * Disable all types of L2 prefetches. 32 * --------------------------------------------- 33 */ 34func cortex_a72_disable_l2_prefetch 35 mrs x0, CORTEX_A72_ECTLR_EL1 36 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 37 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 38 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 39 bic x0, x0, x1 40 msr CORTEX_A72_ECTLR_EL1, x0 41 isb 42 ret 43endfunc cortex_a72_disable_l2_prefetch 44 45 /* --------------------------------------------- 46 * Disable the load-store hardware prefetcher. 47 * --------------------------------------------- 48 */ 49func cortex_a72_disable_hw_prefetcher 50 mrs x0, CORTEX_A72_CPUACTLR_EL1 51 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 52 msr CORTEX_A72_CPUACTLR_EL1, x0 53 isb 54 dsb ish 55 ret 56endfunc cortex_a72_disable_hw_prefetcher 57 58 /* --------------------------------------------- 59 * Disable intra-cluster coherency 60 * --------------------------------------------- 61 */ 62func cortex_a72_disable_smp 63 mrs x0, CORTEX_A72_ECTLR_EL1 64 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 65 msr CORTEX_A72_ECTLR_EL1, x0 66 ret 67endfunc cortex_a72_disable_smp 68 69 /* --------------------------------------------- 70 * Disable debug interfaces 71 * --------------------------------------------- 72 */ 73func cortex_a72_disable_ext_debug 74 mov x0, #1 75 msr osdlr_el1, x0 76 isb 77 dsb sy 78 ret 79endfunc cortex_a72_disable_ext_debug 80 81 /* -------------------------------------------------- 82 * Errata Workaround for Cortex A72 Errata #859971. 83 * This applies only to revision <= r0p3 of Cortex A72. 84 * Inputs: 85 * x0: variant[4:7] and revision[0:3] of current cpu. 86 * Shall clobber: 87 * -------------------------------------------------- 88 */ 89func errata_a72_859971_wa 90 mov x17,x30 91 bl check_errata_859971 92 cbz x0, 1f 93 mrs x1, CORTEX_A72_CPUACTLR_EL1 94 orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 95 msr CORTEX_A72_CPUACTLR_EL1, x1 961: 97 ret x17 98endfunc errata_a72_859971_wa 99 100func check_errata_859971 101 mov x1, #0x03 102 b cpu_rev_var_ls 103endfunc check_errata_859971 104 105func check_errata_cve_2017_5715 106 cpu_check_csv2 x0, 1f 107#if WORKAROUND_CVE_2017_5715 108 mov x0, #ERRATA_APPLIES 109#else 110 mov x0, #ERRATA_MISSING 111#endif 112 ret 1131: 114 mov x0, #ERRATA_NOT_APPLIES 115 ret 116endfunc check_errata_cve_2017_5715 117 118func check_errata_cve_2018_3639 119#if WORKAROUND_CVE_2018_3639 120 mov x0, #ERRATA_APPLIES 121#else 122 mov x0, #ERRATA_MISSING 123#endif 124 ret 125endfunc check_errata_cve_2018_3639 126 127 /* -------------------------------------------------- 128 * Errata workaround for Cortex A72 Errata #1319367. 129 * This applies to all revisions of Cortex A72. 130 * -------------------------------------------------- 131 */ 132func check_errata_1319367 133#if ERRATA_A72_1319367 134 mov x0, #ERRATA_APPLIES 135#else 136 mov x0, #ERRATA_MISSING 137#endif 138 ret 139endfunc check_errata_1319367 140 141func check_errata_cve_2022_23960 142#if WORKAROUND_CVE_2022_23960 143 mov x0, #ERRATA_APPLIES 144#else 145 mov x0, #ERRATA_MISSING 146#endif 147 ret 148endfunc check_errata_cve_2022_23960 149 150func check_smccc_arch_workaround_3 151 cpu_check_csv2 x0, 1f 152 mov x0, #ERRATA_APPLIES 153 ret 1541: 155 mov x0, #ERRATA_NOT_APPLIES 156 ret 157endfunc check_smccc_arch_workaround_3 158 159 /* ------------------------------------------------- 160 * The CPU Ops reset function for Cortex-A72. 161 * ------------------------------------------------- 162 */ 163func cortex_a72_reset_func 164 mov x19, x30 165 bl cpu_get_rev_var 166 mov x18, x0 167 168#if ERRATA_A72_859971 169 mov x0, x18 170 bl errata_a72_859971_wa 171#endif 172 173#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) 174 cpu_check_csv2 x0, 1f 175 adr x0, wa_cve_2017_5715_mmu_vbar 176 msr vbar_el3, x0 177 /* isb will be performed before returning from this function */ 178 179 /* Skip CVE_2022_23960 mitigation if cve_2017_5715 mitigation applied */ 180 b 2f 1811: 182#if WORKAROUND_CVE_2022_23960 183 /* 184 * The Cortex-A72 generic vectors are overridden to apply the 185 * mitigation on exception entry from lower ELs for revisions >= r1p0 186 * which has CSV2 implemented. 187 */ 188 adr x0, wa_cve_vbar_cortex_a72 189 msr vbar_el3, x0 190 191 /* isb will be performed before returning from this function */ 192#endif /* WORKAROUND_CVE_2022_23960 */ 1932: 194#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */ 195 196#if WORKAROUND_CVE_2018_3639 197 mrs x0, CORTEX_A72_CPUACTLR_EL1 198 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 199 msr CORTEX_A72_CPUACTLR_EL1, x0 200 isb 201 dsb sy 202#endif 203 204 /* --------------------------------------------- 205 * Enable the SMP bit. 206 * --------------------------------------------- 207 */ 208 mrs x0, CORTEX_A72_ECTLR_EL1 209 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 210 msr CORTEX_A72_ECTLR_EL1, x0 211 isb 212 ret x19 213endfunc cortex_a72_reset_func 214 215 /* ---------------------------------------------------- 216 * The CPU Ops core power down function for Cortex-A72. 217 * ---------------------------------------------------- 218 */ 219func cortex_a72_core_pwr_dwn 220 mov x18, x30 221 222 /* --------------------------------------------- 223 * Turn off caches. 224 * --------------------------------------------- 225 */ 226 bl cortex_a72_disable_dcache 227 228 /* --------------------------------------------- 229 * Disable the L2 prefetches. 230 * --------------------------------------------- 231 */ 232 bl cortex_a72_disable_l2_prefetch 233 234 /* --------------------------------------------- 235 * Disable the load-store hardware prefetcher. 236 * --------------------------------------------- 237 */ 238 bl cortex_a72_disable_hw_prefetcher 239 240 /* --------------------------------------------- 241 * Flush L1 caches. 242 * --------------------------------------------- 243 */ 244 mov x0, #DCCISW 245 bl dcsw_op_level1 246 247 /* --------------------------------------------- 248 * Come out of intra cluster coherency 249 * --------------------------------------------- 250 */ 251 bl cortex_a72_disable_smp 252 253 /* --------------------------------------------- 254 * Force the debug interfaces to be quiescent 255 * --------------------------------------------- 256 */ 257 mov x30, x18 258 b cortex_a72_disable_ext_debug 259endfunc cortex_a72_core_pwr_dwn 260 261 /* ------------------------------------------------------- 262 * The CPU Ops cluster power down function for Cortex-A72. 263 * ------------------------------------------------------- 264 */ 265func cortex_a72_cluster_pwr_dwn 266 mov x18, x30 267 268 /* --------------------------------------------- 269 * Turn off caches. 270 * --------------------------------------------- 271 */ 272 bl cortex_a72_disable_dcache 273 274 /* --------------------------------------------- 275 * Disable the L2 prefetches. 276 * --------------------------------------------- 277 */ 278 bl cortex_a72_disable_l2_prefetch 279 280 /* --------------------------------------------- 281 * Disable the load-store hardware prefetcher. 282 * --------------------------------------------- 283 */ 284 bl cortex_a72_disable_hw_prefetcher 285 286#if !SKIP_A72_L1_FLUSH_PWR_DWN 287 /* --------------------------------------------- 288 * Flush L1 caches. 289 * --------------------------------------------- 290 */ 291 mov x0, #DCCISW 292 bl dcsw_op_level1 293#endif 294 295 /* --------------------------------------------- 296 * Disable the optional ACP. 297 * --------------------------------------------- 298 */ 299 bl plat_disable_acp 300 301 /* ------------------------------------------------- 302 * Flush the L2 caches. 303 * ------------------------------------------------- 304 */ 305 mov x0, #DCCISW 306 bl dcsw_op_level2 307 308 /* --------------------------------------------- 309 * Come out of intra cluster coherency 310 * --------------------------------------------- 311 */ 312 bl cortex_a72_disable_smp 313 314 /* --------------------------------------------- 315 * Force the debug interfaces to be quiescent 316 * --------------------------------------------- 317 */ 318 mov x30, x18 319 b cortex_a72_disable_ext_debug 320endfunc cortex_a72_cluster_pwr_dwn 321 322#if REPORT_ERRATA 323/* 324 * Errata printing function for Cortex A72. Must follow AAPCS. 325 */ 326func cortex_a72_errata_report 327 stp x8, x30, [sp, #-16]! 328 329 bl cpu_get_rev_var 330 mov x8, x0 331 332 /* 333 * Report all errata. The revision-variant information is passed to 334 * checking functions of each errata. 335 */ 336 report_errata ERRATA_A72_859971, cortex_a72, 859971 337 report_errata ERRATA_A72_1319367, cortex_a72, 1319367 338 report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 339 report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639 340 report_errata WORKAROUND_CVE_2022_23960, cortex_a72, cve_2022_23960 341 342 ldp x8, x30, [sp], #16 343 ret 344endfunc cortex_a72_errata_report 345#endif 346 347 /* --------------------------------------------- 348 * This function provides cortex_a72 specific 349 * register information for crash reporting. 350 * It needs to return with x6 pointing to 351 * a list of register names in ascii and 352 * x8 - x15 having values of registers to be 353 * reported. 354 * --------------------------------------------- 355 */ 356.section .rodata.cortex_a72_regs, "aS" 357cortex_a72_regs: /* The ascii list of register names to be reported */ 358 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 359 360func cortex_a72_cpu_reg_dump 361 adr x6, cortex_a72_regs 362 mrs x8, CORTEX_A72_ECTLR_EL1 363 mrs x9, CORTEX_A72_MERRSR_EL1 364 mrs x10, CORTEX_A72_L2MERRSR_EL1 365 ret 366endfunc cortex_a72_cpu_reg_dump 367 368declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \ 369 cortex_a72_reset_func, \ 370 check_errata_cve_2017_5715, \ 371 CPU_NO_EXTRA2_FUNC, \ 372 check_smccc_arch_workaround_3, \ 373 cortex_a72_core_pwr_dwn, \ 374 cortex_a72_cluster_pwr_dwn 375
