1 /**
2 ******************************************************************************
3 * @file l3gd20h_reg.c
4 * @author Sensors Software Solution Team
5 * @brief L3GD20H driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "l3gd20h_reg.h"
21
22 /**
23 * @defgroup L3GD20H
24 * @brief This file provides a set of functions needed to drive the
25 * l3gd20h enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup L3GD20H_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
l3gd20h_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak l3gd20h_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
l3gd20h_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak l3gd20h_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup L3GD20H_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
l3gd20h_from_fs245_to_mdps(int16_t lsb)103 float_t l3gd20h_from_fs245_to_mdps(int16_t lsb)
104 {
105 return ((float_t)lsb * 8.75f);
106 }
107
l3gd20h_from_fs500_to_mdps(int16_t lsb)108 float_t l3gd20h_from_fs500_to_mdps(int16_t lsb)
109 {
110 return ((float_t)lsb * 17.50f);
111 }
112
l3gd20h_from_fs2000_to_mdps(int16_t lsb)113 float_t l3gd20h_from_fs2000_to_mdps(int16_t lsb)
114 {
115 return ((float_t)lsb * 70.0f);
116 }
117
l3gd20h_from_lsb_to_celsius(int16_t lsb)118 float_t l3gd20h_from_lsb_to_celsius(int16_t lsb)
119 {
120 return ((float_t)lsb + 25.0f);
121 }
122 /**
123 * @}
124 *
125 */
126
127 /**
128 * @defgroup L3GD20H_Datageneration
129 * @brief This section groups all the functions concerning data generation.
130 * @{
131 *
132 */
133
134 /**
135 * @brief Enable gyroscope axis.[set]
136 *
137 * @param ctx Read / write interface definitions.(ptr)
138 * @param val Gyroscope’s pitch axis (X) output enable..
139 * @retval Interface status (MANDATORY: return 0 -> no Error).
140 *
141 */
l3gd20h_gy_axis_set(const stmdev_ctx_t * ctx,l3gd20h_gy_axis_t val)142 int32_t l3gd20h_gy_axis_set(const stmdev_ctx_t *ctx, l3gd20h_gy_axis_t val)
143 {
144 l3gd20h_ctrl1_t ctrl1;
145 int32_t ret;
146 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
147
148 if (ret == 0)
149 {
150 ctrl1.xen = val.xen;
151 ctrl1.yen = val.yen;
152 ctrl1.zen = val.zen;
153 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
154 }
155
156 return ret;
157 }
158
159 /**
160 * @brief Enable gyroscope axis.[get]
161 *
162 * @param ctx Read / write interface definitions.(ptr)
163 * @param val Gyroscope’s pitch axis (X) output enable..(ptr)
164 * @retval Interface status (MANDATORY: return 0 -> no Error).
165 *
166 */
l3gd20h_gy_axis_get(const stmdev_ctx_t * ctx,l3gd20h_gy_axis_t * val)167 int32_t l3gd20h_gy_axis_get(const stmdev_ctx_t *ctx, l3gd20h_gy_axis_t *val)
168 {
169 l3gd20h_ctrl1_t ctrl1;
170 int32_t ret;
171 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
172 val->xen = ctrl1.xen;
173 val->yen = ctrl1.yen;
174 val->zen = ctrl1.zen;
175
176 return ret;
177 }
178
179 /**
180 * @brief Gyroscope data rate selection..[set]
181 *
182 * @param ctx Read / write interface definitions.(ptr)
183 * @param val Change the values of "pd" in reg L3GD20H.
184 * @retval Interface status (MANDATORY: return 0 -> no Error).
185 *
186 */
l3gd20h_gy_data_rate_set(const stmdev_ctx_t * ctx,l3gd20h_gy_data_rate_t val)187 int32_t l3gd20h_gy_data_rate_set(const stmdev_ctx_t *ctx,
188 l3gd20h_gy_data_rate_t val)
189 {
190 l3gd20h_low_odr_t low_odr;
191 l3gd20h_ctrl1_t ctrl1;
192 int32_t ret;
193 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
194
195 if (ret == 0)
196 {
197 ctrl1.pd = ((uint8_t)val & 0x80U) >> 7;
198 ctrl1.dr = (uint8_t)val & 0x07U;
199 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
200 }
201
202 if (ret == 0)
203 {
204 ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
205 }
206
207 if (ret == 0)
208 {
209 low_odr.low_odr = ((uint8_t)val & 0x10U) >> 4;
210 ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
211 }
212
213 return ret;
214 }
215
216 /**
217 * @brief Gyroscope data rate selection..[get]
218 *
219 * @param ctx Read / write interface definitions.(ptr)
220 * @param val Get the values of pd in reg CTRL1.(ptr)
221 * @retval Interface status (MANDATORY: return 0 -> no Error).
222 *
223 */
l3gd20h_gy_data_rate_get(const stmdev_ctx_t * ctx,l3gd20h_gy_data_rate_t * val)224 int32_t l3gd20h_gy_data_rate_get(const stmdev_ctx_t *ctx,
225 l3gd20h_gy_data_rate_t *val)
226 {
227 l3gd20h_low_odr_t low_odr;
228 l3gd20h_ctrl1_t ctrl1;
229 int32_t ret;
230 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
231
232 if (ret == 0)
233 {
234 ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
235 }
236
237 switch ((ctrl1.pd << 7) + (low_odr.low_odr << 4) + ctrl1.dr)
238 {
239 case L3GD20H_POWER_DOWN:
240 *val = L3GD20H_POWER_DOWN;
241 break;
242
243 case L3GD20H_12Hz5:
244 *val = L3GD20H_12Hz5;
245 break;
246
247 case L3GD20H_25Hz:
248 *val = L3GD20H_25Hz;
249 break;
250
251 case L3GD20H_50Hz:
252 *val = L3GD20H_50Hz;
253 break;
254
255 case L3GD20H_100Hz:
256 *val = L3GD20H_100Hz;
257 break;
258
259 case L3GD20H_200Hz:
260 *val = L3GD20H_200Hz;
261 break;
262
263 case L3GD20H_400Hz:
264 *val = L3GD20H_400Hz;
265 break;
266
267 case L3GD20H_800Hz:
268 *val = L3GD20H_800Hz;
269 break;
270
271 default:
272 *val = L3GD20H_POWER_DOWN;
273 break;
274 }
275
276 return ret;
277 }
278
279 /**
280 * @brief Gyroscope full-scale selection..[set]
281 *
282 * @param ctx Read / write interface definitions.(ptr)
283 * @param val Change the values of "fs" in reg L3GD20H.
284 * @retval Interface status (MANDATORY: return 0 -> no Error).
285 *
286 */
l3gd20h_gy_full_scale_set(const stmdev_ctx_t * ctx,l3gd20h_gy_fs_t val)287 int32_t l3gd20h_gy_full_scale_set(const stmdev_ctx_t *ctx,
288 l3gd20h_gy_fs_t val)
289 {
290 l3gd20h_ctrl4_t ctrl4;
291 int32_t ret;
292 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
293
294 if (ret == 0)
295 {
296 ctrl4.fs = (uint8_t)val;
297 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
298 }
299
300 return ret;
301 }
302
303 /**
304 * @brief Gyroscope full-scale selection..[get]
305 *
306 * @param ctx Read / write interface definitions.(ptr)
307 * @param val Get the values of fs in reg CTRL4.(ptr)
308 * @retval Interface status (MANDATORY: return 0 -> no Error).
309 *
310 */
l3gd20h_gy_full_scale_get(const stmdev_ctx_t * ctx,l3gd20h_gy_fs_t * val)311 int32_t l3gd20h_gy_full_scale_get(const stmdev_ctx_t *ctx,
312 l3gd20h_gy_fs_t *val)
313 {
314 l3gd20h_ctrl4_t ctrl4;
315 int32_t ret;
316 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
317
318 switch (ctrl4.fs)
319 {
320 case L3GD20H_245dps:
321 *val = L3GD20H_245dps;
322 break;
323
324 case L3GD20H_500dps:
325 *val = L3GD20H_500dps;
326 break;
327
328 default:
329 *val = L3GD20H_245dps;
330 break;
331 }
332
333 return ret;
334 }
335 /**
336 * @brief Block data update.[set]
337 *
338 * @param ctx Read / write interface definitions.(ptr)
339 * @param val Change the values of bdu in reg CTRL4.
340 * @retval Interface status (MANDATORY: return 0 -> no Error).
341 *
342 */
l3gd20h_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)343 int32_t l3gd20h_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
344 {
345 l3gd20h_ctrl4_t ctrl4;
346 int32_t ret;
347 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
348
349 if (ret == 0)
350 {
351 ctrl4.bdu = val;
352 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
353 }
354
355 return ret;
356 }
357
358 /**
359 * @brief Blockdataupdate.[get]
360 *
361 * @param ctx Read / write interface definitions.(ptr)
362 * @param val Get the values of bdu in reg CTRL4.(ptr)
363 * @retval Interface status (MANDATORY: return 0 -> no Error).
364 *
365 */
l3gd20h_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)366 int32_t l3gd20h_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
367 {
368 l3gd20h_ctrl4_t ctrl4;
369 int32_t ret;
370 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
371 *val = ctrl4.bdu;
372
373 return ret;
374 }
375 /**
376 * @brief Gyroscope new data available..[get]
377 *
378 * @param ctx Read / write interface definitions.(ptr)
379 * @param val Iet the values of "zyxda" in reg STATUS.(ptr)
380 * @retval Interface status (MANDATORY: return 0 -> no Error).
381 *
382 */
l3gd20h_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)383 int32_t l3gd20h_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
384 uint8_t *val)
385 {
386 l3gd20h_status_t status;
387 int32_t ret;
388 ret = l3gd20h_read_reg(ctx, L3GD20H_STATUS, (uint8_t *)&status, 1);
389 *val = status.zyxda;
390
391 return ret;
392 }
393
394 /**
395 * @}
396 *
397 */
398
399 /**
400 * @defgroup L3GD20H_Dataoutput
401 * @brief This section groups all the data output functions.
402 * @{
403 *
404 */
405
406 /**
407 * @brief Temperature data output register (r). L and H registers together
408 * express a 16-bit word in two’s complement..[get]
409 *
410 * @param ctx Read / write interface definitions.(ptr)
411 * @param buff Buffer that stores the data read.(ptr)
412 * @retval Interface status (MANDATORY: return 0 -> no Error).
413 *
414 */
l3gd20h_temperature_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)415 int32_t l3gd20h_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
416 {
417 int32_t ret;
418 ret = l3gd20h_read_reg(ctx, L3GD20H_OUT_TEMP, buff, 1);
419
420 return ret;
421 }
422
423 /**
424 * @brief Angular rate sensor. The value is expressed as a 16-bit
425 * word in two’s complement..[get]
426 *
427 * @param ctx Read / write interface definitions.(ptr)
428 * @param buff Buffer that stores the data read.(ptr)
429 * @retval Interface status (MANDATORY: return 0 -> no Error).
430 *
431 */
l3gd20h_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)432 int32_t l3gd20h_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
433 {
434 uint8_t buff[6];
435 int32_t ret;
436 ret = l3gd20h_read_reg(ctx, L3GD20H_OUT_X_L, buff, 6);
437 val[0] = (int16_t)buff[1];
438 val[0] = (val[0] * 256) + (int16_t)buff[0];
439 val[1] = (int16_t)buff[3];
440 val[1] = (val[1] * 256) + (int16_t)buff[2];
441 val[2] = (int16_t)buff[5];
442 val[2] = (val[2] * 256) + (int16_t)buff[4];
443
444 return ret;
445 }
446
447 /**
448 * @}
449 *
450 */
451
452 /**
453 * @defgroup L3GD20H_Common
454 * @brief This section groups common useful functions.
455 * @{
456 *
457 */
458
459 /**
460 * @brief DeviceWhoamI..[get]
461 *
462 * @param ctx Read / write interface definitions.(ptr)
463 * @param buff Buffer that stores the data read.(ptr)
464 * @retval Interface status (MANDATORY: return 0 -> no Error).
465 *
466 */
l3gd20h_dev_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)467 int32_t l3gd20h_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
468 {
469 int32_t ret;
470 ret = l3gd20h_read_reg(ctx, L3GD20H_WHO_AM_I, buff, 1);
471
472 return ret;
473 }
474
475 /**
476 * @brief Big/Little Endian data selection..[set]
477 *
478 * @param ctx Read / write interface definitions.(ptr)
479 * @param val Change the values of "ble" in reg L3GD20H.
480 * @retval Interface status (MANDATORY: return 0 -> no Error).
481 *
482 */
l3gd20h_dev_data_format_set(const stmdev_ctx_t * ctx,l3gd20h_ble_t val)483 int32_t l3gd20h_dev_data_format_set(const stmdev_ctx_t *ctx,
484 l3gd20h_ble_t val)
485 {
486 l3gd20h_ctrl4_t ctrl4;
487 int32_t ret;
488 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
489
490 if (ret == 0)
491 {
492 ctrl4.ble = (uint8_t)val;
493 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
494 }
495
496 return ret;
497 }
498
499 /**
500 * @brief Big/Little Endian data selection..[get]
501 *
502 * @param ctx Read / write interface definitions.(ptr)
503 * @param val Get the values of ble in reg CTRL4.(ptr)
504 * @retval Interface status (MANDATORY: return 0 -> no Error).
505 *
506 */
l3gd20h_dev_data_format_get(const stmdev_ctx_t * ctx,l3gd20h_ble_t * val)507 int32_t l3gd20h_dev_data_format_get(const stmdev_ctx_t *ctx,
508 l3gd20h_ble_t *val)
509 {
510 l3gd20h_ctrl4_t ctrl4;
511 int32_t ret;
512 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
513
514 switch (ctrl4.ble)
515 {
516 case L3GD20H_LSB_LOW_ADDRESS:
517 *val = L3GD20H_LSB_LOW_ADDRESS;
518 break;
519
520 case L3GD20H_MSB_LOW_ADDRESS:
521 *val = L3GD20H_MSB_LOW_ADDRESS;
522 break;
523
524 default:
525 *val = L3GD20H_LSB_LOW_ADDRESS;
526 break;
527 }
528
529 return ret;
530 }
531
532 /**
533 * @brief Reboot memory content. Reload the calibration parameters..[set]
534 *
535 * @param ctx Read / write interface definitions.(ptr)
536 * @param val Change the values of boot in reg CTRL5.
537 * @retval Interface status (MANDATORY: return 0 -> no Error).
538 *
539 */
l3gd20h_dev_boot_set(const stmdev_ctx_t * ctx,uint8_t val)540 int32_t l3gd20h_dev_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
541 {
542 l3gd20h_ctrl5_t ctrl5;
543 int32_t ret;
544 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
545
546 if (ret == 0)
547 {
548 ctrl5.boot = val;
549 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
550 }
551
552 return ret;
553 }
554
555 /**
556 * @brief Reboot memory content. Reload the calibration parameters..[get]
557 *
558 * @param ctx Read / write interface definitions.(ptr)
559 * @param val Get the values of boot in reg CTRL5.(ptr)
560 * @retval Interface status (MANDATORY: return 0 -> no Error).
561 *
562 */
l3gd20h_dev_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)563 int32_t l3gd20h_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
564 {
565 l3gd20h_ctrl5_t ctrl5;
566 int32_t ret;
567 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
568 *val = ctrl5.boot;
569
570 return ret;
571 }
572 /**
573 * @brief Device status register.[get]
574 *
575 * @param ctx Read / write interface definitions.(ptr)
576 * @param val X axis new data available..(ptr)
577 * @retval Interface status (MANDATORY: return 0 -> no Error).
578 *
579 */
l3gd20h_dev_status_get(const stmdev_ctx_t * ctx,l3gd20h_status_reg_t * val)580 int32_t l3gd20h_dev_status_get(const stmdev_ctx_t *ctx,
581 l3gd20h_status_reg_t *val)
582 {
583 l3gd20h_status_t status;
584 int32_t ret;
585 ret = l3gd20h_read_reg(ctx, L3GD20H_STATUS, (uint8_t *)&status, 1);
586 val->xda = status.xda;
587 val->yda = status.yda;
588 val->zda = status.zda;
589 val->zyxda = status.zyxda;
590 val->_xor = status._xor;
591 val->yor = status.yor;
592 val->zor = status.zor;
593 val->zyxor = status.zyxor;
594
595 return ret;
596 }
597
598 /**
599 * @brief Software reset. Restore the default values in user registers.[set]
600 *
601 * @param ctx Read / write interface definitions.(ptr)
602 * @param val Change the values of sw_res in reg LOW_ODR.
603 * @retval Interface status (MANDATORY: return 0 -> no Error).
604 *
605 */
l3gd20h_dev_reset_set(const stmdev_ctx_t * ctx,uint8_t val)606 int32_t l3gd20h_dev_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
607 {
608 l3gd20h_low_odr_t low_odr;
609 int32_t ret;
610 ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
611
612 if (ret == 0)
613 {
614 low_odr.sw_res = val;
615 ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
616 }
617
618 return ret;
619 }
620
621 /**
622 * @brief Software reset. Restore the default values in user registers.get]
623 *
624 * @param ctx Read / write interface definitions.(ptr)
625 * @param val Get the values of sw_res in reg LOW_ODR.(ptr)
626 * @retval Interface status (MANDATORY: return 0 -> no Error).
627 *
628 */
l3gd20h_dev_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)629 int32_t l3gd20h_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
630 {
631 l3gd20h_low_odr_t low_odr;
632 int32_t ret;
633 ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
634 *val = low_odr.sw_res;
635
636 return ret;
637 }
638
639 /**
640 * @}
641 *
642 */
643
644 /**
645 * @defgroup L3GD20H_Filters
646 * @brief This section group all the functions concerning the
647 * filters configuration.
648 * @{
649 *
650 */
651
652 /**
653 * @brief Low pass filter cutoff frequency.[set]
654 *
655 * @param ctx Read / write interface definitions.(ptr)
656 * @param val Change the values of "bw" in reg L3GD20H.
657 * @retval Interface status (MANDATORY: return 0 -> no Error).
658 *
659 */
l3gd20h_gy_filter_lp_bandwidth_set(const stmdev_ctx_t * ctx,l3gd20h_lpbw_t val)660 int32_t l3gd20h_gy_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx,
661 l3gd20h_lpbw_t val)
662 {
663 l3gd20h_ctrl1_t ctrl1;
664 int32_t ret;
665 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
666
667 if (ret == 0)
668 {
669 ctrl1.bw = (uint8_t)val;
670 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
671 }
672
673 return ret;
674 }
675
676 /**
677 * @brief Low pass filter cutoff frequency.[get]
678 *
679 * @param ctx Read / write interface definitions.(ptr)
680 * @param val Get the values of bw in reg CTRL1.(ptr)
681 * @retval Interface status (MANDATORY: return 0 -> no Error).
682 *
683 */
l3gd20h_gy_filter_lp_bandwidth_get(const stmdev_ctx_t * ctx,l3gd20h_lpbw_t * val)684 int32_t l3gd20h_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx,
685 l3gd20h_lpbw_t *val)
686 {
687 l3gd20h_low_odr_t low_odr;
688 l3gd20h_ctrl1_t ctrl1;
689 int32_t ret;
690 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1);
691
692 if (ret == 0)
693 {
694 ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
695 }
696
697 switch ((low_odr.low_odr << 7) + (ctrl1.dr << 4) + ctrl1.bw)
698 {
699 case L3GD20H_16Hz6_USE_ODR_50Hz:
700 *val = L3GD20H_16Hz6_USE_ODR_50Hz;
701 break;
702
703 case L3GD20H_12Hz5_USE_ODR_100Hz:
704 *val = L3GD20H_12Hz5_USE_ODR_100Hz;
705 break;
706
707 case L3GD20H_25Hz_USE_ODR_100Hz:
708 *val = L3GD20H_25Hz_USE_ODR_100Hz;
709 break;
710
711 case L3GD20H_12Hz5_USE_ODR_200Hz:
712 *val = L3GD20H_12Hz5_USE_ODR_200Hz;
713 break;
714
715 case L3GD20H_70Hz_USE_ODR_200Hz:
716 *val = L3GD20H_70Hz_USE_ODR_200Hz;
717 break;
718
719 case L3GD20H_20Hz_USE_ODR_400Hz:
720 *val = L3GD20H_20Hz_USE_ODR_400Hz;
721 break;
722
723 case L3GD20H_25Hz_USE_ODR_400Hz:
724 *val = L3GD20H_25Hz_USE_ODR_400Hz;
725 break;
726
727 case L3GD20H_50Hz_USE_ODR_400Hz:
728 *val = L3GD20H_50Hz_USE_ODR_400Hz;
729 break;
730
731 case L3GD20H_110Hz_USE_ODR_400Hz:
732 *val = L3GD20H_110Hz_USE_ODR_400Hz;
733 break;
734
735 case L3GD20H_30Hz_USE_ODR_800Hz:
736 *val = L3GD20H_30Hz_USE_ODR_800Hz;
737 break;
738
739 case L3GD20H_35Hz_USE_ODR_800Hz:
740 *val = L3GD20H_35Hz_USE_ODR_800Hz;
741 break;
742
743 case L3GD20H_100Hz_USE_ODR_800Hz:
744 *val = L3GD20H_100Hz_USE_ODR_800Hz;
745 break;
746
747 default:
748 *val = L3GD20H_16Hz6_USE_ODR_50Hz;
749 break;
750 }
751
752 return ret;
753 }
754
755 /**
756 * @brief Gyroscope high-pass filter bandwidth selection..[set]
757 *
758 * @param ctx Read / write interface definitions.(ptr)
759 * @param val Change the values of "hpcf" in reg L3GD20H.
760 * @retval Interface status (MANDATORY: return 0 -> no Error).
761 *
762 */
l3gd20h_gy_filter_hp_bandwidth_set(const stmdev_ctx_t * ctx,l3gd20h_gy_hp_bw_t val)763 int32_t l3gd20h_gy_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx,
764 l3gd20h_gy_hp_bw_t val)
765 {
766 l3gd20h_ctrl2_t ctrl2;
767 int32_t ret;
768 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
769
770 if (ret == 0)
771 {
772 ctrl2.hpcf = (uint8_t)val & 0x03U;
773 ctrl2.hpm = ((uint8_t)val & 0x30U) >> 4;
774 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
775 }
776
777 return ret;
778 }
779
780 /**
781 * @brief Gyroscope high-pass filter bandwidth selection..[get]
782 *
783 * @param ctx Read / write interface definitions.(ptr)
784 * @param val Get the values of hpcf in reg CTRL2.(ptr)
785 * @retval Interface status (MANDATORY: return 0 -> no Error).
786 *
787 */
l3gd20h_gy_filter_hp_bandwidth_get(const stmdev_ctx_t * ctx,l3gd20h_gy_hp_bw_t * val)788 int32_t l3gd20h_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx,
789 l3gd20h_gy_hp_bw_t *val)
790 {
791 l3gd20h_ctrl2_t ctrl2;
792 int32_t ret;
793 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
794
795 if (ret == 0)
796 {
797 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
798 }
799
800 switch ((ctrl2.hpm << 4) + ctrl2.hpcf)
801 {
802 case L3GD20H_NORMAL_MODE_LIGHT:
803 *val = L3GD20H_NORMAL_MODE_LIGHT;
804 break;
805
806 case L3GD20H_NORMAL_MODE_NORMAL:
807 *val = L3GD20H_NORMAL_MODE_NORMAL;
808 break;
809
810 case L3GD20H_NORMAL_MODE_STRONG:
811 *val = L3GD20H_NORMAL_MODE_STRONG;
812 break;
813
814 case L3GD20H_NORMAL_MODE_EXTREME:
815 *val = L3GD20H_NORMAL_MODE_EXTREME;
816 break;
817
818 case L3GD20H_USE_REFERENCE_LIGHT:
819 *val = L3GD20H_USE_REFERENCE_LIGHT;
820 break;
821
822 case L3GD20H_USE_REFERENCE_NORMAL:
823 *val = L3GD20H_USE_REFERENCE_NORMAL;
824 break;
825
826 case L3GD20H_USE_REFERENCE_STRONG:
827 *val = L3GD20H_USE_REFERENCE_STRONG;
828 break;
829
830 case L3GD20H_USE_REFERENCE_EXTREME:
831 *val = L3GD20H_USE_REFERENCE_EXTREME;
832 break;
833
834 case L3GD20H_AUTORESET_LIGHT:
835 *val = L3GD20H_AUTORESET_LIGHT;
836 break;
837
838 case L3GD20H_AUTORESET_NORMAL:
839 *val = L3GD20H_AUTORESET_NORMAL;
840 break;
841
842 case L3GD20H_AUTORESET_STRONG:
843 *val = L3GD20H_AUTORESET_STRONG;
844 break;
845
846 case L3GD20H_AUTORESET_EXTREME:
847 *val = L3GD20H_AUTORESET_EXTREME;
848 break;
849
850 default:
851 *val = L3GD20H_NORMAL_MODE_LIGHT;
852 break;
853 }
854
855 return ret;
856 }
857
858 /**
859 * @brief Gyro output filter path configuration..[set]
860 *
861 * @param ctx Read / write interface definitions.(ptr)
862 * @param val Change the values of "out_sel" in reg L3GD20H.
863 * @retval Interface status (MANDATORY: return 0 -> no Error).
864 *
865 */
l3gd20h_gy_filter_out_path_set(const stmdev_ctx_t * ctx,l3gd20h_gy_out_path_t val)866 int32_t l3gd20h_gy_filter_out_path_set(const stmdev_ctx_t *ctx,
867 l3gd20h_gy_out_path_t val)
868 {
869 l3gd20h_ctrl5_t ctrl5;
870 int32_t ret;
871 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
872
873 if (ret == 0)
874 {
875 ctrl5.out_sel = (uint8_t)val & 0x03U;
876 ctrl5.hpen = ((uint8_t)val & 0x10U) >> 4;
877 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
878 }
879
880 return ret;
881 }
882
883 /**
884 * @brief Gyro output filter path configuration..[get]
885 *
886 * @param ctx Read / write interface definitions.(ptr)
887 * @param val Get the values of out_sel in reg CTRL5.(ptr)
888 * @retval Interface status (MANDATORY: return 0 -> no Error).
889 *
890 */
l3gd20h_gy_filter_out_path_get(const stmdev_ctx_t * ctx,l3gd20h_gy_out_path_t * val)891 int32_t l3gd20h_gy_filter_out_path_get(const stmdev_ctx_t *ctx,
892 l3gd20h_gy_out_path_t *val)
893 {
894 l3gd20h_ctrl5_t ctrl5;
895 int32_t ret;
896 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
897
898 switch ((ctrl5.hpen << 4) + ctrl5.out_sel)
899 {
900 case L3GD20H_LPF1_OUT:
901 *val = L3GD20H_LPF1_OUT;
902 break;
903
904 case L3GD20H_LPF1_HPF_OUT:
905 *val = L3GD20H_LPF1_HPF_OUT;
906 break;
907
908 case L3GD20H_LPF1_LPF2_OUT:
909 *val = L3GD20H_LPF1_LPF2_OUT;
910 break;
911
912 case L3GD20H_LPF1_HPF_LPF2_OUT:
913 *val = L3GD20H_LPF1_HPF_LPF2_OUT;
914 break;
915
916 default:
917 *val = L3GD20H_LPF1_OUT;
918 break;
919 }
920
921 return ret;
922 }
923
924 /**
925 * @brief Gyro interrupt filter path configuration..[set]
926 *
927 * @param ctx Read / write interface definitions.(ptr)
928 * @param val Change the values of "ig_sel" in reg L3GD20H.
929 * @retval Interface status (MANDATORY: return 0 -> no Error).
930 *
931 */
l3gd20h_gy_filter_int_path_set(const stmdev_ctx_t * ctx,l3gd20h_gy_int_path_t val)932 int32_t l3gd20h_gy_filter_int_path_set(const stmdev_ctx_t *ctx,
933 l3gd20h_gy_int_path_t val)
934 {
935 l3gd20h_ctrl5_t ctrl5;
936 int32_t ret;
937 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
938
939 if (ret == 0)
940 {
941 ctrl5.ig_sel = (uint8_t)val & 0x03U;
942 ctrl5.hpen = ((uint8_t)val & 0x10U) >> 4;
943 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
944 }
945
946 return ret;
947 }
948
949 /**
950 * @brief Gyro interrupt filter path configuration..[get]
951 *
952 * @param ctx Read / write interface definitions.(ptr)
953 * @param val Get the values of ig_sel in reg CTRL5.(ptr)
954 * @retval Interface status (MANDATORY: return 0 -> no Error).
955 *
956 */
l3gd20h_gy_filter_int_path_get(const stmdev_ctx_t * ctx,l3gd20h_gy_int_path_t * val)957 int32_t l3gd20h_gy_filter_int_path_get(const stmdev_ctx_t *ctx,
958 l3gd20h_gy_int_path_t *val)
959 {
960 l3gd20h_ctrl5_t ctrl5;
961 int32_t ret;
962 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5,
963 (uint8_t *)&ctrl5, 1);
964
965 switch ((ctrl5.hpen << 4) + ctrl5.ig_sel)
966 {
967 case L3GD20H_LPF1_INT:
968 *val = L3GD20H_LPF1_INT;
969 break;
970
971 case L3GD20H_LPF1_HPF_INT:
972 *val = L3GD20H_LPF1_HPF_INT;
973 break;
974
975 case L3GD20H_LPF1_LPF2_INT:
976 *val = L3GD20H_LPF1_LPF2_INT;
977 break;
978
979 case L3GD20H_LPF1_HPF_LPF2_INT:
980 *val = L3GD20H_LPF1_HPF_LPF2_INT;
981 break;
982
983 default:
984 *val = L3GD20H_LPF1_INT;
985 break;
986 }
987
988 return ret;
989 }
990
991 /**
992 * @brief Reference value for gyroscope’s digital high-pass filter.[set]
993 *
994 * @param ctx Read / write interface definitions.(ptr)
995 * @param buff Buffer that stores data to be write.(ptr)
996 * @retval Interface status (MANDATORY: return 0 -> no Error).
997 *
998 */
l3gd20h_gy_filter_reference_set(const stmdev_ctx_t * ctx,uint8_t * buff)999 int32_t l3gd20h_gy_filter_reference_set(const stmdev_ctx_t *ctx,
1000 uint8_t *buff)
1001 {
1002 int32_t ret;
1003 ret = l3gd20h_write_reg(ctx, L3GD20H_REFERENCE, buff, 1);
1004
1005 return ret;
1006 }
1007
1008 /**
1009 * @brief Reference value for gyroscope’s digital high-pass filter.[get]
1010 *
1011 * @param ctx Read / write interface definitions.(ptr)
1012 * @param buff Buffer that stores data read.(ptr)
1013 * @retval Interface status (MANDATORY: return 0 -> no Error).
1014 *
1015 */
l3gd20h_gy_filter_reference_get(const stmdev_ctx_t * ctx,uint8_t * buff)1016 int32_t l3gd20h_gy_filter_reference_get(const stmdev_ctx_t *ctx,
1017 uint8_t *buff)
1018 {
1019 int32_t ret;
1020 ret = l3gd20h_read_reg(ctx, L3GD20H_REFERENCE, buff, 1);
1021
1022 return ret;
1023 }
1024
1025 /**
1026 * @}
1027 *
1028 */
1029
1030 /**
1031 * @defgroup L3GD20H_Serialinterface
1032 * @brief This section groups all the functions concerning main
1033 * serial interface management (not auxiliary)
1034 * @{
1035 *
1036 */
1037
1038 /**
1039 * @brief SPI Serial Interface Mode selection..[set]
1040 *
1041 * @param ctx Read / write interface definitions.(ptr)
1042 * @param val Change the values of "sim" in reg L3GD20H.
1043 * @retval Interface status (MANDATORY: return 0 -> no Error).
1044 *
1045 */
l3gd20h_spi_mode_set(const stmdev_ctx_t * ctx,l3gd20h_sim_t val)1046 int32_t l3gd20h_spi_mode_set(const stmdev_ctx_t *ctx, l3gd20h_sim_t val)
1047 {
1048 l3gd20h_ctrl4_t ctrl4;
1049 int32_t ret;
1050 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
1051
1052 if (ret == 0)
1053 {
1054 ctrl4.sim = (uint8_t)val;
1055 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
1056 }
1057
1058 return ret;
1059 }
1060
1061 /**
1062 * @brief SPI Serial Interface Mode selection..[get]
1063 *
1064 * @param ctx Read / write interface definitions.(ptr)
1065 * @param val Get the values of sim in reg CTRL4.(ptr)
1066 * @retval Interface status (MANDATORY: return 0 -> no Error).
1067 *
1068 */
l3gd20h_spi_mode_get(const stmdev_ctx_t * ctx,l3gd20h_sim_t * val)1069 int32_t l3gd20h_spi_mode_get(const stmdev_ctx_t *ctx, l3gd20h_sim_t *val)
1070 {
1071 l3gd20h_ctrl4_t ctrl4;
1072 int32_t ret;
1073 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
1074
1075 switch (ctrl4.sim)
1076 {
1077 case L3GD20H_SPI_4_WIRE:
1078 *val = L3GD20H_SPI_4_WIRE;
1079 break;
1080
1081 case L3GD20H_SPI_3_WIRE:
1082 *val = L3GD20H_SPI_3_WIRE;
1083 break;
1084
1085 default:
1086 *val = L3GD20H_SPI_4_WIRE;
1087 break;
1088 }
1089
1090 return ret;
1091 }
1092
1093 /**
1094 * @brief Enable / Disable I2C interface..[set]
1095 *
1096 * @param ctx Read / write interface definitions.(ptr)
1097 * @param val Change the values of "i2c_dis" in reg L3GD20H.
1098 * @retval Interface status (MANDATORY: return 0 -> no Error).
1099 *
1100 */
l3gd20h_i2c_interface_set(const stmdev_ctx_t * ctx,l3gd20h_i2c_dis_t val)1101 int32_t l3gd20h_i2c_interface_set(const stmdev_ctx_t *ctx,
1102 l3gd20h_i2c_dis_t val)
1103 {
1104 l3gd20h_low_odr_t low_odr;
1105 int32_t ret;
1106 ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
1107
1108 if (ret == 0)
1109 {
1110 low_odr.i2c_dis = (uint8_t)val;
1111 ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
1112 }
1113
1114 return ret;
1115 }
1116
1117 /**
1118 * @brief Enable / Disable I2C interface..[get]
1119 *
1120 * @param ctx Read / write interface definitions.(ptr)
1121 * @param val Get the values of i2c_dis in reg LOW_ODR.(ptr)
1122 * @retval Interface status (MANDATORY: return 0 -> no Error).
1123 *
1124 */
l3gd20h_i2c_interface_get(const stmdev_ctx_t * ctx,l3gd20h_i2c_dis_t * val)1125 int32_t l3gd20h_i2c_interface_get(const stmdev_ctx_t *ctx,
1126 l3gd20h_i2c_dis_t *val)
1127 {
1128 l3gd20h_low_odr_t low_odr;
1129 int32_t ret;
1130 ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
1131
1132 switch (low_odr.i2c_dis)
1133 {
1134 case L3GD20H_I2C_ENABLE:
1135 *val = L3GD20H_I2C_ENABLE;
1136 break;
1137
1138 case L3GD20H_I2C_DISABLE:
1139 *val = L3GD20H_I2C_DISABLE;
1140 break;
1141
1142 default:
1143 *val = L3GD20H_I2C_ENABLE;
1144 break;
1145 }
1146
1147 return ret;
1148 }
1149 /**
1150 * @}
1151 *
1152 */
1153
1154 /**
1155 * @defgroup L3GD20H_Interruptpins
1156 * @brief This section groups all the functions that manage interrupt pins
1157 * @{
1158 *
1159 */
1160
1161 /**
1162 * @brief Route a signal on INT 2_A/G pin..[set]
1163 *
1164 * @param ctx Read / write interface definitions.(ptr)
1165 * @param val FIFO Empty interrupt on DRDY/INT2 pin..
1166 * @retval Interface status (MANDATORY: return 0 -> no Error).
1167 *
1168 */
l3gd20h_pin_int2_route_set(const stmdev_ctx_t * ctx,l3gd20h_pin_int2_rt_t val)1169 int32_t l3gd20h_pin_int2_route_set(const stmdev_ctx_t *ctx,
1170 l3gd20h_pin_int2_rt_t val)
1171 {
1172 l3gd20h_ctrl3_t ctrl3;
1173 int32_t ret;
1174 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1175
1176 if (ret == 0)
1177 {
1178 ctrl3.int2_empty = val.int2_empty;
1179 ctrl3.int2_fth = val.int2_fth;
1180 ctrl3.int2_orun = val.int2_orun;
1181 ctrl3.int2_drdy = val.int2_drdy;
1182 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1183 }
1184
1185 return ret;
1186 }
1187
1188 /**
1189 * @brief Route a signal on INT 2_A/G pin..[get]
1190 *
1191 * @param ctx Read / write interface definitions.(ptr)
1192 * @param val FIFO Empty interrupt on DRDY/INT2 pin..(ptr)
1193 * @retval Interface status (MANDATORY: return 0 -> no Error).
1194 *
1195 */
l3gd20h_pin_int2_route_get(const stmdev_ctx_t * ctx,l3gd20h_pin_int2_rt_t * val)1196 int32_t l3gd20h_pin_int2_route_get(const stmdev_ctx_t *ctx,
1197 l3gd20h_pin_int2_rt_t *val)
1198 {
1199 l3gd20h_ctrl3_t ctrl3;
1200 int32_t ret;
1201 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1202 val->int2_empty = ctrl3.int2_empty;
1203 val->int2_orun = ctrl3.int2_orun;
1204 val->int2_fth = ctrl3.int2_fth;
1205 val->int2_drdy = ctrl3.int2_drdy;
1206
1207 return ret;
1208 }
1209
1210 /**
1211 * @brief Push-pull/open drain selection on interrupt pads..[set]
1212 *
1213 * @param ctx Read / write interface definitions.(ptr)
1214 * @param val Change the values of "pp_od" in reg L3GD20H.
1215 * @retval Interface status (MANDATORY: return 0 -> no Error).
1216 *
1217 */
l3gd20h_pin_mode_set(const stmdev_ctx_t * ctx,l3gd20h_pp_od_t val)1218 int32_t l3gd20h_pin_mode_set(const stmdev_ctx_t *ctx, l3gd20h_pp_od_t val)
1219 {
1220 l3gd20h_ctrl3_t ctrl3;
1221 int32_t ret;
1222 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1223
1224 if (ret == 0)
1225 {
1226 ctrl3.pp_od = (uint8_t)val;
1227 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1228 }
1229
1230 return ret;
1231 }
1232
1233 /**
1234 * @brief Push-pull/open drain selection on interrupt pads..[get]
1235 *
1236 * @param ctx Read / write interface definitions.(ptr)
1237 * @param val Get the values of pp_od in reg CTRL3.(ptr)
1238 * @retval Interface status (MANDATORY: return 0 -> no Error).
1239 *
1240 */
l3gd20h_pin_mode_get(const stmdev_ctx_t * ctx,l3gd20h_pp_od_t * val)1241 int32_t l3gd20h_pin_mode_get(const stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val)
1242 {
1243 l3gd20h_ctrl3_t ctrl3;
1244 int32_t ret;
1245 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1246
1247 switch (ctrl3.pp_od)
1248 {
1249 case L3GD20H_PUSH_PULL:
1250 *val = L3GD20H_PUSH_PULL;
1251 break;
1252
1253 case L3GD20H_OPEN_DRAIN:
1254 *val = L3GD20H_OPEN_DRAIN;
1255 break;
1256
1257 default:
1258 *val = L3GD20H_PUSH_PULL;
1259 break;
1260 }
1261
1262 return ret;
1263 }
1264
1265 /**
1266 * @brief Interrupt active-high/low.Interrupt active-high/low..[set]
1267 *
1268 * @param ctx Read / write interface definitions.(ptr)
1269 * @param val Change the values of "h_lactive" in reg L3GD20H.
1270 * @retval Interface status (MANDATORY: return 0 -> no Error).
1271 *
1272 */
l3gd20h_pin_polarity_set(const stmdev_ctx_t * ctx,l3gd20h_pin_pol_t val)1273 int32_t l3gd20h_pin_polarity_set(const stmdev_ctx_t *ctx,
1274 l3gd20h_pin_pol_t val)
1275 {
1276 l3gd20h_low_odr_t low_odr;
1277 l3gd20h_ctrl3_t ctrl3;
1278 int32_t ret;
1279 ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
1280
1281 if (ret == 0)
1282 {
1283 low_odr.drdy_hl = (uint8_t)val;
1284 ret = l3gd20h_write_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1);
1285 }
1286
1287 if (ret == 0)
1288 {
1289 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1290 }
1291
1292 if (ret == 0)
1293 {
1294 ctrl3.h_lactive = (uint8_t)val;
1295 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1296 }
1297
1298 return ret;
1299 }
1300
1301 /**
1302 * @brief Interrupt active-high/low.Interrupt active-high/low..[get]
1303 *
1304 * @param ctx Read / write interface definitions.(ptr)
1305 * @param val Get the values of h_lactive in reg CTRL3.(ptr)
1306 * @retval Interface status (MANDATORY: return 0 -> no Error).
1307 *
1308 */
l3gd20h_pin_polarity_get(const stmdev_ctx_t * ctx,l3gd20h_pin_pol_t * val)1309 int32_t l3gd20h_pin_polarity_get(const stmdev_ctx_t *ctx,
1310 l3gd20h_pin_pol_t *val)
1311 {
1312 l3gd20h_ctrl3_t ctrl3;
1313 int32_t ret;
1314 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1315
1316 switch (ctrl3.h_lactive)
1317 {
1318 case L3GD20H_ACTIVE_HIGH:
1319 *val = L3GD20H_ACTIVE_HIGH;
1320 break;
1321
1322 case L3GD20H_ACTIVE_LOW:
1323 *val = L3GD20H_ACTIVE_LOW;
1324 break;
1325
1326 default:
1327 *val = L3GD20H_ACTIVE_HIGH;
1328 break;
1329 }
1330
1331 return ret;
1332 }
1333
1334 /**
1335 * @brief Route a signal on INT1 pin.[set]
1336 *
1337 * @param ctx Read / write interface definitions.(ptr)
1338 * @param val Boot status available on INT1 pin..
1339 * @retval Interface status (MANDATORY: return 0 -> no Error).
1340 *
1341 */
l3gd20h_pin_int1_route_set(const stmdev_ctx_t * ctx,l3gd20h_pin_int1_rt_t val)1342 int32_t l3gd20h_pin_int1_route_set(const stmdev_ctx_t *ctx,
1343 l3gd20h_pin_int1_rt_t val)
1344 {
1345 l3gd20h_ctrl3_t ctrl3;
1346 int32_t ret;
1347 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1348
1349 if (ret == 0)
1350 {
1351 ctrl3.int1_boot = val.int1_boot;
1352 ctrl3.int1_ig = val.int1_ig;
1353 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1354 }
1355
1356 return ret;
1357 }
1358
1359 /**
1360 * @brief Route a signal on INT1 pin.[get]
1361 *
1362 * @param ctx Read / write interface definitions.(ptr)
1363 * @param val Boot status available on INT1 pin..(ptr)
1364 * @retval Interface status (MANDATORY: return 0 -> no Error).
1365 *
1366 */
l3gd20h_pin_int1_route_get(const stmdev_ctx_t * ctx,l3gd20h_pin_int1_rt_t * val)1367 int32_t l3gd20h_pin_int1_route_get(const stmdev_ctx_t *ctx,
1368 l3gd20h_pin_int1_rt_t *val)
1369 {
1370 l3gd20h_ctrl3_t ctrl3;
1371 int32_t ret;
1372 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1);
1373 val->int1_boot = ctrl3.int1_boot;
1374 val->int1_ig = ctrl3.int1_ig;
1375
1376 return ret;
1377 }
1378
1379 /**
1380 * @brief Latched/pulsed interrupt..[set]
1381 *
1382 * @param ctx Read / write interface definitions.(ptr)
1383 * @param val Change the values of "lir" in reg L3GD20H.
1384 * @retval Interface status (MANDATORY: return 0 -> no Error).
1385 *
1386 */
l3gd20h_pin_notification_set(const stmdev_ctx_t * ctx,l3gd20h_lir_t val)1387 int32_t l3gd20h_pin_notification_set(const stmdev_ctx_t *ctx,
1388 l3gd20h_lir_t val)
1389 {
1390 l3gd20h_ig_cfg_t ig_cfg;
1391 int32_t ret;
1392 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
1393
1394 if (ret == 0)
1395 {
1396 ig_cfg.lir = (uint8_t)val;
1397 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
1398 }
1399
1400 return ret;
1401 }
1402
1403 /**
1404 * @brief Latched/pulsed interrupt..[get]
1405 *
1406 * @param ctx Read / write interface definitions.(ptr)
1407 * @param val Get the values of lir in reg IG_CFG.(ptr)
1408 * @retval Interface status (MANDATORY: return 0 -> no Error).
1409 *
1410 */
l3gd20h_pin_notification_get(const stmdev_ctx_t * ctx,l3gd20h_lir_t * val)1411 int32_t l3gd20h_pin_notification_get(const stmdev_ctx_t *ctx,
1412 l3gd20h_lir_t *val)
1413 {
1414 l3gd20h_ig_cfg_t ig_cfg;
1415 int32_t ret;
1416 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG,
1417 (uint8_t *)&ig_cfg, 1);
1418
1419 switch (ig_cfg.lir)
1420 {
1421 case L3GD20H_INT_PULSED:
1422 *val = L3GD20H_INT_PULSED;
1423 break;
1424
1425 case L3GD20H_INT_LATCHED:
1426 *val = L3GD20H_INT_LATCHED;
1427 break;
1428
1429 default:
1430 *val = L3GD20H_INT_PULSED;
1431 break;
1432 }
1433
1434 return ret;
1435 }
1436
1437 /**
1438 * @brief AND/OR combination of accelerometer’s interrupt events..[set]
1439 *
1440 * @param ctx Read / write interface definitions.(ptr)
1441 * @param val Change the values of "and_or" in reg L3GD20H.
1442 * @retval Interface status (MANDATORY: return 0 -> no Error).
1443 *
1444 */
l3gd20h_pin_logic_set(const stmdev_ctx_t * ctx,l3gd20h_pin_logic_t val)1445 int32_t l3gd20h_pin_logic_set(const stmdev_ctx_t *ctx,
1446 l3gd20h_pin_logic_t val)
1447 {
1448 l3gd20h_ig_cfg_t ig_cfg;
1449 int32_t ret;
1450 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
1451
1452 if (ret == 0)
1453 {
1454 ig_cfg.and_or = (uint8_t)val;
1455 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
1456 }
1457
1458 return ret;
1459 }
1460
1461 /**
1462 * @brief AND/OR combination of accelerometer’s interrupt events..[get]
1463 *
1464 * @param ctx Read / write interface definitions.(ptr)
1465 * @param val Get the values of and_or in reg IG_CFG.(ptr)
1466 * @retval Interface status (MANDATORY: return 0 -> no Error).
1467 *
1468 */
l3gd20h_pin_logic_get(const stmdev_ctx_t * ctx,l3gd20h_pin_logic_t * val)1469 int32_t l3gd20h_pin_logic_get(const stmdev_ctx_t *ctx,
1470 l3gd20h_pin_logic_t *val)
1471 {
1472 l3gd20h_ig_cfg_t ig_cfg;
1473 int32_t ret;
1474 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
1475
1476 switch (ig_cfg.and_or)
1477 {
1478 case L3GD20H_LOGIC_OR:
1479 *val = L3GD20H_LOGIC_OR;
1480 break;
1481
1482 case L3GD20H_LOGIC_AND:
1483 *val = L3GD20H_LOGIC_AND;
1484 break;
1485
1486 default:
1487 *val = L3GD20H_LOGIC_OR;
1488 break;
1489 }
1490
1491 return ret;
1492 }
1493
1494 /**
1495 * @}
1496 *
1497 */
1498
1499 /**
1500 * @defgroup L3GD20H_Interrupt on threshold
1501 * @brief This section group all the functions concerning the
1502 * interrupt on threshold configuration.
1503 * @{
1504 *
1505 */
1506
1507 /**
1508 * @brief Enable interrupt generation on threshold event..[set]
1509 *
1510 * @param ctx Read / write interface definitions.(ptr)
1511 * @param val Enable interrupt generation on gyroscope’s pitch (X)
1512 * axis low event..
1513 * @retval Interface status (MANDATORY: return 0 -> no Error).
1514 *
1515 */
l3gd20h_gy_trshld_axis_set(const stmdev_ctx_t * ctx,l3gd20h_gy_trshld_en_t val)1516 int32_t l3gd20h_gy_trshld_axis_set(const stmdev_ctx_t *ctx,
1517 l3gd20h_gy_trshld_en_t val)
1518 {
1519 l3gd20h_ig_cfg_t ig_cfg;
1520 int32_t ret;
1521 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
1522
1523 if (ret == 0)
1524 {
1525 ig_cfg.xlie = val.xlie;
1526 ig_cfg.xhie = val.xhie;
1527 ig_cfg.ylie = val.ylie;
1528 ig_cfg.yhie = val.yhie;
1529 ig_cfg.zlie = val.zlie;
1530 ig_cfg.zhie = val.zhie;
1531 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1);
1532 }
1533
1534 return ret;
1535 }
1536
1537 /**
1538 * @brief Enable interrupt generation on threshold event..[get]
1539 *
1540 * @param ctx Read / write interface definitions.(ptr)
1541 * @param val Enable interrupt generation on gyroscope’s pitch (X)
1542 * axis low event..(ptr)
1543 * @retval Interface status (MANDATORY: return 0 -> no Error).
1544 *
1545 */
l3gd20h_gy_trshld_axis_get(const stmdev_ctx_t * ctx,l3gd20h_gy_trshld_en_t * val)1546 int32_t l3gd20h_gy_trshld_axis_get(const stmdev_ctx_t *ctx,
1547 l3gd20h_gy_trshld_en_t *val)
1548 {
1549 l3gd20h_ig_cfg_t ig_cfg;
1550 int32_t ret;
1551 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG,
1552 (uint8_t *)&ig_cfg, 1);
1553 val->xlie = ig_cfg.xlie;
1554 val->xhie = ig_cfg.xhie;
1555 val->ylie = ig_cfg.ylie;
1556 val->yhie = ig_cfg.yhie;
1557 val->zlie = ig_cfg.zlie;
1558 val->zhie = ig_cfg.zhie;
1559
1560 return ret;
1561 }
1562
1563 /**
1564 * @brief Angular rate sensor interrupt on threshold source..[get]
1565 *
1566 * @param ctx Read / write interface definitions.(ptr)
1567 * @param val Pitch(X)low..(ptr)
1568 * @retval Interface status (MANDATORY: return 0 -> no Error).
1569 *
1570 */
l3gd20h_gy_trshld_src_get(const stmdev_ctx_t * ctx,l3gd20h_gy_trshld_src_t * val)1571 int32_t l3gd20h_gy_trshld_src_get(const stmdev_ctx_t *ctx,
1572 l3gd20h_gy_trshld_src_t *val)
1573 {
1574 l3gd20h_ig_src_t ig_src;
1575 int32_t ret;
1576 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_SRC, (uint8_t *)&ig_src, 1);
1577 val->xl = ig_src.xl;
1578 val->xh = ig_src.xh;
1579 val->yl = ig_src.yl;
1580 val->yh = ig_src.yh;
1581 val->zl = ig_src.zl;
1582 val->zh = ig_src.zh;
1583 val->ia = ig_src.ia;
1584
1585 return ret;
1586 }
1587
1588 /**
1589 * @brief Angular rate sensor interrupt threshold on pitch (X) axis..[set]
1590 *
1591 * @param ctx Read / write interface definitions.(ptr)
1592 * @param val Change the values of thsx in reg IG_THS_XH.
1593 * @retval Interface status (MANDATORY: return 0 -> no Error).
1594 *
1595 */
l3gd20h_gy_trshld_x_set(const stmdev_ctx_t * ctx,uint16_t val)1596 int32_t l3gd20h_gy_trshld_x_set(const stmdev_ctx_t *ctx, uint16_t val)
1597 {
1598 l3gd20h_ig_ths_xl_t ig_ths_xl;
1599 l3gd20h_ig_ths_xh_t ig_ths_xh;
1600 int32_t ret;
1601 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
1602
1603 if (ret == 0)
1604 {
1605 ig_ths_xh.thsx = (uint8_t)(val / 256U) & 0x7FU;
1606 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
1607 }
1608
1609 if (ret == 0)
1610 {
1611 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XL, (uint8_t *)&ig_ths_xl, 1);
1612 }
1613
1614 if (ret == 0)
1615 {
1616 ig_ths_xl.thsx = (uint8_t)(val - (ig_ths_xh.thsx * 256U));
1617 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_XL, (uint8_t *)&ig_ths_xl, 1);
1618 }
1619
1620 return ret;
1621 }
1622
1623 /**
1624 * @brief Angular rate sensor interrupt threshold on pitch (X) axis..[get]
1625 *
1626 * @param ctx Read / write interface definitions.(ptr)
1627 * @param val Get the values of thsx in reg IG_THS_XH.(ptr)
1628 * @retval Interface status (MANDATORY: return 0 -> no Error).
1629 *
1630 */
l3gd20h_gy_trshld_x_get(const stmdev_ctx_t * ctx,uint16_t * val)1631 int32_t l3gd20h_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val)
1632 {
1633 l3gd20h_ig_ths_xl_t ig_ths_xl;
1634 l3gd20h_ig_ths_xh_t ig_ths_xh;
1635 int32_t ret;
1636 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XL, (uint8_t *)&ig_ths_xl, 1);
1637
1638 if (ret == 0)
1639 {
1640 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
1641 *val = ig_ths_xh.thsx;
1642 *val = *val / 256U;
1643 *val += ig_ths_xl.thsx;
1644 }
1645
1646 return ret;
1647 }
1648 /**
1649 * @brief Decrement or reset counter mode selection..[set]
1650 *
1651 * @param ctx Read / write interface definitions.(ptr)
1652 * @param val Change the values of "dcrm" in reg L3GD20H.
1653 * @retval Interface status (MANDATORY: return 0 -> no Error).
1654 *
1655 */
l3gd20h_gy_trshld_mode_set(const stmdev_ctx_t * ctx,l3gd20h_dcrm_g_t val)1656 int32_t l3gd20h_gy_trshld_mode_set(const stmdev_ctx_t *ctx,
1657 l3gd20h_dcrm_g_t val)
1658 {
1659 l3gd20h_ig_ths_xh_t ig_ths_xh;
1660 int32_t ret;
1661 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
1662
1663 if (ret == 0)
1664 {
1665 ig_ths_xh.dcrm = (uint8_t)val;
1666 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
1667 }
1668
1669 return ret;
1670 }
1671
1672 /**
1673 * @brief Decrement or reset counter mode selection..[get]
1674 *
1675 * @param ctx Read / write interface definitions.(ptr)
1676 * @param val Get the values of dcrm in reg IG_THS_XH.(ptr)
1677 * @retval Interface status (MANDATORY: return 0 -> no Error).
1678 *
1679 */
l3gd20h_gy_trshld_mode_get(const stmdev_ctx_t * ctx,l3gd20h_dcrm_g_t * val)1680 int32_t l3gd20h_gy_trshld_mode_get(const stmdev_ctx_t *ctx,
1681 l3gd20h_dcrm_g_t *val)
1682 {
1683 l3gd20h_ig_ths_xh_t ig_ths_xh;
1684 int32_t ret;
1685 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1);
1686
1687 switch (ig_ths_xh.dcrm)
1688 {
1689 case L3GD20H_RESET_MODE:
1690 *val = L3GD20H_RESET_MODE;
1691 break;
1692
1693 case L3GD20H_DECREMENT_MODE:
1694 *val = L3GD20H_DECREMENT_MODE;
1695 break;
1696
1697 default:
1698 *val = L3GD20H_RESET_MODE;
1699 break;
1700 }
1701
1702 return ret;
1703 }
1704
1705 /**
1706 * @brief Angular rate sensor interrupt threshold on roll (Y) axis.[set]
1707 *
1708 * @param ctx Read / write interface definitions.(ptr)
1709 * @param val Change the values of thsy in reg IG_THS_YH.
1710 * @retval Interface status (MANDATORY: return 0 -> no Error).
1711 *
1712 */
l3gd20h_gy_trshld_y_set(const stmdev_ctx_t * ctx,uint16_t val)1713 int32_t l3gd20h_gy_trshld_y_set(const stmdev_ctx_t *ctx, uint16_t val)
1714 {
1715 l3gd20h_ig_ths_yh_t ig_ths_yh;
1716 l3gd20h_ig_ths_yl_t ig_ths_yl;
1717 int32_t ret;
1718 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t *)&ig_ths_yh, 1);
1719
1720 if (ret == 0)
1721 {
1722 ig_ths_yh.thsy = (uint8_t)(val / 256U) & 0x7FU;
1723 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t *)&ig_ths_yh, 1);
1724 }
1725
1726 if (ret == 0)
1727 {
1728 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YL, (uint8_t *)&ig_ths_yl, 1);
1729 }
1730
1731 if (ret == 0)
1732 {
1733 ig_ths_yl.thsy = (uint8_t)(val - (ig_ths_yh.thsy * 256U));
1734 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_YL, (uint8_t *)&ig_ths_yl, 1);
1735 }
1736
1737 return ret;
1738 }
1739
1740 /**
1741 * @brief Angular rate sensor interrupt threshold on roll (Y) axis.[get]
1742 *
1743 * @param ctx Read / write interface definitions.(ptr)
1744 * @param val Get the values of thsy in reg IG_THS_YH.(ptr)
1745 * @retval Interface status (MANDATORY: return 0 -> no Error).
1746 *
1747 */
l3gd20h_gy_trshld_y_get(const stmdev_ctx_t * ctx,uint16_t * val)1748 int32_t l3gd20h_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val)
1749 {
1750 l3gd20h_ig_ths_yh_t ig_ths_yh;
1751 l3gd20h_ig_ths_yl_t ig_ths_yl;
1752 int32_t ret;
1753 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YL, (uint8_t *)&ig_ths_yl, 1);
1754
1755 if (ret == 0)
1756 {
1757 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t *)&ig_ths_yh, 1);
1758 *val = ig_ths_yh.thsy;
1759 *val = *val / 256U;
1760 *val += ig_ths_yl.thsy;
1761 }
1762
1763 return ret;
1764 }
1765
1766 /**
1767 * @brief Angular rate sensor interrupt threshold on roll (Z) axis.[set]
1768 *
1769 * @param ctx Read / write interface definitions.(ptr)
1770 * @param val Change the values of thsz in reg IG_THS_ZH.
1771 * @retval Interface status (MANDATORY: return 0 -> no Error).
1772 *
1773 */
l3gd20h_gy_trshld_z_set(const stmdev_ctx_t * ctx,uint16_t val)1774 int32_t l3gd20h_gy_trshld_z_set(const stmdev_ctx_t *ctx, uint16_t val)
1775 {
1776 l3gd20h_ig_ths_zh_t ig_ths_zh;
1777 l3gd20h_ig_ths_zl_t ig_ths_zl;
1778 int32_t ret;
1779 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t *)&ig_ths_zh, 1);
1780
1781 if (ret == 0)
1782 {
1783 ig_ths_zh.thsz = (uint8_t)(val / 256U) & 0x7FU;
1784 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t *)&ig_ths_zh, 1);
1785 }
1786
1787 if (ret == 0)
1788 {
1789 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZL, (uint8_t *)&ig_ths_zl, 1);
1790 }
1791
1792 if (ret == 0)
1793 {
1794 ig_ths_zl.thsz = (uint8_t)(val - (ig_ths_zh.thsz * 256U));
1795 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_THS_ZL, (uint8_t *)&ig_ths_zl, 1);
1796 }
1797
1798 return ret;
1799 }
1800
1801 /**
1802 * @brief Angular rate sensor interrupt threshold on roll (Z) axis.[get]
1803 *
1804 * @param ctx Read / write interface definitions.(ptr)
1805 * @param val Get the values of thsz in reg IG_THS_ZH.(ptr)
1806 * @retval Interface status (MANDATORY: return 0 -> no Error).
1807 *
1808 */
l3gd20h_gy_trshld_z_get(const stmdev_ctx_t * ctx,uint16_t * val)1809 int32_t l3gd20h_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val)
1810 {
1811 l3gd20h_ig_ths_zh_t ig_ths_zh;
1812 l3gd20h_ig_ths_zl_t ig_ths_zl;
1813 int32_t ret;
1814 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZL, (uint8_t *)&ig_ths_zl, 1);
1815
1816 if (ret == 0)
1817 {
1818 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t *)&ig_ths_zh, 1);
1819 *val = ig_ths_zh.thsz;
1820 *val = *val / 256U;
1821 *val += ig_ths_zh.thsz;
1822 }
1823
1824 return ret;
1825 }
1826
1827 /**
1828 * @brief Enter/exit interrupt duration value..[set]
1829 *
1830 * @param ctx Read / write interface definitions.(ptr)
1831 * @param val Change the values of d in reg IG_DURATION.
1832 * @retval Interface status (MANDATORY: return 0 -> no Error).
1833 *
1834 */
l3gd20h_gy_trshld_min_sample_set(const stmdev_ctx_t * ctx,uint8_t val)1835 int32_t l3gd20h_gy_trshld_min_sample_set(const stmdev_ctx_t *ctx,
1836 uint8_t val)
1837 {
1838 l3gd20h_ig_duration_t ig_duration;
1839 int32_t ret;
1840 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_DURATION,
1841 (uint8_t *)&ig_duration, 1);
1842
1843 if (ret == 0)
1844 {
1845 ig_duration.d = val;
1846
1847 if (val != 0x00U)
1848 {
1849 ig_duration.wait = PROPERTY_ENABLE;
1850 }
1851
1852 else
1853 {
1854 ig_duration.wait = PROPERTY_DISABLE;
1855 }
1856
1857 ret = l3gd20h_write_reg(ctx, L3GD20H_IG_DURATION,
1858 (uint8_t *)&ig_duration, 1);
1859 }
1860
1861 return ret;
1862 }
1863
1864 /**
1865 * @brief Enter/exit interrupt duration value..[get]
1866 *
1867 * @param ctx Read / write interface definitions.(ptr)
1868 * @param val Get the values of d in reg IG_DURATION.(ptr)
1869 * @retval Interface status (MANDATORY: return 0 -> no Error).
1870 *
1871 */
l3gd20h_gy_trshld_min_sample_get(const stmdev_ctx_t * ctx,uint8_t * val)1872 int32_t l3gd20h_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx,
1873 uint8_t *val)
1874 {
1875 l3gd20h_ig_duration_t ig_duration;
1876 int32_t ret;
1877 ret = l3gd20h_read_reg(ctx, L3GD20H_IG_DURATION,
1878 (uint8_t *)&ig_duration, 1);
1879 *val = ig_duration.d;
1880
1881 return ret;
1882 }
1883
1884 /**
1885 * @}
1886 *
1887 */
1888
1889 /**
1890 * @defgroup L3GD20H_Fifo
1891 * @brief This section group all the functions concerning the fifo usage.
1892 * @{
1893 *
1894 */
1895
1896 /**
1897 * @brief Sensing chain FIFO stop values memorization at threshold level.[set]
1898 *
1899 * @param ctx Read / write interface definitions.(ptr)
1900 * @param val Change the values of stoponfth in reg CTRL5.
1901 * @retval Interface status (MANDATORY: return 0 -> no Error).
1902 *
1903 */
l3gd20h_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)1904 int32_t l3gd20h_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
1905 {
1906 l3gd20h_ctrl5_t ctrl5;
1907 int32_t ret;
1908 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
1909
1910 if (ret == 0)
1911 {
1912 ctrl5.stoponfth = val;
1913 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
1914 }
1915
1916 return ret;
1917 }
1918
1919 /**
1920 * @brief Sensing chain FIFO stop values memorization at threshold level.[get]
1921 *
1922 * @param ctx Read / write interface definitions.(ptr)
1923 * @param val Get the values of stoponfth in reg CTRL5.(ptr)
1924 * @retval Interface status (MANDATORY: return 0 -> no Error).
1925 *
1926 */
l3gd20h_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)1927 int32_t l3gd20h_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
1928 {
1929 l3gd20h_ctrl5_t ctrl5;
1930 int32_t ret;
1931 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
1932 *val = ctrl5.stoponfth;
1933
1934 return ret;
1935 }
1936 /**
1937 * @brief FIFO mode selection..[set]
1938 *
1939 * @param ctx Read / write interface definitions.(ptr)
1940 * @param val Change the values of "fifo_en" in reg L3GD20H.
1941 * @retval Interface status (MANDATORY: return 0 -> no Error).
1942 *
1943 */
l3gd20h_fifo_mode_set(const stmdev_ctx_t * ctx,l3gd20h_fifo_m_t val)1944 int32_t l3gd20h_fifo_mode_set(const stmdev_ctx_t *ctx, l3gd20h_fifo_m_t val)
1945 {
1946 l3gd20h_ctrl5_t ctrl5;
1947 l3gd20h_fifo_ctrl_t fifo_ctrl;
1948 int32_t ret;
1949 ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1950
1951 if (ret == 0)
1952 {
1953 fifo_ctrl.fm = ((uint8_t)val & 0x07U);
1954 ret = l3gd20h_write_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1955 }
1956
1957 if (ret == 0)
1958 {
1959 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
1960 }
1961
1962 if (ret == 0)
1963 {
1964 ctrl5.fifo_en = (((uint8_t)val & 0x10U) >> 4);
1965 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
1966 }
1967
1968 return ret;
1969 }
1970
1971 /**
1972 * @brief FIFO mode selection..[get]
1973 *
1974 * @param ctx Read / write interface definitions.(ptr)
1975 * @param val Get the values of fifo_en in reg CTRL5.(ptr)
1976 * @retval Interface status (MANDATORY: return 0 -> no Error).
1977 *
1978 */
l3gd20h_fifo_mode_get(const stmdev_ctx_t * ctx,l3gd20h_fifo_m_t * val)1979 int32_t l3gd20h_fifo_mode_get(const stmdev_ctx_t *ctx,
1980 l3gd20h_fifo_m_t *val)
1981 {
1982 l3gd20h_ctrl5_t ctrl5;
1983 l3gd20h_fifo_ctrl_t fifo_ctrl;
1984 int32_t ret;
1985 ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1986
1987 if (ret == 0)
1988 {
1989 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1);
1990 }
1991
1992 switch ((ctrl5.fifo_en << 4) + fifo_ctrl.fm)
1993 {
1994 case L3GD20H_BYPASS_MODE:
1995 *val = L3GD20H_BYPASS_MODE;
1996 break;
1997
1998 case L3GD20H_FIFO_MODE:
1999 *val = L3GD20H_FIFO_MODE;
2000 break;
2001
2002 case L3GD20H_STREAM_MODE:
2003 *val = L3GD20H_STREAM_MODE;
2004 break;
2005
2006 case L3GD20H_STREAM_TO_FIFO_MODE:
2007 *val = L3GD20H_STREAM_TO_FIFO_MODE;
2008 break;
2009
2010 case L3GD20H_BYPASS_TO_STREAM_MODE:
2011 *val = L3GD20H_BYPASS_TO_STREAM_MODE;
2012 break;
2013
2014 case L3GD20H_BYPASS_TO_FIFO_MODE:
2015 *val = L3GD20H_BYPASS_TO_FIFO_MODE;
2016 break;
2017
2018 default:
2019 *val = L3GD20H_BYPASS_MODE;
2020 break;
2021 }
2022
2023 return ret;
2024 }
2025 /**
2026 * @brief FIFO watermark level selection..[set]
2027 *
2028 * @param ctx Read / write interface definitions.(ptr)
2029 * @param val Change the values of fth in reg FIFO_CTRL.
2030 * @retval Interface status (MANDATORY: return 0 -> no Error).
2031 *
2032 */
l3gd20h_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)2033 int32_t l3gd20h_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
2034 {
2035 l3gd20h_fifo_ctrl_t fifo_ctrl;
2036 int32_t ret;
2037 ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
2038
2039 if (ret == 0)
2040 {
2041 fifo_ctrl.fth = val;
2042 ret = l3gd20h_write_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
2043 }
2044
2045 return ret;
2046 }
2047
2048 /**
2049 * @brief FIFO watermark level selection..[get]
2050 *
2051 * @param ctx Read / write interface definitions.(ptr)
2052 * @param val Get the values of fth in reg FIFO_CTRL.(ptr)
2053 * @retval Interface status (MANDATORY: return 0 -> no Error).
2054 *
2055 */
l3gd20h_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)2056 int32_t l3gd20h_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
2057 {
2058 l3gd20h_fifo_ctrl_t fifo_ctrl;
2059 int32_t ret;
2060 ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
2061 *val = fifo_ctrl.fth;
2062
2063 return ret;
2064 }
2065
2066 /**
2067 * @brief FIFO source register..[get]
2068 *
2069 * @param ctx Read / write interface definitions.(ptr)
2070 * @param val FIFO stored data level of the unread samples..(ptr)
2071 * @retval Interface status (MANDATORY: return 0 -> no Error).
2072 *
2073 */
l3gd20h_fifo_src_get(const stmdev_ctx_t * ctx,l3gd20h_fifo_srs_t * val)2074 int32_t l3gd20h_fifo_src_get(const stmdev_ctx_t *ctx,
2075 l3gd20h_fifo_srs_t *val)
2076 {
2077 l3gd20h_fifo_src_t fifo_src;
2078 int32_t ret;
2079 ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1);
2080 val->fss = fifo_src.fss;
2081 val->empty = fifo_src.empty;
2082 val->ovrn = fifo_src.ovrn;
2083 val->fth = fifo_src.fth;
2084
2085 return ret;
2086 }
2087
2088 /**
2089 * @brief FIFO stored data level of the unread samples..[get]
2090 *
2091 * @param ctx Read / write interface definitions.(ptr)
2092 * @param val Iet the values of "fss" in reg FIFO_SRC.(ptr)
2093 * @retval Interface status (MANDATORY: return 0 -> no Error).
2094 *
2095 */
l3gd20h_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)2096 int32_t l3gd20h_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
2097 {
2098 l3gd20h_fifo_src_t fifo_src;
2099 int32_t ret;
2100 ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1);
2101 *val = fifo_src.fss;
2102
2103 return ret;
2104 }
2105
2106 /**
2107 * @brief FIFOfullstatus.[get]
2108 *
2109 * @param ctx Read / write interface definitions.(ptr)
2110 * @param val Iet the values of "fss" in reg FIFO_SRC.(ptr)
2111 * @retval Interface status (MANDATORY: return 0 -> no Error).
2112 *
2113 */
l3gd20h_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2114 int32_t l3gd20h_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2115 {
2116 l3gd20h_fifo_src_t fifo_src;
2117 int32_t ret;
2118 ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1);
2119 *val = fifo_src.fss;
2120
2121 return ret;
2122 }
2123
2124 /**
2125 * @brief FIFO watermark status..[get]
2126 *
2127 * @param ctx Read / write interface definitions.(ptr)
2128 * @param val Iet the values of "fth" in reg FIFO_SRC.(ptr)
2129 * @retval Interface status (MANDATORY: return 0 -> no Error).
2130 *
2131 */
l3gd20h_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2132 int32_t l3gd20h_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2133 {
2134 l3gd20h_fifo_src_t fifo_src;
2135 int32_t ret;
2136 ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1);
2137 *val = fifo_src.fth;
2138
2139 return ret;
2140 }
2141
2142 /**
2143 * @}
2144 *
2145 */
2146
2147 /**
2148 * @defgroup L3GD20H_DENPin
2149 * @brief This section group all the functions concerning DEN pin usage.
2150 * @{
2151 *
2152 */
2153
2154 /**
2155 * @brief DEN pin mode..[set]
2156 *
2157 * @param ctx Read / write interface definitions.(ptr)
2158 * @param val Change the values of "lvlen" in reg L3GD20H.
2159 * @retval Interface status (MANDATORY: return 0 -> no Error).
2160 *
2161 */
l3gd20h_den_mode_set(const stmdev_ctx_t * ctx,l3gd20h_den_md_t val)2162 int32_t l3gd20h_den_mode_set(const stmdev_ctx_t *ctx, l3gd20h_den_md_t val)
2163 {
2164 l3gd20h_ctrl2_t ctrl2;
2165 l3gd20h_ctrl4_t ctrl4;
2166 int32_t ret;
2167 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
2168
2169 if (ret == 0)
2170 {
2171 ctrl4.impen = (uint8_t)val & 0x01U;
2172 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
2173 }
2174
2175 if (ret == 0)
2176 {
2177 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
2178 }
2179
2180 if (ret == 0)
2181 {
2182 ctrl2.lvlen = ((uint8_t)val & 0x04U) >> 2;
2183 ctrl2.extren = ((uint8_t)val & 0x02U) >> 1;
2184 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
2185 }
2186
2187 return ret;
2188 }
2189
2190 /**
2191 * @brief DEN pin mode..[get]
2192 *
2193 * @param ctx Read / write interface definitions.(ptr)
2194 * @param val Get the values of lvlen in reg CTRL2.(ptr)
2195 * @retval Interface status (MANDATORY: return 0 -> no Error).
2196 *
2197 */
l3gd20h_den_mode_get(const stmdev_ctx_t * ctx,l3gd20h_den_md_t * val)2198 int32_t l3gd20h_den_mode_get(const stmdev_ctx_t *ctx, l3gd20h_den_md_t *val)
2199 {
2200 l3gd20h_ctrl2_t ctrl2;
2201 l3gd20h_ctrl4_t ctrl4;
2202 int32_t ret;
2203 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
2204
2205 if (ret == 0)
2206 {
2207 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1);
2208 }
2209
2210 switch ((ctrl2.lvlen << 2) + (ctrl2.extren << 1) + ctrl4.impen)
2211 {
2212 case L3GD20H_DEN_DISABLE:
2213 *val = L3GD20H_DEN_DISABLE;
2214 break;
2215
2216 case L3GD20H_DEN_ON_LEVEL_TRIGGER:
2217 *val = L3GD20H_DEN_ON_LEVEL_TRIGGER;
2218 break;
2219
2220 case L3GD20H_DEN_ON_EDGE_TRIGGER:
2221 *val = L3GD20H_DEN_ON_EDGE_TRIGGER;
2222 break;
2223
2224 case L3GD20H_DEN_IMPULSE_TRIGGER:
2225 *val = L3GD20H_DEN_IMPULSE_TRIGGER;
2226 break;
2227
2228 default:
2229 *val = L3GD20H_DEN_DISABLE;
2230 break;
2231 }
2232
2233 return ret;
2234 }
2235
2236 /**
2237 * @}
2238 *
2239 */
2240
2241 /**
2242 * @defgroup L3GD20H_Selftest
2243 * @brief This section groups all the functions that manage self
2244 * test configuration
2245 * @{
2246 *
2247 */
2248
2249 /**
2250 * @brief Enable/disable self-test mode for gyroscope..[set]
2251 *
2252 * @param ctx Read / write interface definitions.(ptr)
2253 * @param val Change the values of "st" in reg L3GD20H.
2254 * @retval Interface status (MANDATORY: return 0 -> no Error).
2255 *
2256 */
l3gd20h_gy_self_test_set(const stmdev_ctx_t * ctx,l3gd20h_st_t val)2257 int32_t l3gd20h_gy_self_test_set(const stmdev_ctx_t *ctx, l3gd20h_st_t val)
2258 {
2259 l3gd20h_ctrl4_t ctrl4;
2260 int32_t ret;
2261 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
2262
2263 if (ret == 0)
2264 {
2265 ctrl4.st = (uint8_t)val;
2266 ret = l3gd20h_write_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
2267 }
2268
2269 return ret;
2270 }
2271
2272 /**
2273 * @brief Enable/disable self-test mode for gyroscope..[get]
2274 *
2275 * @param ctx Read / write interface definitions.(ptr)
2276 * @param val Get the values of st in reg CTRL4.(ptr)
2277 * @retval Interface status (MANDATORY: return 0 -> no Error).
2278 *
2279 */
l3gd20h_gy_self_test_get(const stmdev_ctx_t * ctx,l3gd20h_st_t * val)2280 int32_t l3gd20h_gy_self_test_get(const stmdev_ctx_t *ctx, l3gd20h_st_t *val)
2281 {
2282 l3gd20h_ctrl4_t ctrl4;
2283 int32_t ret;
2284 ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1);
2285
2286 switch (ctrl4.st)
2287 {
2288 case L3GD20H_ST_DISABLE:
2289 *val = L3GD20H_ST_DISABLE;
2290 break;
2291
2292 case L3GD20H_ST_POSITIVE:
2293 *val = L3GD20H_ST_POSITIVE;
2294 break;
2295
2296 case L3GD20H_ST_NEGATIVE:
2297 *val = L3GD20H_ST_NEGATIVE;
2298 break;
2299
2300 default:
2301 *val = L3GD20H_ST_DISABLE;
2302 break;
2303 }
2304
2305 return ret;
2306 }
2307
2308 /**
2309 * @}
2310 *
2311 */
2312
2313 /**
2314 * @}
2315 *
2316 */
2317
2318 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2319
