1 /** 2 ****************************************************************************** 3 * @file ism330dlc_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ism330dlc_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ISM330DLC_REGS_H 23 #define ISM330DLC_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ISM330DLC 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ISM330DLC_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define ISM330DLC_I2C_ADD_L 0xD5U 173 #define ISM330DLC_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define ISM330DLC_ID 0x6AU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define ISM330DLC_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 7; 188 uint8_t func_cfg_en : 1; 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t func_cfg_en : 1; 191 uint8_t not_used_01 : 7; 192 #endif /* DRV_BYTE_ORDER */ 193 } ism330dlc_func_cfg_access_t; 194 195 #define ISM330DLC_SENSOR_SYNC_TIME_FRAME 0x04U 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t tph : 4; 200 uint8_t not_used_01 : 4; 201 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 202 uint8_t not_used_01 : 4; 203 uint8_t tph : 4; 204 #endif /* DRV_BYTE_ORDER */ 205 } ism330dlc_sensor_sync_time_frame_t; 206 207 #define ISM330DLC_SENSOR_SYNC_RES_RATIO 0x05U 208 typedef struct 209 { 210 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 211 uint8_t rr : 2; 212 uint8_t not_used_01 : 6; 213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 214 uint8_t not_used_01 : 6; 215 uint8_t rr : 2; 216 #endif /* DRV_BYTE_ORDER */ 217 } ism330dlc_sensor_sync_res_ratio_t; 218 219 #define ISM330DLC_FIFO_CTRL1 0x06U 220 typedef struct 221 { 222 uint8_t fth : 8; /* + FIFO_CTRL2(fth) */ 223 } ism330dlc_fifo_ctrl1_t; 224 225 #define ISM330DLC_FIFO_CTRL2 0x07U 226 typedef struct 227 { 228 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 229 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 230 uint8_t fifo_temp_en : 1; 231 uint8_t not_used_01 : 4; 232 uint8_t fifo_timer_en : 1; 233 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 234 uint8_t fifo_timer_en : 1; 235 uint8_t not_used_01 : 4; 236 uint8_t fifo_temp_en : 1; 237 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 238 #endif /* DRV_BYTE_ORDER */ 239 } ism330dlc_fifo_ctrl2_t; 240 241 #define ISM330DLC_FIFO_CTRL3 0x08U 242 typedef struct 243 { 244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 245 uint8_t dec_fifo_xl : 3; 246 uint8_t dec_fifo_gyro : 3; 247 uint8_t not_used_01 : 2; 248 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 249 uint8_t not_used_01 : 2; 250 uint8_t dec_fifo_gyro : 3; 251 uint8_t dec_fifo_xl : 3; 252 #endif /* DRV_BYTE_ORDER */ 253 } ism330dlc_fifo_ctrl3_t; 254 255 #define ISM330DLC_FIFO_CTRL4 0x09U 256 typedef struct 257 { 258 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 259 uint8_t dec_ds3_fifo : 3; 260 uint8_t dec_ds4_fifo : 3; 261 uint8_t only_high_data : 1; 262 uint8_t stop_on_fth : 1; 263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 264 uint8_t stop_on_fth : 1; 265 uint8_t only_high_data : 1; 266 uint8_t dec_ds4_fifo : 3; 267 uint8_t dec_ds3_fifo : 3; 268 #endif /* DRV_BYTE_ORDER */ 269 } ism330dlc_fifo_ctrl4_t; 270 271 #define ISM330DLC_FIFO_CTRL5 0x0AU 272 typedef struct 273 { 274 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 275 uint8_t fifo_mode : 3; 276 uint8_t odr_fifo : 4; 277 uint8_t not_used_01 : 1; 278 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 279 uint8_t not_used_01 : 1; 280 uint8_t odr_fifo : 4; 281 uint8_t fifo_mode : 3; 282 #endif /* DRV_BYTE_ORDER */ 283 } ism330dlc_fifo_ctrl5_t; 284 285 #define ISM330DLC_DRDY_PULSE_CFG 0x0BU 286 typedef struct 287 { 288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 289 uint8_t not_used_01 : 7; 290 uint8_t drdy_pulsed : 1; 291 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 292 uint8_t drdy_pulsed : 1; 293 uint8_t not_used_01 : 7; 294 #endif /* DRV_BYTE_ORDER */ 295 } ism330dlc_drdy_pulse_cfg_t; 296 297 #define ISM330DLC_INT1_CTRL 0x0DU 298 typedef struct 299 { 300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 301 uint8_t int1_drdy_xl : 1; 302 uint8_t int1_drdy_g : 1; 303 uint8_t int1_boot : 1; 304 uint8_t int1_fth : 1; 305 uint8_t int1_fifo_ovr : 1; 306 uint8_t int1_full_flag : 1; 307 uint8_t not_used_01 : 2; 308 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 309 uint8_t not_used_01 : 2; 310 uint8_t int1_full_flag : 1; 311 uint8_t int1_fifo_ovr : 1; 312 uint8_t int1_fth : 1; 313 uint8_t int1_boot : 1; 314 uint8_t int1_drdy_g : 1; 315 uint8_t int1_drdy_xl : 1; 316 #endif /* DRV_BYTE_ORDER */ 317 } ism330dlc_int1_ctrl_t; 318 319 #define ISM330DLC_INT2_CTRL 0x0EU 320 typedef struct 321 { 322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 323 uint8_t int2_drdy_xl : 1; 324 uint8_t int2_drdy_g : 1; 325 uint8_t int2_drdy_temp : 1; 326 uint8_t int2_fth : 1; 327 uint8_t int2_fifo_ovr : 1; 328 uint8_t int2_full_flag : 1; 329 uint8_t not_used_01 : 2; 330 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 331 uint8_t not_used_01 : 2; 332 uint8_t int2_full_flag : 1; 333 uint8_t int2_fifo_ovr : 1; 334 uint8_t int2_fth : 1; 335 uint8_t int2_drdy_temp : 1; 336 uint8_t int2_drdy_g : 1; 337 uint8_t int2_drdy_xl : 1; 338 #endif /* DRV_BYTE_ORDER */ 339 } ism330dlc_int2_ctrl_t; 340 341 #define ISM330DLC_WHO_AM_I 0x0FU 342 #define ISM330DLC_CTRL1_XL 0x10U 343 typedef struct 344 { 345 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 346 uint8_t bw0_xl : 1; 347 uint8_t lpf1_bw_sel : 1; 348 uint8_t fs_xl : 2; 349 uint8_t odr_xl : 4; 350 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 351 uint8_t odr_xl : 4; 352 uint8_t fs_xl : 2; 353 uint8_t lpf1_bw_sel : 1; 354 uint8_t bw0_xl : 1; 355 #endif /* DRV_BYTE_ORDER */ 356 } ism330dlc_ctrl1_xl_t; 357 358 #define ISM330DLC_CTRL2_G 0x11U 359 typedef struct 360 { 361 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 362 uint8_t not_used_01 : 1; 363 uint8_t fs_g : 3; /* fs_g + fs_125 */ 364 uint8_t odr_g : 4; 365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 366 uint8_t odr_g : 4; 367 uint8_t fs_g : 3; /* fs_g + fs_125 */ 368 uint8_t not_used_01 : 1; 369 #endif /* DRV_BYTE_ORDER */ 370 } ism330dlc_ctrl2_g_t; 371 372 #define ISM330DLC_CTRL3_C 0x12U 373 typedef struct 374 { 375 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 376 uint8_t sw_reset : 1; 377 uint8_t ble : 1; 378 uint8_t if_inc : 1; 379 uint8_t sim : 1; 380 uint8_t pp_od : 1; 381 uint8_t h_lactive : 1; 382 uint8_t bdu : 1; 383 uint8_t boot : 1; 384 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 385 uint8_t boot : 1; 386 uint8_t bdu : 1; 387 uint8_t h_lactive : 1; 388 uint8_t pp_od : 1; 389 uint8_t sim : 1; 390 uint8_t if_inc : 1; 391 uint8_t ble : 1; 392 uint8_t sw_reset : 1; 393 #endif /* DRV_BYTE_ORDER */ 394 } ism330dlc_ctrl3_c_t; 395 396 #define ISM330DLC_CTRL4_C 0x13U 397 typedef struct 398 { 399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 400 uint8_t not_used_01 : 1; 401 uint8_t lpf1_sel_g : 1; 402 uint8_t i2c_disable : 1; 403 uint8_t drdy_mask : 1; 404 uint8_t den_drdy_int1 : 1; 405 uint8_t int2_on_int1 : 1; 406 uint8_t sleep : 1; 407 uint8_t den_xl_en : 1; 408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 409 uint8_t den_xl_en : 1; 410 uint8_t sleep : 1; 411 uint8_t int2_on_int1 : 1; 412 uint8_t den_drdy_int1 : 1; 413 uint8_t drdy_mask : 1; 414 uint8_t i2c_disable : 1; 415 uint8_t lpf1_sel_g : 1; 416 uint8_t not_used_01 : 1; 417 #endif /* DRV_BYTE_ORDER */ 418 } ism330dlc_ctrl4_c_t; 419 420 #define ISM330DLC_CTRL5_C 0x14U 421 typedef struct 422 { 423 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 424 uint8_t st_xl : 2; 425 uint8_t st_g : 2; 426 uint8_t den_lh : 1; 427 uint8_t rounding : 3; 428 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 429 uint8_t rounding : 3; 430 uint8_t den_lh : 1; 431 uint8_t st_g : 2; 432 uint8_t st_xl : 2; 433 #endif /* DRV_BYTE_ORDER */ 434 } ism330dlc_ctrl5_c_t; 435 436 #define ISM330DLC_CTRL6_C 0x15U 437 typedef struct 438 { 439 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 440 uint8_t ftype : 2; 441 uint8_t not_used_01 : 1; 442 uint8_t usr_off_w : 1; 443 uint8_t xl_hm_mode : 1; 444 uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ 445 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 446 uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ 447 uint8_t xl_hm_mode : 1; 448 uint8_t usr_off_w : 1; 449 uint8_t not_used_01 : 1; 450 uint8_t ftype : 2; 451 #endif /* DRV_BYTE_ORDER */ 452 } ism330dlc_ctrl6_c_t; 453 454 #define ISM330DLC_CTRL7_G 0x16U 455 typedef struct 456 { 457 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 458 uint8_t not_used_01 : 2; 459 uint8_t rounding_status : 1; 460 uint8_t not_used_02 : 1; 461 uint8_t hpm_g : 2; 462 uint8_t hp_en_g : 1; 463 uint8_t g_hm_mode : 1; 464 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 465 uint8_t g_hm_mode : 1; 466 uint8_t hp_en_g : 1; 467 uint8_t hpm_g : 2; 468 uint8_t not_used_02 : 1; 469 uint8_t rounding_status : 1; 470 uint8_t not_used_01 : 2; 471 #endif /* DRV_BYTE_ORDER */ 472 } ism330dlc_ctrl7_g_t; 473 474 #define ISM330DLC_CTRL8_XL 0x17U 475 typedef struct 476 { 477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 478 uint8_t low_pass_on_6d : 1; 479 uint8_t not_used_01 : 1; 480 uint8_t hp_slope_xl_en : 1; 481 uint8_t input_composite : 1; 482 uint8_t hp_ref_mode : 1; 483 uint8_t hpcf_xl : 2; 484 uint8_t lpf2_xl_en : 1; 485 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 486 uint8_t lpf2_xl_en : 1; 487 uint8_t hpcf_xl : 2; 488 uint8_t hp_ref_mode : 1; 489 uint8_t input_composite : 1; 490 uint8_t hp_slope_xl_en : 1; 491 uint8_t not_used_01 : 1; 492 uint8_t low_pass_on_6d : 1; 493 #endif /* DRV_BYTE_ORDER */ 494 } ism330dlc_ctrl8_xl_t; 495 496 #define ISM330DLC_CTRL9_XL 0x18U 497 typedef struct 498 { 499 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 500 uint8_t not_used_01 : 2; 501 uint8_t soft_en : 1; 502 uint8_t not_used_02 : 1; 503 uint8_t den_xl_g : 1; 504 uint8_t den_z : 1; 505 uint8_t den_y : 1; 506 uint8_t den_x : 1; 507 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 508 uint8_t den_x : 1; 509 uint8_t den_y : 1; 510 uint8_t den_z : 1; 511 uint8_t den_xl_g : 1; 512 uint8_t not_used_02 : 1; 513 uint8_t soft_en : 1; 514 uint8_t not_used_01 : 2; 515 #endif /* DRV_BYTE_ORDER */ 516 } ism330dlc_ctrl9_xl_t; 517 518 #define ISM330DLC_CTRL10_C 0x19U 519 typedef struct 520 { 521 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 522 uint8_t not_used_01 : 2; 523 uint8_t func_en : 1; 524 uint8_t tilt_en : 1; 525 uint8_t not_used_02 : 1; 526 uint8_t timer_en : 1; 527 uint8_t not_used_03 : 2; 528 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 529 uint8_t not_used_03 : 2; 530 uint8_t timer_en : 1; 531 uint8_t not_used_02 : 1; 532 uint8_t tilt_en : 1; 533 uint8_t func_en : 1; 534 uint8_t not_used_01 : 2; 535 #endif /* DRV_BYTE_ORDER */ 536 } ism330dlc_ctrl10_c_t; 537 538 #define ISM330DLC_MASTER_CONFIG 0x1AU 539 typedef struct 540 { 541 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 542 uint8_t master_on : 1; 543 uint8_t iron_en : 1; 544 uint8_t pass_through_mode : 1; 545 uint8_t pull_up_en : 1; 546 uint8_t start_config : 1; 547 uint8_t not_used_01 : 1; 548 uint8_t data_valid_sel_fifo : 1; 549 uint8_t drdy_on_int1 : 1; 550 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 551 uint8_t drdy_on_int1 : 1; 552 uint8_t data_valid_sel_fifo : 1; 553 uint8_t not_used_01 : 1; 554 uint8_t start_config : 1; 555 uint8_t pull_up_en : 1; 556 uint8_t pass_through_mode : 1; 557 uint8_t iron_en : 1; 558 uint8_t master_on : 1; 559 #endif /* DRV_BYTE_ORDER */ 560 } ism330dlc_master_config_t; 561 562 #define ISM330DLC_WAKE_UP_SRC 0x1BU 563 typedef struct 564 { 565 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 566 uint8_t z_wu : 1; 567 uint8_t y_wu : 1; 568 uint8_t x_wu : 1; 569 uint8_t wu_ia : 1; 570 uint8_t sleep_state_ia : 1; 571 uint8_t ff_ia : 1; 572 uint8_t not_used_01 : 2; 573 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 574 uint8_t not_used_01 : 2; 575 uint8_t ff_ia : 1; 576 uint8_t sleep_state_ia : 1; 577 uint8_t wu_ia : 1; 578 uint8_t x_wu : 1; 579 uint8_t y_wu : 1; 580 uint8_t z_wu : 1; 581 #endif /* DRV_BYTE_ORDER */ 582 } ism330dlc_wake_up_src_t; 583 584 #define ISM330DLC_TAP_SRC 0x1CU 585 typedef struct 586 { 587 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 588 uint8_t z_tap : 1; 589 uint8_t y_tap : 1; 590 uint8_t x_tap : 1; 591 uint8_t tap_sign : 1; 592 uint8_t double_tap : 1; 593 uint8_t single_tap : 1; 594 uint8_t tap_ia : 1; 595 uint8_t not_used_01 : 1; 596 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 597 uint8_t not_used_01 : 1; 598 uint8_t tap_ia : 1; 599 uint8_t single_tap : 1; 600 uint8_t double_tap : 1; 601 uint8_t tap_sign : 1; 602 uint8_t x_tap : 1; 603 uint8_t y_tap : 1; 604 uint8_t z_tap : 1; 605 #endif /* DRV_BYTE_ORDER */ 606 } ism330dlc_tap_src_t; 607 608 #define ISM330DLC_D6D_SRC 0x1DU 609 typedef struct 610 { 611 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 612 uint8_t xl : 1; 613 uint8_t xh : 1; 614 uint8_t yl : 1; 615 uint8_t yh : 1; 616 uint8_t zl : 1; 617 uint8_t zh : 1; 618 uint8_t d6d_ia : 1; 619 uint8_t den_drdy : 1; 620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 621 uint8_t den_drdy : 1; 622 uint8_t d6d_ia : 1; 623 uint8_t zh : 1; 624 uint8_t zl : 1; 625 uint8_t yh : 1; 626 uint8_t yl : 1; 627 uint8_t xh : 1; 628 uint8_t xl : 1; 629 #endif /* DRV_BYTE_ORDER */ 630 } ism330dlc_d6d_src_t; 631 632 #define ISM330DLC_STATUS_REG 0x1EU 633 typedef struct 634 { 635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 636 uint8_t xlda : 1; 637 uint8_t gda : 1; 638 uint8_t tda : 1; 639 uint8_t not_used_01 : 5; 640 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 641 uint8_t not_used_01 : 5; 642 uint8_t tda : 1; 643 uint8_t gda : 1; 644 uint8_t xlda : 1; 645 #endif /* DRV_BYTE_ORDER */ 646 } ism330dlc_status_reg_t; 647 648 #define ISM330DLC_STATUS_SPIAUX 0x1EU 649 typedef struct 650 { 651 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 652 uint8_t xlda : 1; 653 uint8_t gda : 1; 654 uint8_t gyro_settling : 1; 655 uint8_t not_used_01 : 5; 656 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 657 uint8_t not_used_01 : 5; 658 uint8_t gyro_settling : 1; 659 uint8_t gda : 1; 660 uint8_t xlda : 1; 661 #endif /* DRV_BYTE_ORDER */ 662 } ism330dlc_status_spiaux_t; 663 664 #define ISM330DLC_OUT_TEMP_L 0x20U 665 #define ISM330DLC_OUT_TEMP_H 0x21U 666 #define ISM330DLC_OUTX_L_G 0x22U 667 #define ISM330DLC_OUTX_H_G 0x23U 668 #define ISM330DLC_OUTY_L_G 0x24U 669 #define ISM330DLC_OUTY_H_G 0x25U 670 #define ISM330DLC_OUTZ_L_G 0x26U 671 #define ISM330DLC_OUTZ_H_G 0x27U 672 #define ISM330DLC_OUTX_L_XL 0x28U 673 #define ISM330DLC_OUTX_H_XL 0x29U 674 #define ISM330DLC_OUTY_L_XL 0x2AU 675 #define ISM330DLC_OUTY_H_XL 0x2BU 676 #define ISM330DLC_OUTZ_L_XL 0x2CU 677 #define ISM330DLC_OUTZ_H_XL 0x2DU 678 #define ISM330DLC_SENSORHUB1_REG 0x2EU 679 typedef struct 680 { 681 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 682 uint8_t bit0 : 1; 683 uint8_t bit1 : 1; 684 uint8_t bit2 : 1; 685 uint8_t bit3 : 1; 686 uint8_t bit4 : 1; 687 uint8_t bit5 : 1; 688 uint8_t bit6 : 1; 689 uint8_t bit7 : 1; 690 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 691 uint8_t bit7 : 1; 692 uint8_t bit6 : 1; 693 uint8_t bit5 : 1; 694 uint8_t bit4 : 1; 695 uint8_t bit3 : 1; 696 uint8_t bit2 : 1; 697 uint8_t bit1 : 1; 698 uint8_t bit0 : 1; 699 #endif /* DRV_BYTE_ORDER */ 700 } ism330dlc_sensorhub1_reg_t; 701 702 #define ISM330DLC_SENSORHUB2_REG 0x2FU 703 typedef struct 704 { 705 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 706 uint8_t bit0 : 1; 707 uint8_t bit1 : 1; 708 uint8_t bit2 : 1; 709 uint8_t bit3 : 1; 710 uint8_t bit4 : 1; 711 uint8_t bit5 : 1; 712 uint8_t bit6 : 1; 713 uint8_t bit7 : 1; 714 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 715 uint8_t bit7 : 1; 716 uint8_t bit6 : 1; 717 uint8_t bit5 : 1; 718 uint8_t bit4 : 1; 719 uint8_t bit3 : 1; 720 uint8_t bit2 : 1; 721 uint8_t bit1 : 1; 722 uint8_t bit0 : 1; 723 #endif /* DRV_BYTE_ORDER */ 724 } ism330dlc_sensorhub2_reg_t; 725 726 #define ISM330DLC_SENSORHUB3_REG 0x30U 727 typedef struct 728 { 729 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 730 uint8_t bit0 : 1; 731 uint8_t bit1 : 1; 732 uint8_t bit2 : 1; 733 uint8_t bit3 : 1; 734 uint8_t bit4 : 1; 735 uint8_t bit5 : 1; 736 uint8_t bit6 : 1; 737 uint8_t bit7 : 1; 738 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 739 uint8_t bit7 : 1; 740 uint8_t bit6 : 1; 741 uint8_t bit5 : 1; 742 uint8_t bit4 : 1; 743 uint8_t bit3 : 1; 744 uint8_t bit2 : 1; 745 uint8_t bit1 : 1; 746 uint8_t bit0 : 1; 747 #endif /* DRV_BYTE_ORDER */ 748 } ism330dlc_sensorhub3_reg_t; 749 750 #define ISM330DLC_SENSORHUB4_REG 0x31U 751 typedef struct 752 { 753 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 754 uint8_t bit0 : 1; 755 uint8_t bit1 : 1; 756 uint8_t bit2 : 1; 757 uint8_t bit3 : 1; 758 uint8_t bit4 : 1; 759 uint8_t bit5 : 1; 760 uint8_t bit6 : 1; 761 uint8_t bit7 : 1; 762 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 763 uint8_t bit7 : 1; 764 uint8_t bit6 : 1; 765 uint8_t bit5 : 1; 766 uint8_t bit4 : 1; 767 uint8_t bit3 : 1; 768 uint8_t bit2 : 1; 769 uint8_t bit1 : 1; 770 uint8_t bit0 : 1; 771 #endif /* DRV_BYTE_ORDER */ 772 } ism330dlc_sensorhub4_reg_t; 773 774 #define ISM330DLC_SENSORHUB5_REG 0x32U 775 typedef struct 776 { 777 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 778 uint8_t bit0 : 1; 779 uint8_t bit1 : 1; 780 uint8_t bit2 : 1; 781 uint8_t bit3 : 1; 782 uint8_t bit4 : 1; 783 uint8_t bit5 : 1; 784 uint8_t bit6 : 1; 785 uint8_t bit7 : 1; 786 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 787 uint8_t bit7 : 1; 788 uint8_t bit6 : 1; 789 uint8_t bit5 : 1; 790 uint8_t bit4 : 1; 791 uint8_t bit3 : 1; 792 uint8_t bit2 : 1; 793 uint8_t bit1 : 1; 794 uint8_t bit0 : 1; 795 #endif /* DRV_BYTE_ORDER */ 796 } ism330dlc_sensorhub5_reg_t; 797 798 #define ISM330DLC_SENSORHUB6_REG 0x33U 799 typedef struct 800 { 801 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 802 uint8_t bit0 : 1; 803 uint8_t bit1 : 1; 804 uint8_t bit2 : 1; 805 uint8_t bit3 : 1; 806 uint8_t bit4 : 1; 807 uint8_t bit5 : 1; 808 uint8_t bit6 : 1; 809 uint8_t bit7 : 1; 810 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 811 uint8_t bit7 : 1; 812 uint8_t bit6 : 1; 813 uint8_t bit5 : 1; 814 uint8_t bit4 : 1; 815 uint8_t bit3 : 1; 816 uint8_t bit2 : 1; 817 uint8_t bit1 : 1; 818 uint8_t bit0 : 1; 819 #endif /* DRV_BYTE_ORDER */ 820 } ism330dlc_sensorhub6_reg_t; 821 822 #define ISM330DLC_SENSORHUB7_REG 0x34U 823 typedef struct 824 { 825 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 826 uint8_t bit0 : 1; 827 uint8_t bit1 : 1; 828 uint8_t bit2 : 1; 829 uint8_t bit3 : 1; 830 uint8_t bit4 : 1; 831 uint8_t bit5 : 1; 832 uint8_t bit6 : 1; 833 uint8_t bit7 : 1; 834 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 835 uint8_t bit7 : 1; 836 uint8_t bit6 : 1; 837 uint8_t bit5 : 1; 838 uint8_t bit4 : 1; 839 uint8_t bit3 : 1; 840 uint8_t bit2 : 1; 841 uint8_t bit1 : 1; 842 uint8_t bit0 : 1; 843 #endif /* DRV_BYTE_ORDER */ 844 } ism330dlc_sensorhub7_reg_t; 845 846 #define ISM330DLC_SENSORHUB8_REG 0x35U 847 typedef struct 848 { 849 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 850 uint8_t bit0 : 1; 851 uint8_t bit1 : 1; 852 uint8_t bit2 : 1; 853 uint8_t bit3 : 1; 854 uint8_t bit4 : 1; 855 uint8_t bit5 : 1; 856 uint8_t bit6 : 1; 857 uint8_t bit7 : 1; 858 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 859 uint8_t bit7 : 1; 860 uint8_t bit6 : 1; 861 uint8_t bit5 : 1; 862 uint8_t bit4 : 1; 863 uint8_t bit3 : 1; 864 uint8_t bit2 : 1; 865 uint8_t bit1 : 1; 866 uint8_t bit0 : 1; 867 #endif /* DRV_BYTE_ORDER */ 868 } ism330dlc_sensorhub8_reg_t; 869 870 #define ISM330DLC_SENSORHUB9_REG 0x36U 871 typedef struct 872 { 873 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 874 uint8_t bit0 : 1; 875 uint8_t bit1 : 1; 876 uint8_t bit2 : 1; 877 uint8_t bit3 : 1; 878 uint8_t bit4 : 1; 879 uint8_t bit5 : 1; 880 uint8_t bit6 : 1; 881 uint8_t bit7 : 1; 882 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 883 uint8_t bit7 : 1; 884 uint8_t bit6 : 1; 885 uint8_t bit5 : 1; 886 uint8_t bit4 : 1; 887 uint8_t bit3 : 1; 888 uint8_t bit2 : 1; 889 uint8_t bit1 : 1; 890 uint8_t bit0 : 1; 891 #endif /* DRV_BYTE_ORDER */ 892 } ism330dlc_sensorhub9_reg_t; 893 894 #define ISM330DLC_SENSORHUB10_REG 0x37U 895 typedef struct 896 { 897 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 898 uint8_t bit0 : 1; 899 uint8_t bit1 : 1; 900 uint8_t bit2 : 1; 901 uint8_t bit3 : 1; 902 uint8_t bit4 : 1; 903 uint8_t bit5 : 1; 904 uint8_t bit6 : 1; 905 uint8_t bit7 : 1; 906 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 907 uint8_t bit7 : 1; 908 uint8_t bit6 : 1; 909 uint8_t bit5 : 1; 910 uint8_t bit4 : 1; 911 uint8_t bit3 : 1; 912 uint8_t bit2 : 1; 913 uint8_t bit1 : 1; 914 uint8_t bit0 : 1; 915 #endif /* DRV_BYTE_ORDER */ 916 } ism330dlc_sensorhub10_reg_t; 917 918 #define ISM330DLC_SENSORHUB11_REG 0x38U 919 typedef struct 920 { 921 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 922 uint8_t bit0 : 1; 923 uint8_t bit1 : 1; 924 uint8_t bit2 : 1; 925 uint8_t bit3 : 1; 926 uint8_t bit4 : 1; 927 uint8_t bit5 : 1; 928 uint8_t bit6 : 1; 929 uint8_t bit7 : 1; 930 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 931 uint8_t bit7 : 1; 932 uint8_t bit6 : 1; 933 uint8_t bit5 : 1; 934 uint8_t bit4 : 1; 935 uint8_t bit3 : 1; 936 uint8_t bit2 : 1; 937 uint8_t bit1 : 1; 938 uint8_t bit0 : 1; 939 #endif /* DRV_BYTE_ORDER */ 940 } ism330dlc_sensorhub11_reg_t; 941 942 #define ISM330DLC_SENSORHUB12_REG 0x39U 943 typedef struct 944 { 945 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 946 uint8_t bit0 : 1; 947 uint8_t bit1 : 1; 948 uint8_t bit2 : 1; 949 uint8_t bit3 : 1; 950 uint8_t bit4 : 1; 951 uint8_t bit5 : 1; 952 uint8_t bit6 : 1; 953 uint8_t bit7 : 1; 954 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 955 uint8_t bit7 : 1; 956 uint8_t bit6 : 1; 957 uint8_t bit5 : 1; 958 uint8_t bit4 : 1; 959 uint8_t bit3 : 1; 960 uint8_t bit2 : 1; 961 uint8_t bit1 : 1; 962 uint8_t bit0 : 1; 963 #endif /* DRV_BYTE_ORDER */ 964 } ism330dlc_sensorhub12_reg_t; 965 966 #define ISM330DLC_FIFO_STATUS1 0x3AU 967 typedef struct 968 { 969 uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */ 970 } ism330dlc_fifo_status1_t; 971 972 #define ISM330DLC_FIFO_STATUS2 0x3BU 973 typedef struct 974 { 975 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 976 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 977 uint8_t not_used_01 : 1; 978 uint8_t fifo_empty : 1; 979 uint8_t fifo_full_smart : 1; 980 uint8_t over_run : 1; 981 uint8_t waterm : 1; 982 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 983 uint8_t waterm : 1; 984 uint8_t over_run : 1; 985 uint8_t fifo_full_smart : 1; 986 uint8_t fifo_empty : 1; 987 uint8_t not_used_01 : 1; 988 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 989 #endif /* DRV_BYTE_ORDER */ 990 } ism330dlc_fifo_status2_t; 991 992 #define ISM330DLC_FIFO_STATUS3 0x3CU 993 typedef struct 994 { 995 uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */ 996 } ism330dlc_fifo_status3_t; 997 998 #define ISM330DLC_FIFO_STATUS4 0x3DU 999 typedef struct 1000 { 1001 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1002 uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ 1003 uint8_t not_used_01 : 6; 1004 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1005 uint8_t not_used_01 : 6; 1006 uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ 1007 #endif /* DRV_BYTE_ORDER */ 1008 } ism330dlc_fifo_status4_t; 1009 1010 #define ISM330DLC_FIFO_DATA_OUT_L 0x3E 1011 #define ISM330DLC_FIFO_DATA_OUT_H 0x3F 1012 #define ISM330DLC_TIMESTAMP0_REG 0x40 1013 #define ISM330DLC_TIMESTAMP1_REG 0x41 1014 #define ISM330DLC_TIMESTAMP2_REG 0x42 1015 1016 #define ISM330DLC_SENSORHUB13_REG 0x4DU 1017 typedef struct 1018 { 1019 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1020 uint8_t bit0 : 1; 1021 uint8_t bit1 : 1; 1022 uint8_t bit2 : 1; 1023 uint8_t bit3 : 1; 1024 uint8_t bit4 : 1; 1025 uint8_t bit5 : 1; 1026 uint8_t bit6 : 1; 1027 uint8_t bit7 : 1; 1028 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1029 uint8_t bit7 : 1; 1030 uint8_t bit6 : 1; 1031 uint8_t bit5 : 1; 1032 uint8_t bit4 : 1; 1033 uint8_t bit3 : 1; 1034 uint8_t bit2 : 1; 1035 uint8_t bit1 : 1; 1036 uint8_t bit0 : 1; 1037 #endif /* DRV_BYTE_ORDER */ 1038 } ism330dlc_sensorhub13_reg_t; 1039 1040 #define ISM330DLC_SENSORHUB14_REG 0x4EU 1041 typedef struct 1042 { 1043 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1044 uint8_t bit0 : 1; 1045 uint8_t bit1 : 1; 1046 uint8_t bit2 : 1; 1047 uint8_t bit3 : 1; 1048 uint8_t bit4 : 1; 1049 uint8_t bit5 : 1; 1050 uint8_t bit6 : 1; 1051 uint8_t bit7 : 1; 1052 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1053 uint8_t bit7 : 1; 1054 uint8_t bit6 : 1; 1055 uint8_t bit5 : 1; 1056 uint8_t bit4 : 1; 1057 uint8_t bit3 : 1; 1058 uint8_t bit2 : 1; 1059 uint8_t bit1 : 1; 1060 uint8_t bit0 : 1; 1061 #endif /* DRV_BYTE_ORDER */ 1062 } ism330dlc_sensorhub14_reg_t; 1063 1064 #define ISM330DLC_SENSORHUB15_REG 0x4FU 1065 typedef struct 1066 { 1067 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1068 uint8_t bit0 : 1; 1069 uint8_t bit1 : 1; 1070 uint8_t bit2 : 1; 1071 uint8_t bit3 : 1; 1072 uint8_t bit4 : 1; 1073 uint8_t bit5 : 1; 1074 uint8_t bit6 : 1; 1075 uint8_t bit7 : 1; 1076 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1077 uint8_t bit7 : 1; 1078 uint8_t bit6 : 1; 1079 uint8_t bit5 : 1; 1080 uint8_t bit4 : 1; 1081 uint8_t bit3 : 1; 1082 uint8_t bit2 : 1; 1083 uint8_t bit1 : 1; 1084 uint8_t bit0 : 1; 1085 #endif /* DRV_BYTE_ORDER */ 1086 } ism330dlc_sensorhub15_reg_t; 1087 1088 #define ISM330DLC_SENSORHUB16_REG 0x50U 1089 typedef struct 1090 { 1091 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1092 uint8_t bit0 : 1; 1093 uint8_t bit1 : 1; 1094 uint8_t bit2 : 1; 1095 uint8_t bit3 : 1; 1096 uint8_t bit4 : 1; 1097 uint8_t bit5 : 1; 1098 uint8_t bit6 : 1; 1099 uint8_t bit7 : 1; 1100 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1101 uint8_t bit7 : 1; 1102 uint8_t bit6 : 1; 1103 uint8_t bit5 : 1; 1104 uint8_t bit4 : 1; 1105 uint8_t bit3 : 1; 1106 uint8_t bit2 : 1; 1107 uint8_t bit1 : 1; 1108 uint8_t bit0 : 1; 1109 #endif /* DRV_BYTE_ORDER */ 1110 } ism330dlc_sensorhub16_reg_t; 1111 1112 #define ISM330DLC_SENSORHUB17_REG 0x51U 1113 typedef struct 1114 { 1115 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1116 uint8_t bit0 : 1; 1117 uint8_t bit1 : 1; 1118 uint8_t bit2 : 1; 1119 uint8_t bit3 : 1; 1120 uint8_t bit4 : 1; 1121 uint8_t bit5 : 1; 1122 uint8_t bit6 : 1; 1123 uint8_t bit7 : 1; 1124 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1125 uint8_t bit7 : 1; 1126 uint8_t bit6 : 1; 1127 uint8_t bit5 : 1; 1128 uint8_t bit4 : 1; 1129 uint8_t bit3 : 1; 1130 uint8_t bit2 : 1; 1131 uint8_t bit1 : 1; 1132 uint8_t bit0 : 1; 1133 #endif /* DRV_BYTE_ORDER */ 1134 } ism330dlc_sensorhub17_reg_t; 1135 1136 #define ISM330DLC_SENSORHUB18_REG 0x52U 1137 typedef struct 1138 { 1139 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1140 uint8_t bit0 : 1; 1141 uint8_t bit1 : 1; 1142 uint8_t bit2 : 1; 1143 uint8_t bit3 : 1; 1144 uint8_t bit4 : 1; 1145 uint8_t bit5 : 1; 1146 uint8_t bit6 : 1; 1147 uint8_t bit7 : 1; 1148 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1149 uint8_t bit7 : 1; 1150 uint8_t bit6 : 1; 1151 uint8_t bit5 : 1; 1152 uint8_t bit4 : 1; 1153 uint8_t bit3 : 1; 1154 uint8_t bit2 : 1; 1155 uint8_t bit1 : 1; 1156 uint8_t bit0 : 1; 1157 #endif /* DRV_BYTE_ORDER */ 1158 } ism330dlc_sensorhub18_reg_t; 1159 1160 #define ISM330DLC_FUNC_SRC1 0x53U 1161 typedef struct 1162 { 1163 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1164 uint8_t sensorhub_end_op : 1; 1165 uint8_t si_end_op : 1; 1166 uint8_t hi_fail : 1; 1167 uint8_t not_used_01 : 2; 1168 uint8_t tilt_ia : 1; 1169 uint8_t not_used_02 : 2; 1170 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1171 uint8_t not_used_02 : 2; 1172 uint8_t tilt_ia : 1; 1173 uint8_t not_used_01 : 2; 1174 uint8_t hi_fail : 1; 1175 uint8_t si_end_op : 1; 1176 uint8_t sensorhub_end_op : 1; 1177 #endif /* DRV_BYTE_ORDER */ 1178 } ism330dlc_func_src1_t; 1179 1180 #define ISM330DLC_FUNC_SRC2 0x54U 1181 typedef struct 1182 { 1183 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1184 uint8_t not_used_01 : 3; 1185 uint8_t slave0_nack : 1; 1186 uint8_t slave1_nack : 1; 1187 uint8_t slave2_nack : 1; 1188 uint8_t slave3_nack : 1; 1189 uint8_t not_used_02 : 1; 1190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1191 uint8_t not_used_02 : 1; 1192 uint8_t slave3_nack : 1; 1193 uint8_t slave2_nack : 1; 1194 uint8_t slave1_nack : 1; 1195 uint8_t slave0_nack : 1; 1196 uint8_t not_used_01 : 3; 1197 #endif /* DRV_BYTE_ORDER */ 1198 } ism330dlc_func_src2_t; 1199 1200 #define ISM330DLC_TAP_CFG 0x58U 1201 typedef struct 1202 { 1203 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1204 uint8_t lir : 1; 1205 uint8_t tap_z_en : 1; 1206 uint8_t tap_y_en : 1; 1207 uint8_t tap_x_en : 1; 1208 uint8_t slope_fds : 1; 1209 uint8_t inact_en : 2; 1210 uint8_t interrupts_enable : 1; 1211 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1212 uint8_t interrupts_enable : 1; 1213 uint8_t inact_en : 2; 1214 uint8_t slope_fds : 1; 1215 uint8_t tap_x_en : 1; 1216 uint8_t tap_y_en : 1; 1217 uint8_t tap_z_en : 1; 1218 uint8_t lir : 1; 1219 #endif /* DRV_BYTE_ORDER */ 1220 } ism330dlc_tap_cfg_t; 1221 1222 #define ISM330DLC_TAP_THS_6D 0x59U 1223 typedef struct 1224 { 1225 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1226 uint8_t tap_ths : 5; 1227 uint8_t sixd_ths : 2; 1228 uint8_t d4d_en : 1; 1229 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1230 uint8_t d4d_en : 1; 1231 uint8_t sixd_ths : 2; 1232 uint8_t tap_ths : 5; 1233 #endif /* DRV_BYTE_ORDER */ 1234 } ism330dlc_tap_ths_6d_t; 1235 1236 #define ISM330DLC_INT_DUR2 0x5AU 1237 typedef struct 1238 { 1239 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1240 uint8_t shock : 2; 1241 uint8_t quiet : 2; 1242 uint8_t dur : 4; 1243 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1244 uint8_t dur : 4; 1245 uint8_t quiet : 2; 1246 uint8_t shock : 2; 1247 #endif /* DRV_BYTE_ORDER */ 1248 } ism330dlc_int_dur2_t; 1249 1250 #define ISM330DLC_WAKE_UP_THS 0x5BU 1251 typedef struct 1252 { 1253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1254 uint8_t wk_ths : 6; 1255 uint8_t not_used_01 : 1; 1256 uint8_t single_double_tap : 1; 1257 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1258 uint8_t single_double_tap : 1; 1259 uint8_t not_used_01 : 1; 1260 uint8_t wk_ths : 6; 1261 #endif /* DRV_BYTE_ORDER */ 1262 } ism330dlc_wake_up_ths_t; 1263 1264 #define ISM330DLC_WAKE_UP_DUR 0x5CU 1265 typedef struct 1266 { 1267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1268 uint8_t sleep_dur : 4; 1269 uint8_t timer_hr : 1; 1270 uint8_t wake_dur : 2; 1271 uint8_t ff_dur : 1; 1272 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1273 uint8_t ff_dur : 1; 1274 uint8_t wake_dur : 2; 1275 uint8_t timer_hr : 1; 1276 uint8_t sleep_dur : 4; 1277 #endif /* DRV_BYTE_ORDER */ 1278 } ism330dlc_wake_up_dur_t; 1279 1280 #define ISM330DLC_FREE_FALL 0x5DU 1281 typedef struct 1282 { 1283 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1284 uint8_t ff_ths : 3; 1285 uint8_t ff_dur : 5; 1286 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1287 uint8_t ff_dur : 5; 1288 uint8_t ff_ths : 3; 1289 #endif /* DRV_BYTE_ORDER */ 1290 } ism330dlc_free_fall_t; 1291 1292 #define ISM330DLC_MD1_CFG 0x5EU 1293 typedef struct 1294 { 1295 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1296 uint8_t int1_timer : 1; 1297 uint8_t int1_tilt : 1; 1298 uint8_t int1_6d : 1; 1299 uint8_t int1_double_tap : 1; 1300 uint8_t int1_ff : 1; 1301 uint8_t int1_wu : 1; 1302 uint8_t int1_single_tap : 1; 1303 uint8_t int1_inact_state : 1; 1304 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1305 uint8_t int1_inact_state : 1; 1306 uint8_t int1_single_tap : 1; 1307 uint8_t int1_wu : 1; 1308 uint8_t int1_ff : 1; 1309 uint8_t int1_double_tap : 1; 1310 uint8_t int1_6d : 1; 1311 uint8_t int1_tilt : 1; 1312 uint8_t int1_timer : 1; 1313 #endif /* DRV_BYTE_ORDER */ 1314 } ism330dlc_md1_cfg_t; 1315 1316 #define ISM330DLC_MD2_CFG 0x5FU 1317 typedef struct 1318 { 1319 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1320 uint8_t int2_iron : 1; 1321 uint8_t int2_tilt : 1; 1322 uint8_t int2_6d : 1; 1323 uint8_t int2_double_tap : 1; 1324 uint8_t int2_ff : 1; 1325 uint8_t int2_wu : 1; 1326 uint8_t int2_single_tap : 1; 1327 uint8_t int2_inact_state : 1; 1328 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1329 uint8_t int2_inact_state : 1; 1330 uint8_t int2_single_tap : 1; 1331 uint8_t int2_wu : 1; 1332 uint8_t int2_ff : 1; 1333 uint8_t int2_double_tap : 1; 1334 uint8_t int2_6d : 1; 1335 uint8_t int2_tilt : 1; 1336 uint8_t int2_iron : 1; 1337 #endif /* DRV_BYTE_ORDER */ 1338 } ism330dlc_md2_cfg_t; 1339 1340 #define ISM330DLC_MASTER_CMD_CODE 0x60U 1341 typedef struct 1342 { 1343 uint8_t master_cmd_code : 8; 1344 } ism330dlc_master_cmd_code_t; 1345 1346 #define ISM330DLC_SENS_SYNC_SPI_ERROR_CODE 0x61U 1347 typedef struct 1348 { 1349 uint8_t error_code : 8; 1350 } ism330dlc_sens_sync_spi_error_code_t; 1351 1352 #define ISM330DLC_OUT_MAG_RAW_X_L 0x66U 1353 #define ISM330DLC_OUT_MAG_RAW_X_H 0x67U 1354 #define ISM330DLC_OUT_MAG_RAW_Y_L 0x68U 1355 #define ISM330DLC_OUT_MAG_RAW_Y_H 0x69U 1356 #define ISM330DLC_OUT_MAG_RAW_Z_L 0x6AU 1357 #define ISM330DLC_OUT_MAG_RAW_Z_H 0x6BU 1358 #define ISM330DLC_INT_OIS 0x6FU 1359 typedef struct 1360 { 1361 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1362 uint8_t not_used_01 : 6; 1363 uint8_t lvl2_ois : 1; 1364 uint8_t int2_drdy_ois : 1; 1365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1366 uint8_t int2_drdy_ois : 1; 1367 uint8_t lvl2_ois : 1; 1368 uint8_t not_used_01 : 6; 1369 #endif /* DRV_BYTE_ORDER */ 1370 } ism330dlc_int_ois_t; 1371 1372 #define ISM330DLC_CTRL1_OIS 0x70U 1373 typedef struct 1374 { 1375 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1376 uint8_t ois_en_spi2 : 1; 1377 uint8_t fs_g_ois : 3; /* fs_g_ois + fs_125_ois */ 1378 uint8_t mode4_en : 1; 1379 uint8_t sim_ois : 1; 1380 uint8_t lvl1_ois : 1; 1381 uint8_t ble_ois : 1; 1382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1383 uint8_t ble_ois : 1; 1384 uint8_t lvl1_ois : 1; 1385 uint8_t sim_ois : 1; 1386 uint8_t mode4_en : 1; 1387 uint8_t fs_g_ois : 3; /* fs_g_ois + fs_125_ois */ 1388 uint8_t ois_en_spi2 : 1; 1389 #endif /* DRV_BYTE_ORDER */ 1390 } ism330dlc_ctrl1_ois_t; 1391 1392 #define ISM330DLC_CTRL2_OIS 0x71U 1393 typedef struct 1394 { 1395 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1396 uint8_t hp_en_ois : 1; 1397 uint8_t ftype_ois : 2; 1398 uint8_t not_used_01 : 1; 1399 uint8_t hpm_ois : 2; 1400 uint8_t not_used_02 : 2; 1401 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1402 uint8_t not_used_02 : 2; 1403 uint8_t hpm_ois : 2; 1404 uint8_t not_used_01 : 1; 1405 uint8_t ftype_ois : 2; 1406 uint8_t hp_en_ois : 1; 1407 #endif /* DRV_BYTE_ORDER */ 1408 } ism330dlc_ctrl2_ois_t; 1409 1410 #define ISM330DLC_CTRL3_OIS 0x72U 1411 typedef struct 1412 { 1413 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1414 uint8_t st_ois_clampdis : 1; 1415 uint8_t st_ois : 2; 1416 uint8_t filter_xl_conf_ois : 2; 1417 uint8_t fs_xl_ois : 2; 1418 uint8_t den_lh_ois : 1; 1419 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1420 uint8_t den_lh_ois : 1; 1421 uint8_t fs_xl_ois : 2; 1422 uint8_t filter_xl_conf_ois : 2; 1423 uint8_t st_ois : 2; 1424 uint8_t st_ois_clampdis : 1; 1425 #endif /* DRV_BYTE_ORDER */ 1426 } ism330dlc_ctrl3_ois_t; 1427 1428 #define ISM330DLC_X_OFS_USR 0x73U 1429 #define ISM330DLC_Y_OFS_USR 0x74U 1430 #define ISM330DLC_Z_OFS_USR 0x75U 1431 #define ISM330DLC_SLV0_ADD 0x02U 1432 typedef struct 1433 { 1434 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1435 uint8_t rw_0 : 1; 1436 uint8_t slave0_add : 7; 1437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1438 uint8_t slave0_add : 7; 1439 uint8_t rw_0 : 1; 1440 #endif /* DRV_BYTE_ORDER */ 1441 } ism330dlc_slv0_add_t; 1442 1443 #define ISM330DLC_SLV0_SUBADD 0x03U 1444 typedef struct 1445 { 1446 uint8_t slave0_reg : 8; 1447 } ism330dlc_slv0_subadd_t; 1448 1449 #define ISM330DLC_SLAVE0_CONFIG 0x04U 1450 typedef struct 1451 { 1452 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1453 uint8_t slave0_numop : 3; 1454 uint8_t src_mode : 1; 1455 uint8_t aux_sens_on : 2; 1456 uint8_t slave0_rate : 2; 1457 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1458 uint8_t slave0_rate : 2; 1459 uint8_t aux_sens_on : 2; 1460 uint8_t src_mode : 1; 1461 uint8_t slave0_numop : 3; 1462 #endif /* DRV_BYTE_ORDER */ 1463 } ism330dlc_slave0_config_t; 1464 1465 #define ISM330DLC_SLV1_ADD 0x05U 1466 typedef struct 1467 { 1468 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1469 uint8_t r_1 : 1; 1470 uint8_t slave1_add : 7; 1471 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1472 uint8_t slave1_add : 7; 1473 uint8_t r_1 : 1; 1474 #endif /* DRV_BYTE_ORDER */ 1475 } ism330dlc_slv1_add_t; 1476 1477 #define ISM330DLC_SLV1_SUBADD 0x06U 1478 typedef struct 1479 { 1480 uint8_t slave1_reg : 8; 1481 } ism330dlc_slv1_subadd_t; 1482 1483 #define ISM330DLC_SLAVE1_CONFIG 0x07U 1484 typedef struct 1485 { 1486 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1487 uint8_t slave1_numop : 3; 1488 uint8_t not_used_01 : 2; 1489 uint8_t write_once : 1; 1490 uint8_t slave1_rate : 2; 1491 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1492 uint8_t slave1_rate : 2; 1493 uint8_t write_once : 1; 1494 uint8_t not_used_01 : 2; 1495 uint8_t slave1_numop : 3; 1496 #endif /* DRV_BYTE_ORDER */ 1497 } ism330dlc_slave1_config_t; 1498 1499 #define ISM330DLC_SLV2_ADD 0x08U 1500 typedef struct 1501 { 1502 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1503 uint8_t r_2 : 1; 1504 uint8_t slave2_add : 7; 1505 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1506 uint8_t slave2_add : 7; 1507 uint8_t r_2 : 1; 1508 #endif /* DRV_BYTE_ORDER */ 1509 } ism330dlc_slv2_add_t; 1510 1511 #define ISM330DLC_SLV2_SUBADD 0x09U 1512 typedef struct 1513 { 1514 uint8_t slave2_reg : 8; 1515 } ism330dlc_slv2_subadd_t; 1516 1517 #define ISM330DLC_SLAVE2_CONFIG 0x0AU 1518 typedef struct 1519 { 1520 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1521 uint8_t slave2_numop : 3; 1522 uint8_t not_used_01 : 3; 1523 uint8_t slave2_rate : 2; 1524 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1525 uint8_t slave2_rate : 2; 1526 uint8_t not_used_01 : 3; 1527 uint8_t slave2_numop : 3; 1528 #endif /* DRV_BYTE_ORDER */ 1529 } ism330dlc_slave2_config_t; 1530 1531 #define ISM330DLC_SLV3_ADD 0x0BU 1532 typedef struct 1533 { 1534 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1535 uint8_t r_3 : 1; 1536 uint8_t slave3_add : 7; 1537 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1538 uint8_t slave3_add : 7; 1539 uint8_t r_3 : 1; 1540 #endif /* DRV_BYTE_ORDER */ 1541 } ism330dlc_slv3_add_t; 1542 1543 #define ISM330DLC_SLV3_SUBADD 0x0CU 1544 typedef struct 1545 { 1546 uint8_t slave3_reg : 8; 1547 } ism330dlc_slv3_subadd_t; 1548 1549 #define ISM330DLC_SLAVE3_CONFIG 0x0DU 1550 typedef struct 1551 { 1552 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1553 uint8_t slave3_numop : 3; 1554 uint8_t not_used_01 : 3; 1555 uint8_t slave3_rate : 2; 1556 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1557 uint8_t slave3_rate : 2; 1558 uint8_t not_used_01 : 3; 1559 uint8_t slave3_numop : 3; 1560 #endif /* DRV_BYTE_ORDER */ 1561 } ism330dlc_slave3_config_t; 1562 1563 #define ISM330DLC_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU 1564 typedef struct 1565 { 1566 uint8_t slave_dataw : 8; 1567 } ism330dlc_datawrite_src_mode_sub_slv0_t; 1568 1569 #define ISM330DLC_MAG_SI_XX 0x24U 1570 #define ISM330DLC_MAG_SI_XY 0x25U 1571 #define ISM330DLC_MAG_SI_XZ 0x26U 1572 #define ISM330DLC_MAG_SI_YX 0x27U 1573 #define ISM330DLC_MAG_SI_YY 0x28U 1574 #define ISM330DLC_MAG_SI_YZ 0x29U 1575 #define ISM330DLC_MAG_SI_ZX 0x2AU 1576 #define ISM330DLC_MAG_SI_ZY 0x2BU 1577 #define ISM330DLC_MAG_SI_ZZ 0x2CU 1578 #define ISM330DLC_MAG_OFFX_L 0x2DU 1579 #define ISM330DLC_MAG_OFFX_H 0x2EU 1580 #define ISM330DLC_MAG_OFFY_L 0x2FU 1581 #define ISM330DLC_MAG_OFFY_H 0x30U 1582 #define ISM330DLC_MAG_OFFZ_L 0x31U 1583 #define ISM330DLC_MAG_OFFZ_H 0x32U 1584 1585 /** 1586 * @defgroup ISM330DLC_Register_Union 1587 * @brief This union group all the registers having a bit-field 1588 * description. 1589 * This union is useful but it's not needed by the driver. 1590 * 1591 * REMOVING this union you are compliant with: 1592 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 1593 * 1594 * @{ 1595 * 1596 */ 1597 typedef union 1598 { 1599 ism330dlc_func_cfg_access_t func_cfg_access; 1600 ism330dlc_sensor_sync_time_frame_t sensor_sync_time_frame; 1601 ism330dlc_sensor_sync_res_ratio_t sensor_sync_res_ratio; 1602 ism330dlc_fifo_ctrl1_t fifo_ctrl1; 1603 ism330dlc_fifo_ctrl2_t fifo_ctrl2; 1604 ism330dlc_fifo_ctrl3_t fifo_ctrl3; 1605 ism330dlc_fifo_ctrl4_t fifo_ctrl4; 1606 ism330dlc_fifo_ctrl5_t fifo_ctrl5; 1607 ism330dlc_drdy_pulse_cfg_t drdy_pulse_cfg; 1608 ism330dlc_int1_ctrl_t int1_ctrl; 1609 ism330dlc_int2_ctrl_t int2_ctrl; 1610 ism330dlc_ctrl1_xl_t ctrl1_xl; 1611 ism330dlc_ctrl2_g_t ctrl2_g; 1612 ism330dlc_ctrl3_c_t ctrl3_c; 1613 ism330dlc_ctrl4_c_t ctrl4_c; 1614 ism330dlc_ctrl5_c_t ctrl5_c; 1615 ism330dlc_ctrl6_c_t ctrl6_c; 1616 ism330dlc_ctrl7_g_t ctrl7_g; 1617 ism330dlc_ctrl8_xl_t ctrl8_xl; 1618 ism330dlc_ctrl9_xl_t ctrl9_xl; 1619 ism330dlc_ctrl10_c_t ctrl10_c; 1620 ism330dlc_master_config_t master_config; 1621 ism330dlc_wake_up_src_t wake_up_src; 1622 ism330dlc_tap_src_t tap_src; 1623 ism330dlc_d6d_src_t d6d_src; 1624 ism330dlc_status_reg_t status_reg; 1625 ism330dlc_status_spiaux_t status_spiaux; 1626 ism330dlc_sensorhub1_reg_t sensorhub1_reg; 1627 ism330dlc_sensorhub2_reg_t sensorhub2_reg; 1628 ism330dlc_sensorhub3_reg_t sensorhub3_reg; 1629 ism330dlc_sensorhub4_reg_t sensorhub4_reg; 1630 ism330dlc_sensorhub5_reg_t sensorhub5_reg; 1631 ism330dlc_sensorhub6_reg_t sensorhub6_reg; 1632 ism330dlc_sensorhub7_reg_t sensorhub7_reg; 1633 ism330dlc_sensorhub8_reg_t sensorhub8_reg; 1634 ism330dlc_sensorhub9_reg_t sensorhub9_reg; 1635 ism330dlc_sensorhub10_reg_t sensorhub10_reg; 1636 ism330dlc_sensorhub11_reg_t sensorhub11_reg; 1637 ism330dlc_sensorhub12_reg_t sensorhub12_reg; 1638 ism330dlc_fifo_status1_t fifo_status1; 1639 ism330dlc_fifo_status2_t fifo_status2; 1640 ism330dlc_fifo_status3_t fifo_status3; 1641 ism330dlc_fifo_status4_t fifo_status4; 1642 ism330dlc_sensorhub13_reg_t sensorhub13_reg; 1643 ism330dlc_sensorhub14_reg_t sensorhub14_reg; 1644 ism330dlc_sensorhub15_reg_t sensorhub15_reg; 1645 ism330dlc_sensorhub16_reg_t sensorhub16_reg; 1646 ism330dlc_sensorhub17_reg_t sensorhub17_reg; 1647 ism330dlc_sensorhub18_reg_t sensorhub18_reg; 1648 ism330dlc_func_src1_t func_src1; 1649 ism330dlc_func_src2_t func_src2; 1650 ism330dlc_tap_cfg_t tap_cfg; 1651 ism330dlc_tap_ths_6d_t tap_ths_6d; 1652 ism330dlc_int_dur2_t int_dur2; 1653 ism330dlc_wake_up_ths_t wake_up_ths; 1654 ism330dlc_wake_up_dur_t wake_up_dur; 1655 ism330dlc_free_fall_t free_fall; 1656 ism330dlc_md1_cfg_t md1_cfg; 1657 ism330dlc_md2_cfg_t md2_cfg; 1658 ism330dlc_master_cmd_code_t master_cmd_code; 1659 ism330dlc_sens_sync_spi_error_code_t sens_sync_spi_error_code; 1660 ism330dlc_int_ois_t int_ois; 1661 ism330dlc_ctrl1_ois_t ctrl1_ois; 1662 ism330dlc_ctrl2_ois_t ctrl2_ois; 1663 ism330dlc_ctrl3_ois_t ctrl3_ois; 1664 ism330dlc_slv0_add_t slv0_add; 1665 ism330dlc_slv0_subadd_t slv0_subadd; 1666 ism330dlc_slave0_config_t slave0_config; 1667 ism330dlc_slv1_add_t slv1_add; 1668 ism330dlc_slv1_subadd_t slv1_subadd; 1669 ism330dlc_slave1_config_t slave1_config; 1670 ism330dlc_slv2_add_t slv2_add; 1671 ism330dlc_slv2_subadd_t slv2_subadd; 1672 ism330dlc_slave2_config_t slave2_config; 1673 ism330dlc_slv3_add_t slv3_add; 1674 ism330dlc_slv3_subadd_t slv3_subadd; 1675 ism330dlc_slave3_config_t slave3_config; 1676 ism330dlc_datawrite_src_mode_sub_slv0_t 1677 datawrite_src_mode_sub_slv0; 1678 bitwise_t bitwise; 1679 uint8_t byte; 1680 } ism330dlc_reg_t; 1681 1682 /** 1683 * @} 1684 * 1685 */ 1686 1687 #ifndef __weak 1688 #define __weak __attribute__((weak)) 1689 #endif /* __weak */ 1690 1691 /* 1692 * These are the basic platform dependent I/O routines to read 1693 * and write device registers connected on a standard bus. 1694 * The driver keeps offering a default implementation based on function 1695 * pointers to read/write routines for backward compatibility. 1696 * The __weak directive allows the final application to overwrite 1697 * them with a custom implementation. 1698 */ 1699 1700 int32_t ism330dlc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 1701 uint8_t *data, 1702 uint16_t len); 1703 int32_t ism330dlc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 1704 uint8_t *data, 1705 uint16_t len); 1706 1707 float_t ism330dlc_from_fs2g_to_mg(int16_t lsb); 1708 float_t ism330dlc_from_fs4g_to_mg(int16_t lsb); 1709 float_t ism330dlc_from_fs8g_to_mg(int16_t lsb); 1710 float_t ism330dlc_from_fs16g_to_mg(int16_t lsb); 1711 1712 float_t ism330dlc_from_fs125dps_to_mdps(int16_t lsb); 1713 float_t ism330dlc_from_fs250dps_to_mdps(int16_t lsb); 1714 float_t ism330dlc_from_fs500dps_to_mdps(int16_t lsb); 1715 float_t ism330dlc_from_fs1000dps_to_mdps(int16_t lsb); 1716 float_t ism330dlc_from_fs2000dps_to_mdps(int16_t lsb); 1717 1718 float_t ism330dlc_from_lsb_to_celsius(int16_t lsb); 1719 1720 typedef enum 1721 { 1722 ISM330DLC_2g = 0, 1723 ISM330DLC_16g = 1, 1724 ISM330DLC_4g = 2, 1725 ISM330DLC_8g = 3, 1726 ISM330DLC_XL_FS_ND = 4, /* ERROR CODE */ 1727 } ism330dlc_fs_xl_t; 1728 int32_t ism330dlc_xl_full_scale_set(const stmdev_ctx_t *ctx, 1729 ism330dlc_fs_xl_t val); 1730 int32_t ism330dlc_xl_full_scale_get(const stmdev_ctx_t *ctx, 1731 ism330dlc_fs_xl_t *val); 1732 1733 typedef enum 1734 { 1735 ISM330DLC_XL_ODR_OFF = 0, 1736 ISM330DLC_XL_ODR_12Hz5 = 1, 1737 ISM330DLC_XL_ODR_26Hz = 2, 1738 ISM330DLC_XL_ODR_52Hz = 3, 1739 ISM330DLC_XL_ODR_104Hz = 4, 1740 ISM330DLC_XL_ODR_208Hz = 5, 1741 ISM330DLC_XL_ODR_416Hz = 6, 1742 ISM330DLC_XL_ODR_833Hz = 7, 1743 ISM330DLC_XL_ODR_1k66Hz = 8, 1744 ISM330DLC_XL_ODR_3k33Hz = 9, 1745 ISM330DLC_XL_ODR_6k66Hz = 10, 1746 ISM330DLC_XL_ODR_1Hz6 = 11, 1747 } ism330dlc_odr_xl_t; 1748 int32_t ism330dlc_xl_data_rate_set(const stmdev_ctx_t *ctx, 1749 ism330dlc_odr_xl_t val); 1750 int32_t ism330dlc_xl_data_rate_get(const stmdev_ctx_t *ctx, 1751 ism330dlc_odr_xl_t *val); 1752 1753 typedef enum 1754 { 1755 ISM330DLC_250dps = 0, 1756 ISM330DLC_125dps = 1, 1757 ISM330DLC_500dps = 2, 1758 ISM330DLC_1000dps = 4, 1759 ISM330DLC_2000dps = 6, 1760 } ism330dlc_fs_g_t; 1761 int32_t ism330dlc_gy_full_scale_set(const stmdev_ctx_t *ctx, 1762 ism330dlc_fs_g_t val); 1763 int32_t ism330dlc_gy_full_scale_get(const stmdev_ctx_t *ctx, 1764 ism330dlc_fs_g_t *val); 1765 1766 typedef enum 1767 { 1768 ISM330DLC_GY_ODR_OFF = 0, 1769 ISM330DLC_GY_ODR_12Hz5 = 1, 1770 ISM330DLC_GY_ODR_26Hz = 2, 1771 ISM330DLC_GY_ODR_52Hz = 3, 1772 ISM330DLC_GY_ODR_104Hz = 4, 1773 ISM330DLC_GY_ODR_208Hz = 5, 1774 ISM330DLC_GY_ODR_416Hz = 6, 1775 ISM330DLC_GY_ODR_833Hz = 7, 1776 ISM330DLC_GY_ODR_1k66Hz = 8, 1777 ISM330DLC_GY_ODR_3k33Hz = 9, 1778 ISM330DLC_GY_ODR_6k66Hz = 10, 1779 } ism330dlc_odr_g_t; 1780 int32_t ism330dlc_gy_data_rate_set(const stmdev_ctx_t *ctx, 1781 ism330dlc_odr_g_t val); 1782 int32_t ism330dlc_gy_data_rate_get(const stmdev_ctx_t *ctx, 1783 ism330dlc_odr_g_t *val); 1784 1785 int32_t ism330dlc_block_data_update_set(const stmdev_ctx_t *ctx, 1786 uint8_t val); 1787 int32_t ism330dlc_block_data_update_get(const stmdev_ctx_t *ctx, 1788 uint8_t *val); 1789 1790 typedef enum 1791 { 1792 ISM330DLC_LSb_1mg = 0, 1793 ISM330DLC_LSb_16mg = 1, 1794 } ism330dlc_usr_off_w_t; 1795 int32_t ism330dlc_xl_offset_weight_set(const stmdev_ctx_t *ctx, 1796 ism330dlc_usr_off_w_t val); 1797 int32_t ism330dlc_xl_offset_weight_get(const stmdev_ctx_t *ctx, 1798 ism330dlc_usr_off_w_t *val); 1799 1800 typedef enum 1801 { 1802 ISM330DLC_XL_HIGH_PERFORMANCE = 0, 1803 ISM330DLC_XL_NORMAL = 1, 1804 } ism330dlc_xl_hm_mode_t; 1805 int32_t ism330dlc_xl_power_mode_set(const stmdev_ctx_t *ctx, 1806 ism330dlc_xl_hm_mode_t val); 1807 int32_t ism330dlc_xl_power_mode_get(const stmdev_ctx_t *ctx, 1808 ism330dlc_xl_hm_mode_t *val); 1809 1810 typedef enum 1811 { 1812 ISM330DLC_STAT_RND_DISABLE = 0, 1813 ISM330DLC_STAT_RND_ENABLE = 1, 1814 } ism330dlc_rounding_status_t; 1815 int32_t ism330dlc_rounding_on_status_set(const stmdev_ctx_t *ctx, 1816 ism330dlc_rounding_status_t val); 1817 int32_t ism330dlc_rounding_on_status_get(const stmdev_ctx_t *ctx, 1818 ism330dlc_rounding_status_t *val); 1819 1820 typedef enum 1821 { 1822 ISM330DLC_GY_HIGH_PERFORMANCE = 0, 1823 ISM330DLC_GY_NORMAL = 1, 1824 } ism330dlc_g_hm_mode_t; 1825 int32_t ism330dlc_gy_power_mode_set(const stmdev_ctx_t *ctx, 1826 ism330dlc_g_hm_mode_t val); 1827 int32_t ism330dlc_gy_power_mode_get(const stmdev_ctx_t *ctx, 1828 ism330dlc_g_hm_mode_t *val); 1829 1830 typedef struct 1831 { 1832 ism330dlc_wake_up_src_t wake_up_src; 1833 ism330dlc_tap_src_t tap_src; 1834 ism330dlc_d6d_src_t d6d_src; 1835 ism330dlc_status_reg_t status_reg; 1836 ism330dlc_func_src1_t func_src1; 1837 ism330dlc_func_src2_t func_src2; 1838 } ism330dlc_all_sources_t; 1839 int32_t ism330dlc_all_sources_get(const stmdev_ctx_t *ctx, 1840 ism330dlc_all_sources_t *val); 1841 1842 int32_t ism330dlc_status_reg_get(const stmdev_ctx_t *ctx, 1843 ism330dlc_status_reg_t *val); 1844 1845 int32_t ism330dlc_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 1846 uint8_t *val); 1847 1848 int32_t ism330dlc_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 1849 uint8_t *val); 1850 1851 int32_t ism330dlc_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 1852 uint8_t *val); 1853 1854 int32_t ism330dlc_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff); 1855 int32_t ism330dlc_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1856 int32_t ism330dlc_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 1857 int32_t ism330dlc_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 1858 1859 typedef enum 1860 { 1861 ISM330DLC_LSB_6ms4 = 0, 1862 ISM330DLC_LSB_25us = 1, 1863 } ism330dlc_timer_hr_t; 1864 int32_t ism330dlc_timestamp_res_set(const stmdev_ctx_t *ctx, 1865 ism330dlc_timer_hr_t val); 1866 int32_t ism330dlc_timestamp_res_get(const stmdev_ctx_t *ctx, 1867 ism330dlc_timer_hr_t *val); 1868 1869 typedef enum 1870 { 1871 ISM330DLC_ROUND_DISABLE = 0, 1872 ISM330DLC_ROUND_XL = 1, 1873 ISM330DLC_ROUND_GY = 2, 1874 ISM330DLC_ROUND_GY_XL = 3, 1875 ISM330DLC_ROUND_SH1_TO_SH6 = 4, 1876 ISM330DLC_ROUND_XL_SH1_TO_SH6 = 5, 1877 ISM330DLC_ROUND_GY_XL_SH1_TO_SH12 = 6, 1878 ISM330DLC_ROUND_GY_XL_SH1_TO_SH6 = 7, 1879 } ism330dlc_rounding_t; 1880 int32_t ism330dlc_rounding_mode_set(const stmdev_ctx_t *ctx, 1881 ism330dlc_rounding_t val); 1882 int32_t ism330dlc_rounding_mode_get(const stmdev_ctx_t *ctx, 1883 ism330dlc_rounding_t *val); 1884 1885 int32_t ism330dlc_temperature_raw_get(const stmdev_ctx_t *ctx, 1886 int16_t *val); 1887 1888 int32_t ism330dlc_angular_rate_raw_get(const stmdev_ctx_t *ctx, 1889 int16_t *val); 1890 1891 int32_t ism330dlc_acceleration_raw_get(const stmdev_ctx_t *ctx, 1892 int16_t *val); 1893 1894 int32_t ism330dlc_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, 1895 int16_t *val); 1896 1897 int32_t ism330dlc_fifo_raw_data_get(const stmdev_ctx_t *ctx, 1898 uint8_t *buffer, 1899 uint8_t len); 1900 1901 typedef enum 1902 { 1903 ISM330DLC_USER_BANK = 0, 1904 ISM330DLC_BANK_A = 1, 1905 } ism330dlc_func_cfg_en_t; 1906 int32_t ism330dlc_mem_bank_set(const stmdev_ctx_t *ctx, 1907 ism330dlc_func_cfg_en_t val); 1908 int32_t ism330dlc_mem_bank_get(const stmdev_ctx_t *ctx, 1909 ism330dlc_func_cfg_en_t *val); 1910 1911 typedef enum 1912 { 1913 ISM330DLC_DRDY_LATCHED = 0, 1914 ISM330DLC_DRDY_PULSED = 1, 1915 } ism330dlc_drdy_pulsed_t; 1916 int32_t ism330dlc_data_ready_mode_set(const stmdev_ctx_t *ctx, 1917 ism330dlc_drdy_pulsed_t val); 1918 int32_t ism330dlc_data_ready_mode_get(const stmdev_ctx_t *ctx, 1919 ism330dlc_drdy_pulsed_t *val); 1920 1921 int32_t ism330dlc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1922 int32_t ism330dlc_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 1923 int32_t ism330dlc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 1924 1925 typedef enum 1926 { 1927 ISM330DLC_LSB_AT_LOW_ADD = 0, 1928 ISM330DLC_MSB_AT_LOW_ADD = 1, 1929 } ism330dlc_ble_t; 1930 int32_t ism330dlc_data_format_set(const stmdev_ctx_t *ctx, 1931 ism330dlc_ble_t val); 1932 int32_t ism330dlc_data_format_get(const stmdev_ctx_t *ctx, 1933 ism330dlc_ble_t *val); 1934 1935 int32_t ism330dlc_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 1936 int32_t ism330dlc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 1937 1938 int32_t ism330dlc_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 1939 int32_t ism330dlc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 1940 1941 typedef enum 1942 { 1943 ISM330DLC_XL_ST_DISABLE = 0, 1944 ISM330DLC_XL_ST_POSITIVE = 1, 1945 ISM330DLC_XL_ST_NEGATIVE = 2, 1946 } ism330dlc_st_xl_t; 1947 int32_t ism330dlc_xl_self_test_set(const stmdev_ctx_t *ctx, 1948 ism330dlc_st_xl_t val); 1949 int32_t ism330dlc_xl_self_test_get(const stmdev_ctx_t *ctx, 1950 ism330dlc_st_xl_t *val); 1951 1952 typedef enum 1953 { 1954 ISM330DLC_GY_ST_DISABLE = 0, 1955 ISM330DLC_GY_ST_POSITIVE = 1, 1956 ISM330DLC_GY_ST_NEGATIVE = 3, 1957 } ism330dlc_st_g_t; 1958 int32_t ism330dlc_gy_self_test_set(const stmdev_ctx_t *ctx, 1959 ism330dlc_st_g_t val); 1960 int32_t ism330dlc_gy_self_test_get(const stmdev_ctx_t *ctx, 1961 ism330dlc_st_g_t *val); 1962 1963 int32_t ism330dlc_filter_settling_mask_set(const stmdev_ctx_t *ctx, 1964 uint8_t val); 1965 int32_t ism330dlc_filter_settling_mask_get(const stmdev_ctx_t *ctx, 1966 uint8_t *val); 1967 1968 typedef enum 1969 { 1970 ISM330DLC_USE_SLOPE = 0, 1971 ISM330DLC_USE_HPF = 1, 1972 } ism330dlc_slope_fds_t; 1973 int32_t ism330dlc_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 1974 ism330dlc_slope_fds_t val); 1975 int32_t ism330dlc_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 1976 ism330dlc_slope_fds_t *val); 1977 1978 typedef enum 1979 { 1980 ISM330DLC_XL_ANA_BW_1k5Hz = 0, 1981 ISM330DLC_XL_ANA_BW_400Hz = 1, 1982 } ism330dlc_bw0_xl_t; 1983 int32_t ism330dlc_xl_filter_analog_set(const stmdev_ctx_t *ctx, 1984 ism330dlc_bw0_xl_t val); 1985 int32_t ism330dlc_xl_filter_analog_get(const stmdev_ctx_t *ctx, 1986 ism330dlc_bw0_xl_t *val); 1987 1988 typedef enum 1989 { 1990 ISM330DLC_XL_LP1_ODR_DIV_2 = 0, 1991 ISM330DLC_XL_LP1_ODR_DIV_4 = 1, 1992 ISM330DLC_XL_LP1_NA = 2, 1993 } ism330dlc_lpf1_bw_sel_t; 1994 int32_t ism330dlc_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 1995 ism330dlc_lpf1_bw_sel_t val); 1996 int32_t ism330dlc_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 1997 ism330dlc_lpf1_bw_sel_t *val); 1998 1999 typedef enum 2000 { 2001 ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00, 2002 ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01, 2003 ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02, 2004 ISM330DLC_XL_LOW_LAT_LP_ODR_DIV_400 = 0x03, 2005 ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_50 = 0x10, 2006 ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_100 = 0x11, 2007 ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_9 = 0x12, 2008 ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, 2009 ISM330DLC_XL_LP_NA = 0x14 2010 } ism330dlc_input_composite_t; 2011 int32_t ism330dlc_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, 2012 ism330dlc_input_composite_t val); 2013 int32_t ism330dlc_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, 2014 ism330dlc_input_composite_t *val); 2015 2016 int32_t ism330dlc_xl_reference_mode_set(const stmdev_ctx_t *ctx, 2017 uint8_t val); 2018 int32_t ism330dlc_xl_reference_mode_get(const stmdev_ctx_t *ctx, 2019 uint8_t *val); 2020 2021 typedef enum 2022 { 2023 ISM330DLC_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */ 2024 ISM330DLC_XL_HP_ODR_DIV_100 = 0x01, 2025 ISM330DLC_XL_HP_ODR_DIV_9 = 0x02, 2026 ISM330DLC_XL_HP_ODR_DIV_400 = 0x03, 2027 ISM330DLC_XL_HP_NA = 0x04, 2028 } ism330dlc_hpcf_xl_t; 2029 int32_t ism330dlc_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, 2030 ism330dlc_hpcf_xl_t val); 2031 int32_t ism330dlc_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, 2032 ism330dlc_hpcf_xl_t *val); 2033 2034 typedef enum 2035 { 2036 ISM330DLC_XL_UI_LP1_ODR_DIV_2 = 0, 2037 ISM330DLC_XL_UI_LP1_ODR_DIV_4 = 1, 2038 ISM330DLC_XL_UI_LP1_NA = 2, /* ERROR CODE */ 2039 } ism330dlc_ui_lpf1_bw_sel_t; 2040 int32_t ism330dlc_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 2041 ism330dlc_ui_lpf1_bw_sel_t val); 2042 int32_t ism330dlc_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 2043 ism330dlc_ui_lpf1_bw_sel_t *val); 2044 2045 int32_t ism330dlc_xl_ui_slope_set(const stmdev_ctx_t *ctx, uint8_t val); 2046 int32_t ism330dlc_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val); 2047 2048 typedef enum 2049 { 2050 ISM330DLC_AUX_LP_LIGHT = 2, 2051 ISM330DLC_AUX_LP_NORMAL = 3, 2052 ISM330DLC_AUX_LP_STRONG = 0, 2053 ISM330DLC_AUX_LP_AGGRESSIVE = 1, 2054 } ism330dlc_filter_xl_conf_ois_t; 2055 int32_t ism330dlc_xl_aux_lp_bandwidth_set(const stmdev_ctx_t *ctx, 2056 ism330dlc_filter_xl_conf_ois_t val); 2057 int32_t ism330dlc_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx, 2058 ism330dlc_filter_xl_conf_ois_t *val); 2059 2060 typedef enum 2061 { 2062 ISM330DLC_LP2_ONLY = 0x00, 2063 2064 ISM330DLC_HP_16mHz_LP2 = 0x80, 2065 ISM330DLC_HP_65mHz_LP2 = 0x90, 2066 ISM330DLC_HP_260mHz_LP2 = 0xA0, 2067 ISM330DLC_HP_1Hz04_LP2 = 0xB0, 2068 2069 ISM330DLC_HP_DISABLE_LP1_LIGHT = 0x0A, 2070 ISM330DLC_HP_DISABLE_LP1_NORMAL = 0x09, 2071 ISM330DLC_HP_DISABLE_LP_STRONG = 0x08, 2072 ISM330DLC_HP_DISABLE_LP1_AGGRESSIVE = 0x0B, 2073 2074 ISM330DLC_HP_16mHz_LP1_LIGHT = 0x8A, 2075 ISM330DLC_HP_65mHz_LP1_NORMAL = 0x99, 2076 ISM330DLC_HP_260mHz_LP1_STRONG = 0xA8, 2077 ISM330DLC_HP_1Hz04_LP1_AGGRESSIVE = 0xBB, 2078 } ism330dlc_lpf1_sel_g_t; 2079 int32_t ism330dlc_gy_band_pass_set(const stmdev_ctx_t *ctx, 2080 ism330dlc_lpf1_sel_g_t val); 2081 int32_t ism330dlc_gy_band_pass_get(const stmdev_ctx_t *ctx, 2082 ism330dlc_lpf1_sel_g_t *val); 2083 2084 int32_t ism330dlc_gy_ui_high_pass_set(const stmdev_ctx_t *ctx, uint8_t val); 2085 int32_t ism330dlc_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, 2086 uint8_t *val); 2087 2088 typedef enum 2089 { 2090 ISM330DLC_HP_DISABLE_LP_173Hz = 0x02, 2091 ISM330DLC_HP_DISABLE_LP_237Hz = 0x01, 2092 ISM330DLC_HP_DISABLE_LP_351Hz = 0x00, 2093 ISM330DLC_HP_DISABLE_LP_937Hz = 0x03, 2094 2095 ISM330DLC_HP_16mHz_LP_173Hz = 0x82, 2096 ISM330DLC_HP_65mHz_LP_237Hz = 0x91, 2097 ISM330DLC_HP_260mHz_LP_351Hz = 0xA0, 2098 ISM330DLC_HP_1Hz04_LP_937Hz = 0xB3, 2099 } ism330dlc_hp_en_ois_t; 2100 int32_t ism330dlc_gy_aux_bandwidth_set(const stmdev_ctx_t *ctx, 2101 ism330dlc_hp_en_ois_t val); 2102 int32_t ism330dlc_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx, 2103 ism330dlc_hp_en_ois_t *val); 2104 2105 int32_t ism330dlc_aux_status_reg_get(const stmdev_ctx_t *ctx, 2106 ism330dlc_status_spiaux_t *val); 2107 2108 int32_t ism330dlc_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 2109 uint8_t *val); 2110 2111 int32_t ism330dlc_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 2112 uint8_t *val); 2113 2114 int32_t ism330dlc_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, 2115 uint8_t *val); 2116 2117 typedef enum 2118 { 2119 ISM330DLC_AUX_DEN_DISABLE = 0, 2120 ISM330DLC_AUX_DEN_LEVEL_LATCH = 3, 2121 ISM330DLC_AUX_DEN_LEVEL_TRIG = 2, 2122 } ism330dlc_lvl_ois_t; 2123 int32_t ism330dlc_aux_den_mode_set(const stmdev_ctx_t *ctx, 2124 ism330dlc_lvl_ois_t val); 2125 int32_t ism330dlc_aux_den_mode_get(const stmdev_ctx_t *ctx, 2126 ism330dlc_lvl_ois_t *val); 2127 2128 int32_t ism330dlc_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, 2129 uint8_t val); 2130 int32_t ism330dlc_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, 2131 uint8_t *val); 2132 2133 typedef enum 2134 { 2135 ISM330DLC_AUX_DISABLE = 0, 2136 ISM330DLC_MODE_3_GY = 1, 2137 ISM330DLC_MODE_4_GY_XL = 3, 2138 } ism330dlc_ois_en_spi2_t; 2139 int32_t ism330dlc_aux_mode_set(const stmdev_ctx_t *ctx, 2140 ism330dlc_ois_en_spi2_t val); 2141 int32_t ism330dlc_aux_mode_get(const stmdev_ctx_t *ctx, 2142 ism330dlc_ois_en_spi2_t *val); 2143 2144 typedef enum 2145 { 2146 ISM330DLC_250dps_AUX = 0, 2147 ISM330DLC_125dps_AUX = 1, 2148 ISM330DLC_500dps_AUX = 2, 2149 ISM330DLC_1000dps_AUX = 4, 2150 ISM330DLC_2000dps_AUX = 6, 2151 } ism330dlc_fs_g_ois_t; 2152 int32_t ism330dlc_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, 2153 ism330dlc_fs_g_ois_t val); 2154 int32_t ism330dlc_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, 2155 ism330dlc_fs_g_ois_t *val); 2156 2157 typedef enum 2158 { 2159 ISM330DLC_AUX_SPI_4_WIRE = 0, 2160 ISM330DLC_AUX_SPI_3_WIRE = 1, 2161 } ism330dlc_sim_ois_t; 2162 int32_t ism330dlc_aux_spi_mode_set(const stmdev_ctx_t *ctx, 2163 ism330dlc_sim_ois_t val); 2164 int32_t ism330dlc_aux_spi_mode_get(const stmdev_ctx_t *ctx, 2165 ism330dlc_sim_ois_t *val); 2166 2167 typedef enum 2168 { 2169 ISM330DLC_AUX_LSB_AT_LOW_ADD = 0, 2170 ISM330DLC_AUX_MSB_AT_LOW_ADD = 1, 2171 } ism330dlc_ble_ois_t; 2172 int32_t ism330dlc_aux_data_format_set(const stmdev_ctx_t *ctx, 2173 ism330dlc_ble_ois_t val); 2174 int32_t ism330dlc_aux_data_format_get(const stmdev_ctx_t *ctx, 2175 ism330dlc_ble_ois_t *val); 2176 2177 typedef enum 2178 { 2179 ISM330DLC_ENABLE_CLAMP = 0, 2180 ISM330DLC_DISABLE_CLAMP = 1, 2181 } ism330dlc_st_ois_clampdis_t; 2182 int32_t ism330dlc_aux_gy_clamp_set(const stmdev_ctx_t *ctx, 2183 ism330dlc_st_ois_clampdis_t val); 2184 int32_t ism330dlc_aux_gy_clamp_get(const stmdev_ctx_t *ctx, 2185 ism330dlc_st_ois_clampdis_t *val); 2186 2187 typedef enum 2188 { 2189 ISM330DLC_AUX_GY_DISABLE = 0, 2190 ISM330DLC_AUX_GY_POS = 1, 2191 ISM330DLC_AUX_GY_NEG = 3, 2192 } ism330dlc_st_ois_t; 2193 int32_t ism330dlc_aux_gy_self_test_set(const stmdev_ctx_t *ctx, 2194 ism330dlc_st_ois_t val); 2195 int32_t ism330dlc_aux_gy_self_test_get(const stmdev_ctx_t *ctx, 2196 ism330dlc_st_ois_t *val); 2197 2198 typedef enum 2199 { 2200 ISM330DLC_AUX_2g = 0, 2201 ISM330DLC_AUX_16g = 1, 2202 ISM330DLC_AUX_4g = 2, 2203 ISM330DLC_AUX_8g = 3, 2204 } ism330dlc_fs_xl_ois_t; 2205 int32_t ism330dlc_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, 2206 ism330dlc_fs_xl_ois_t val); 2207 int32_t ism330dlc_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, 2208 ism330dlc_fs_xl_ois_t *val); 2209 2210 typedef enum 2211 { 2212 ISM330DLC_AUX_DEN_ACTIVE_LOW = 0, 2213 ISM330DLC_AUX_DEN_ACTIVE_HIGH = 1, 2214 } ism330dlc_den_lh_ois_t; 2215 int32_t ism330dlc_aux_den_polarity_set(const stmdev_ctx_t *ctx, 2216 ism330dlc_den_lh_ois_t val); 2217 int32_t ism330dlc_aux_den_polarity_get(const stmdev_ctx_t *ctx, 2218 ism330dlc_den_lh_ois_t *val); 2219 2220 typedef enum 2221 { 2222 ISM330DLC_SPI_4_WIRE = 0, 2223 ISM330DLC_SPI_3_WIRE = 1, 2224 } ism330dlc_sim_t; 2225 int32_t ism330dlc_spi_mode_set(const stmdev_ctx_t *ctx, 2226 ism330dlc_sim_t val); 2227 int32_t ism330dlc_spi_mode_get(const stmdev_ctx_t *ctx, 2228 ism330dlc_sim_t *val); 2229 2230 typedef enum 2231 { 2232 ISM330DLC_I2C_ENABLE = 0, 2233 ISM330DLC_I2C_DISABLE = 1, 2234 } ism330dlc_i2c_disable_t; 2235 int32_t ism330dlc_i2c_interface_set(const stmdev_ctx_t *ctx, 2236 ism330dlc_i2c_disable_t val); 2237 int32_t ism330dlc_i2c_interface_get(const stmdev_ctx_t *ctx, 2238 ism330dlc_i2c_disable_t *val); 2239 2240 typedef struct 2241 { 2242 uint8_t int1_drdy_xl : 1; 2243 uint8_t int1_drdy_g : 1; 2244 uint8_t int1_boot : 1; 2245 uint8_t int1_fth : 1; 2246 uint8_t int1_fifo_ovr : 1; 2247 uint8_t int1_full_flag : 1; 2248 uint8_t int1_tilt : 1; 2249 uint8_t int1_6d : 1; 2250 uint8_t int1_double_tap : 1; 2251 uint8_t int1_ff : 1; 2252 uint8_t int1_wu : 1; 2253 uint8_t int1_single_tap : 1; 2254 uint8_t int1_inact_state : 1; 2255 uint8_t den_drdy_int1 : 1; 2256 uint8_t drdy_on_int1 : 1; 2257 } ism330dlc_int1_route_t; 2258 int32_t ism330dlc_pin_int1_route_set(const stmdev_ctx_t *ctx, 2259 ism330dlc_int1_route_t val); 2260 int32_t ism330dlc_pin_int1_route_get(const stmdev_ctx_t *ctx, 2261 ism330dlc_int1_route_t *val); 2262 2263 typedef struct 2264 { 2265 uint8_t int2_drdy_xl : 1; 2266 uint8_t int2_drdy_g : 1; 2267 uint8_t int2_drdy_temp : 1; 2268 uint8_t int2_fth : 1; 2269 uint8_t int2_fifo_ovr : 1; 2270 uint8_t int2_full_flag : 1; 2271 uint8_t int2_iron : 1; 2272 uint8_t int2_tilt : 1; 2273 uint8_t int2_6d : 1; 2274 uint8_t int2_double_tap : 1; 2275 uint8_t int2_ff : 1; 2276 uint8_t int2_wu : 1; 2277 uint8_t int2_single_tap : 1; 2278 uint8_t int2_inact_state : 1; 2279 } ism330dlc_int2_route_t; 2280 int32_t ism330dlc_pin_int2_route_set(const stmdev_ctx_t *ctx, 2281 ism330dlc_int2_route_t val); 2282 int32_t ism330dlc_pin_int2_route_get(const stmdev_ctx_t *ctx, 2283 ism330dlc_int2_route_t *val); 2284 2285 typedef enum 2286 { 2287 ISM330DLC_PUSH_PULL = 0, 2288 ISM330DLC_OPEN_DRAIN = 1, 2289 } ism330dlc_pp_od_t; 2290 int32_t ism330dlc_pin_mode_set(const stmdev_ctx_t *ctx, 2291 ism330dlc_pp_od_t val); 2292 int32_t ism330dlc_pin_mode_get(const stmdev_ctx_t *ctx, 2293 ism330dlc_pp_od_t *val); 2294 2295 typedef enum 2296 { 2297 ISM330DLC_ACTIVE_HIGH = 0, 2298 ISM330DLC_ACTIVE_LOW = 1, 2299 } ism330dlc_h_lactive_t; 2300 int32_t ism330dlc_pin_polarity_set(const stmdev_ctx_t *ctx, 2301 ism330dlc_h_lactive_t val); 2302 int32_t ism330dlc_pin_polarity_get(const stmdev_ctx_t *ctx, 2303 ism330dlc_h_lactive_t *val); 2304 2305 int32_t ism330dlc_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 2306 int32_t ism330dlc_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2307 2308 typedef enum 2309 { 2310 ISM330DLC_INT_PULSED = 0, 2311 ISM330DLC_INT_LATCHED = 1, 2312 } ism330dlc_lir_t; 2313 int32_t ism330dlc_int_notification_set(const stmdev_ctx_t *ctx, 2314 ism330dlc_lir_t val); 2315 int32_t ism330dlc_int_notification_get(const stmdev_ctx_t *ctx, 2316 ism330dlc_lir_t *val); 2317 2318 int32_t ism330dlc_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 2319 int32_t ism330dlc_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 2320 2321 int32_t ism330dlc_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2322 int32_t ism330dlc_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2323 2324 int32_t ism330dlc_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2325 int32_t ism330dlc_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2326 2327 typedef enum 2328 { 2329 ISM330DLC_PROPERTY_DISABLE = 0, 2330 ISM330DLC_XL_12Hz5_GY_NOT_AFFECTED = 1, 2331 ISM330DLC_XL_12Hz5_GY_SLEEP = 2, 2332 ISM330DLC_XL_12Hz5_GY_PD = 3, 2333 } ism330dlc_inact_en_t; 2334 int32_t ism330dlc_act_mode_set(const stmdev_ctx_t *ctx, 2335 ism330dlc_inact_en_t val); 2336 int32_t ism330dlc_act_mode_get(const stmdev_ctx_t *ctx, 2337 ism330dlc_inact_en_t *val); 2338 2339 int32_t ism330dlc_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2340 int32_t ism330dlc_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2341 2342 int32_t ism330dlc_tap_src_get(const stmdev_ctx_t *ctx, 2343 ism330dlc_tap_src_t *val); 2344 2345 int32_t ism330dlc_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 2346 uint8_t val); 2347 int32_t ism330dlc_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 2348 uint8_t *val); 2349 2350 int32_t ism330dlc_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 2351 uint8_t val); 2352 int32_t ism330dlc_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 2353 uint8_t *val); 2354 2355 int32_t ism330dlc_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 2356 uint8_t val); 2357 int32_t ism330dlc_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 2358 uint8_t *val); 2359 2360 int32_t ism330dlc_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); 2361 int32_t ism330dlc_tap_threshold_x_get(const stmdev_ctx_t *ctx, 2362 uint8_t *val); 2363 2364 int32_t ism330dlc_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 2365 int32_t ism330dlc_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 2366 2367 int32_t ism330dlc_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 2368 int32_t ism330dlc_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 2369 2370 int32_t ism330dlc_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2371 int32_t ism330dlc_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2372 2373 typedef enum 2374 { 2375 ISM330DLC_ONLY_SINGLE = 0, 2376 ISM330DLC_BOTH_SINGLE_DOUBLE = 1, 2377 } ism330dlc_single_double_tap_t; 2378 int32_t ism330dlc_tap_mode_set(const stmdev_ctx_t *ctx, 2379 ism330dlc_single_double_tap_t val); 2380 int32_t ism330dlc_tap_mode_get(const stmdev_ctx_t *ctx, 2381 ism330dlc_single_double_tap_t *val); 2382 2383 typedef enum 2384 { 2385 ISM330DLC_ODR_DIV_2_FEED = 0, 2386 ISM330DLC_LPF2_FEED = 1, 2387 } ism330dlc_low_pass_on_6d_t; 2388 int32_t ism330dlc_6d_feed_data_set(const stmdev_ctx_t *ctx, 2389 ism330dlc_low_pass_on_6d_t val); 2390 int32_t ism330dlc_6d_feed_data_get(const stmdev_ctx_t *ctx, 2391 ism330dlc_low_pass_on_6d_t *val); 2392 2393 typedef enum 2394 { 2395 ISM330DLC_DEG_80 = 0, 2396 ISM330DLC_DEG_70 = 1, 2397 ISM330DLC_DEG_60 = 2, 2398 ISM330DLC_DEG_50 = 3, 2399 } ism330dlc_sixd_ths_t; 2400 int32_t ism330dlc_6d_threshold_set(const stmdev_ctx_t *ctx, 2401 ism330dlc_sixd_ths_t val); 2402 int32_t ism330dlc_6d_threshold_get(const stmdev_ctx_t *ctx, 2403 ism330dlc_sixd_ths_t *val); 2404 2405 int32_t ism330dlc_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2406 int32_t ism330dlc_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2407 2408 int32_t ism330dlc_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2409 int32_t ism330dlc_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2410 2411 typedef enum 2412 { 2413 ISM330DLC_FF_TSH_156mg = 0, 2414 ISM330DLC_FF_TSH_219mg = 1, 2415 ISM330DLC_FF_TSH_250mg = 2, 2416 ISM330DLC_FF_TSH_312mg = 3, 2417 ISM330DLC_FF_TSH_344mg = 4, 2418 ISM330DLC_FF_TSH_406mg = 5, 2419 ISM330DLC_FF_TSH_469mg = 6, 2420 ISM330DLC_FF_TSH_500mg = 7, 2421 } ism330dlc_ff_ths_t; 2422 int32_t ism330dlc_ff_threshold_set(const stmdev_ctx_t *ctx, 2423 ism330dlc_ff_ths_t val); 2424 int32_t ism330dlc_ff_threshold_get(const stmdev_ctx_t *ctx, 2425 ism330dlc_ff_ths_t *val); 2426 2427 int32_t ism330dlc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); 2428 int32_t ism330dlc_fifo_watermark_get(const stmdev_ctx_t *ctx, 2429 uint16_t *val); 2430 2431 int32_t ism330dlc_fifo_data_level_get(const stmdev_ctx_t *ctx, 2432 uint16_t *val); 2433 2434 int32_t ism330dlc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 2435 2436 int32_t ism330dlc_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val); 2437 2438 int32_t ism330dlc_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 2439 int32_t ism330dlc_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 2440 uint8_t *val); 2441 2442 typedef enum 2443 { 2444 ISM330DLC_TRG_XL_GY_DRDY = 0, 2445 ISM330DLC_TRG_SH_DRDY = 1, 2446 } ism330dlc_trigger_fifo_t; 2447 int32_t ism330dlc_fifo_write_trigger_set(const stmdev_ctx_t *ctx, 2448 ism330dlc_trigger_fifo_t val); 2449 int32_t ism330dlc_fifo_write_trigger_get(const stmdev_ctx_t *ctx, 2450 ism330dlc_trigger_fifo_t *val); 2451 2452 typedef enum 2453 { 2454 ISM330DLC_FIFO_XL_DISABLE = 0, 2455 ISM330DLC_FIFO_XL_NO_DEC = 1, 2456 ISM330DLC_FIFO_XL_DEC_2 = 2, 2457 ISM330DLC_FIFO_XL_DEC_3 = 3, 2458 ISM330DLC_FIFO_XL_DEC_4 = 4, 2459 ISM330DLC_FIFO_XL_DEC_8 = 5, 2460 ISM330DLC_FIFO_XL_DEC_16 = 6, 2461 ISM330DLC_FIFO_XL_DEC_32 = 7, 2462 } ism330dlc_dec_fifo_xl_t; 2463 int32_t ism330dlc_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 2464 ism330dlc_dec_fifo_xl_t val); 2465 int32_t ism330dlc_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 2466 ism330dlc_dec_fifo_xl_t *val); 2467 2468 typedef enum 2469 { 2470 ISM330DLC_FIFO_GY_DISABLE = 0, 2471 ISM330DLC_FIFO_GY_NO_DEC = 1, 2472 ISM330DLC_FIFO_GY_DEC_2 = 2, 2473 ISM330DLC_FIFO_GY_DEC_3 = 3, 2474 ISM330DLC_FIFO_GY_DEC_4 = 4, 2475 ISM330DLC_FIFO_GY_DEC_8 = 5, 2476 ISM330DLC_FIFO_GY_DEC_16 = 6, 2477 ISM330DLC_FIFO_GY_DEC_32 = 7, 2478 } ism330dlc_dec_fifo_gyro_t; 2479 int32_t ism330dlc_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 2480 ism330dlc_dec_fifo_gyro_t val); 2481 int32_t ism330dlc_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 2482 ism330dlc_dec_fifo_gyro_t *val); 2483 2484 typedef enum 2485 { 2486 ISM330DLC_FIFO_DS3_DISABLE = 0, 2487 ISM330DLC_FIFO_DS3_NO_DEC = 1, 2488 ISM330DLC_FIFO_DS3_DEC_2 = 2, 2489 ISM330DLC_FIFO_DS3_DEC_3 = 3, 2490 ISM330DLC_FIFO_DS3_DEC_4 = 4, 2491 ISM330DLC_FIFO_DS3_DEC_8 = 5, 2492 ISM330DLC_FIFO_DS3_DEC_16 = 6, 2493 ISM330DLC_FIFO_DS3_DEC_32 = 7, 2494 } ism330dlc_dec_ds3_fifo_t; 2495 int32_t ism330dlc_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, 2496 ism330dlc_dec_ds3_fifo_t val); 2497 int32_t ism330dlc_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, 2498 ism330dlc_dec_ds3_fifo_t *val); 2499 2500 typedef enum 2501 { 2502 ISM330DLC_FIFO_DS4_DISABLE = 0, 2503 ISM330DLC_FIFO_DS4_NO_DEC = 1, 2504 ISM330DLC_FIFO_DS4_DEC_2 = 2, 2505 ISM330DLC_FIFO_DS4_DEC_3 = 3, 2506 ISM330DLC_FIFO_DS4_DEC_4 = 4, 2507 ISM330DLC_FIFO_DS4_DEC_8 = 5, 2508 ISM330DLC_FIFO_DS4_DEC_16 = 6, 2509 ISM330DLC_FIFO_DS4_DEC_32 = 7, 2510 } ism330dlc_dec_ds4_fifo_t; 2511 int32_t ism330dlc_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, 2512 ism330dlc_dec_ds4_fifo_t val); 2513 int32_t ism330dlc_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, 2514 ism330dlc_dec_ds4_fifo_t *val); 2515 2516 int32_t ism330dlc_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, 2517 uint8_t val); 2518 int32_t ism330dlc_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, 2519 uint8_t *val); 2520 2521 int32_t ism330dlc_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, 2522 uint8_t val); 2523 int32_t ism330dlc_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, 2524 uint8_t *val); 2525 2526 typedef enum 2527 { 2528 ISM330DLC_BYPASS_MODE = 0, 2529 ISM330DLC_FIFO_MODE = 1, 2530 ISM330DLC_STREAM_TO_FIFO_MODE = 3, 2531 ISM330DLC_BYPASS_TO_STREAM_MODE = 4, 2532 ISM330DLC_STREAM_MODE = 6, 2533 } ism330dlc_fifo_mode_t; 2534 int32_t ism330dlc_fifo_mode_set(const stmdev_ctx_t *ctx, 2535 ism330dlc_fifo_mode_t val); 2536 int32_t ism330dlc_fifo_mode_get(const stmdev_ctx_t *ctx, 2537 ism330dlc_fifo_mode_t *val); 2538 2539 typedef enum 2540 { 2541 ISM330DLC_FIFO_DISABLE = 0, 2542 ISM330DLC_FIFO_12Hz5 = 1, 2543 ISM330DLC_FIFO_26Hz = 2, 2544 ISM330DLC_FIFO_52Hz = 3, 2545 ISM330DLC_FIFO_104Hz = 4, 2546 ISM330DLC_FIFO_208Hz = 5, 2547 ISM330DLC_FIFO_416Hz = 6, 2548 ISM330DLC_FIFO_833Hz = 7, 2549 ISM330DLC_FIFO_1k66Hz = 8, 2550 ISM330DLC_FIFO_3k33Hz = 9, 2551 ISM330DLC_FIFO_6k66Hz = 10, 2552 } ism330dlc_odr_fifo_t; 2553 int32_t ism330dlc_fifo_data_rate_set(const stmdev_ctx_t *ctx, 2554 ism330dlc_odr_fifo_t val); 2555 int32_t ism330dlc_fifo_data_rate_get(const stmdev_ctx_t *ctx, 2556 ism330dlc_odr_fifo_t *val); 2557 2558 typedef enum 2559 { 2560 ISM330DLC_DEN_ACT_LOW = 0, 2561 ISM330DLC_DEN_ACT_HIGH = 1, 2562 } ism330dlc_den_lh_t; 2563 int32_t ism330dlc_den_polarity_set(const stmdev_ctx_t *ctx, 2564 ism330dlc_den_lh_t val); 2565 int32_t ism330dlc_den_polarity_get(const stmdev_ctx_t *ctx, 2566 ism330dlc_den_lh_t *val); 2567 2568 typedef enum 2569 { 2570 ISM330DLC_DEN_DISABLE = 0, 2571 ISM330DLC_LEVEL_FIFO = 6, 2572 ISM330DLC_LEVEL_LETCHED = 3, 2573 ISM330DLC_LEVEL_TRIGGER = 2, 2574 ISM330DLC_EDGE_TRIGGER = 4, 2575 } ism330dlc_den_mode_t; 2576 int32_t ism330dlc_den_mode_set(const stmdev_ctx_t *ctx, 2577 ism330dlc_den_mode_t val); 2578 int32_t ism330dlc_den_mode_get(const stmdev_ctx_t *ctx, 2579 ism330dlc_den_mode_t *val); 2580 2581 typedef enum 2582 { 2583 ISM330DLC_STAMP_IN_GY_DATA = 0, 2584 ISM330DLC_STAMP_IN_XL_DATA = 1, 2585 ISM330DLC_STAMP_IN_GY_XL_DATA = 2, 2586 } ism330dlc_den_xl_en_t; 2587 int32_t ism330dlc_den_enable_set(const stmdev_ctx_t *ctx, 2588 ism330dlc_den_xl_en_t val); 2589 int32_t ism330dlc_den_enable_get(const stmdev_ctx_t *ctx, 2590 ism330dlc_den_xl_en_t *val); 2591 2592 int32_t ism330dlc_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); 2593 int32_t ism330dlc_den_mark_axis_z_get(const stmdev_ctx_t *ctx, 2594 uint8_t *val); 2595 2596 int32_t ism330dlc_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); 2597 int32_t ism330dlc_den_mark_axis_y_get(const stmdev_ctx_t *ctx, 2598 uint8_t *val); 2599 2600 int32_t ism330dlc_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); 2601 int32_t ism330dlc_den_mark_axis_x_get(const stmdev_ctx_t *ctx, 2602 uint8_t *val); 2603 2604 int32_t ism330dlc_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val); 2605 int32_t ism330dlc_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); 2606 2607 int32_t ism330dlc_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val); 2608 int32_t ism330dlc_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); 2609 2610 int32_t ism330dlc_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, 2611 uint8_t *buff); 2612 int32_t ism330dlc_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, 2613 uint8_t *buff); 2614 2615 int32_t ism330dlc_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 2616 int32_t ism330dlc_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 2617 2618 int32_t ism330dlc_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, 2619 uint8_t val); 2620 int32_t ism330dlc_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, 2621 uint8_t *val); 2622 2623 typedef enum 2624 { 2625 ISM330DLC_RES_RATIO_2_11 = 0, 2626 ISM330DLC_RES_RATIO_2_12 = 1, 2627 ISM330DLC_RES_RATIO_2_13 = 2, 2628 ISM330DLC_RES_RATIO_2_14 = 3, 2629 } ism330dlc_rr_t; 2630 int32_t ism330dlc_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, 2631 ism330dlc_rr_t val); 2632 int32_t ism330dlc_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, 2633 ism330dlc_rr_t *val); 2634 2635 int32_t ism330dlc_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 2636 int32_t ism330dlc_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 2637 2638 int32_t ism330dlc_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); 2639 int32_t ism330dlc_sh_pass_through_get(const stmdev_ctx_t *ctx, 2640 uint8_t *val); 2641 2642 typedef enum 2643 { 2644 ISM330DLC_EXT_PULL_UP = 0, 2645 ISM330DLC_INTERNAL_PULL_UP = 1, 2646 } ism330dlc_pull_up_en_t; 2647 int32_t ism330dlc_sh_pin_mode_set(const stmdev_ctx_t *ctx, 2648 ism330dlc_pull_up_en_t val); 2649 int32_t ism330dlc_sh_pin_mode_get(const stmdev_ctx_t *ctx, 2650 ism330dlc_pull_up_en_t *val); 2651 2652 typedef enum 2653 { 2654 ISM330DLC_XL_GY_DRDY = 1, 2655 ISM330DLC_EXT_ON_INT2_PIN = 0, 2656 } ism330dlc_start_config_t; 2657 int32_t ism330dlc_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 2658 ism330dlc_start_config_t val); 2659 int32_t ism330dlc_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 2660 ism330dlc_start_config_t *val); 2661 2662 int32_t ism330dlc_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 2663 int32_t ism330dlc_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, 2664 uint8_t *val); 2665 2666 typedef struct 2667 { 2668 ism330dlc_sensorhub1_reg_t sh_byte_1; 2669 ism330dlc_sensorhub2_reg_t sh_byte_2; 2670 ism330dlc_sensorhub3_reg_t sh_byte_3; 2671 ism330dlc_sensorhub4_reg_t sh_byte_4; 2672 ism330dlc_sensorhub5_reg_t sh_byte_5; 2673 ism330dlc_sensorhub6_reg_t sh_byte_6; 2674 ism330dlc_sensorhub7_reg_t sh_byte_7; 2675 ism330dlc_sensorhub8_reg_t sh_byte_8; 2676 ism330dlc_sensorhub9_reg_t sh_byte_9; 2677 ism330dlc_sensorhub10_reg_t sh_byte_10; 2678 ism330dlc_sensorhub11_reg_t sh_byte_11; 2679 ism330dlc_sensorhub12_reg_t sh_byte_12; 2680 ism330dlc_sensorhub13_reg_t sh_byte_13; 2681 ism330dlc_sensorhub14_reg_t sh_byte_14; 2682 ism330dlc_sensorhub15_reg_t sh_byte_15; 2683 ism330dlc_sensorhub16_reg_t sh_byte_16; 2684 ism330dlc_sensorhub17_reg_t sh_byte_17; 2685 ism330dlc_sensorhub18_reg_t sh_byte_18; 2686 } ism330dlc_emb_sh_read_t; 2687 int32_t ism330dlc_sh_read_data_raw_get(const stmdev_ctx_t *ctx, 2688 ism330dlc_emb_sh_read_t *val); 2689 2690 int32_t ism330dlc_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, 2691 uint8_t val); 2692 int32_t ism330dlc_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, 2693 uint8_t *val); 2694 2695 int32_t ism330dlc_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, 2696 uint8_t val); 2697 int32_t ism330dlc_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, 2698 uint8_t *val); 2699 2700 typedef enum 2701 { 2702 ISM330DLC_NORMAL_MODE_READ = 0, 2703 ISM330DLC_SRC_MODE_READ = 1, 2704 } ism330dlc_src_mode_t; 2705 int32_t ism330dlc_sh_cfg_slave_0_rd_mode_set(const stmdev_ctx_t *ctx, 2706 ism330dlc_src_mode_t val); 2707 int32_t ism330dlc_sh_cfg_slave_0_rd_mode_get(const stmdev_ctx_t *ctx, 2708 ism330dlc_src_mode_t *val); 2709 2710 typedef enum 2711 { 2712 ISM330DLC_SLV_0 = 0, 2713 ISM330DLC_SLV_0_1 = 1, 2714 ISM330DLC_SLV_0_1_2 = 2, 2715 ISM330DLC_SLV_0_1_2_3 = 3, 2716 } ism330dlc_aux_sens_on_t; 2717 int32_t ism330dlc_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, 2718 ism330dlc_aux_sens_on_t val); 2719 int32_t ism330dlc_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, 2720 ism330dlc_aux_sens_on_t *val); 2721 2722 typedef struct 2723 { 2724 uint8_t slv0_add; 2725 uint8_t slv0_subadd; 2726 uint8_t slv0_data; 2727 } ism330dlc_sh_cfg_write_t; 2728 int32_t ism330dlc_sh_cfg_write(const stmdev_ctx_t *ctx, 2729 ism330dlc_sh_cfg_write_t *val); 2730 2731 typedef struct 2732 { 2733 uint8_t slv_add; 2734 uint8_t slv_subadd; 2735 uint8_t slv_len; 2736 } ism330dlc_sh_cfg_read_t; 2737 int32_t ism330dlc_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, 2738 ism330dlc_sh_cfg_read_t *val); 2739 int32_t ism330dlc_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, 2740 ism330dlc_sh_cfg_read_t *val); 2741 int32_t ism330dlc_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, 2742 ism330dlc_sh_cfg_read_t *val); 2743 int32_t ism330dlc_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, 2744 ism330dlc_sh_cfg_read_t *val); 2745 2746 typedef enum 2747 { 2748 ISM330DLC_SL0_NO_DEC = 0, 2749 ISM330DLC_SL0_DEC_2 = 1, 2750 ISM330DLC_SL0_DEC_4 = 2, 2751 ISM330DLC_SL0_DEC_8 = 3, 2752 } ism330dlc_slave0_rate_t; 2753 int32_t ism330dlc_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, 2754 ism330dlc_slave0_rate_t val); 2755 int32_t ism330dlc_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, 2756 ism330dlc_slave0_rate_t *val); 2757 2758 typedef enum 2759 { 2760 ISM330DLC_EACH_SH_CYCLE = 0, 2761 ISM330DLC_ONLY_FIRST_CYCLE = 1, 2762 } ism330dlc_write_once_t; 2763 int32_t ism330dlc_sh_write_mode_set(const stmdev_ctx_t *ctx, 2764 ism330dlc_write_once_t val); 2765 int32_t ism330dlc_sh_write_mode_get(const stmdev_ctx_t *ctx, 2766 ism330dlc_write_once_t *val); 2767 2768 typedef enum 2769 { 2770 ISM330DLC_SL1_NO_DEC = 0, 2771 ISM330DLC_SL1_DEC_2 = 1, 2772 ISM330DLC_SL1_DEC_4 = 2, 2773 ISM330DLC_SL1_DEC_8 = 3, 2774 } ism330dlc_slave1_rate_t; 2775 int32_t ism330dlc_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, 2776 ism330dlc_slave1_rate_t val); 2777 int32_t ism330dlc_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, 2778 ism330dlc_slave1_rate_t *val); 2779 2780 typedef enum 2781 { 2782 ISM330DLC_SL2_NO_DEC = 0, 2783 ISM330DLC_SL2_DEC_2 = 1, 2784 ISM330DLC_SL2_DEC_4 = 2, 2785 ISM330DLC_SL2_DEC_8 = 3, 2786 } ism330dlc_slave2_rate_t; 2787 int32_t ism330dlc_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, 2788 ism330dlc_slave2_rate_t val); 2789 int32_t ism330dlc_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, 2790 ism330dlc_slave2_rate_t *val); 2791 2792 typedef enum 2793 { 2794 ISM330DLC_SL3_NO_DEC = 0, 2795 ISM330DLC_SL3_DEC_2 = 1, 2796 ISM330DLC_SL3_DEC_4 = 2, 2797 ISM330DLC_SL3_DEC_8 = 3, 2798 } ism330dlc_slave3_rate_t; 2799 int32_t ism330dlc_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, 2800 ism330dlc_slave3_rate_t val); 2801 int32_t ism330dlc_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, 2802 ism330dlc_slave3_rate_t *val); 2803 2804 /** 2805 * @} 2806 * 2807 */ 2808 2809 #ifdef __cplusplus 2810 } 2811 #endif 2812 2813 #endif /* ISM330DLC_DRIVER_H */ 2814 2815 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2816
