1 /*--------------------------------------------------------------------------*/ 2 /* Copyright 2020-2021 NXP */ 3 /* */ 4 /* All rights are reserved. Reproduction in whole or in part is prohibited */ 5 /* without the prior written consent of the copy-right owner. */ 6 /* This source code and any compilation or derivative thereof is the sole */ 7 /* property of NXP N.V. and is provided pursuant to a Software License */ 8 /* Agreement. This code is the proprietary information of NXP N.V. and */ 9 /* is confidential in nature. Its use and dissemination by any party other */ 10 /* than NXP N.V. is strictly limited by the confidential information */ 11 /* provisions of the agreement referenced above. */ 12 /*--------------------------------------------------------------------------*/ 13 14 /** @file ip_platform.h 15 * @brief Include file for the IP. 16 * 17 * This includes the CMSIS for all of the functionality provided by the CSSv2 IP and provides support for external base 18 * address linking. */ 19 20 #ifndef IP_PLATFORM_H 21 #define IP_PLATFORM_H 22 23 #include "fsl_common.h" 24 #include "cssv2.h" 25 #include "fame3.h" 26 27 /* ================================================================================ */ 28 /* ================ Peripheral declaration ================ */ 29 /* ================================================================================ */ 30 31 #undef IP_CSS 32 #define IP_CSS ((ip_css_Type *)CSS_BASE) 33 34 #undef PKC 35 #undef PKC_BASE 36 #undef PKC_Type 37 #define PKC_BASE 0x5002F000UL 38 #define PKC ((ip_pkc_Type *)PKC_BASE) 39 #define PKC_Type ip_pkc_Type 40 41 // extern const uint32_t __ICFEDIT_region_RAM_PKC_start__; 42 //#define PKC_RAM_ADDR (&__ICFEDIT_region_RAM_PKC_start__) 43 #define PKC_RAM_ADDR (0x30002000) 44 #define PKC_RAM_SIZE 0x2000 // 8KB (second half of RAM bank A) 45 #define PKC_WORD_SIZE 8u 46 #define MCUXCL_FEATURE_ECC_MONTGOMERY_DH 47 48 49 #endif 50
