1 /***************************************************************************//** 2 * \file cyip_smif_v2.h 3 * 4 * \brief 5 * SMIF IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SMIF_V2_H_ 28 #define _CYIP_SMIF_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SMIF 34 *******************************************************************************/ 35 36 #define SMIF_DEVICE_SECTION_SIZE 0x00000080UL 37 #define SMIF_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Device (only used in XIP mode) (SMIF_DEVICE) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 44 __IM uint32_t RESERVED; 45 __IOM uint32_t ADDR; /*!< 0x00000008 Device region base address */ 46 __IOM uint32_t MASK; /*!< 0x0000000C Device region mask */ 47 __IM uint32_t RESERVED1[4]; 48 __IOM uint32_t ADDR_CTL; /*!< 0x00000020 Address control */ 49 __IM uint32_t RESERVED2[3]; 50 __IM uint32_t RD_STATUS; /*!< 0x00000030 Read status */ 51 __IM uint32_t RESERVED3[3]; 52 __IOM uint32_t RD_CMD_CTL; /*!< 0x00000040 Read command control */ 53 __IOM uint32_t RD_ADDR_CTL; /*!< 0x00000044 Read address control */ 54 __IOM uint32_t RD_MODE_CTL; /*!< 0x00000048 Read mode control */ 55 __IOM uint32_t RD_DUMMY_CTL; /*!< 0x0000004C Read dummy control */ 56 __IOM uint32_t RD_DATA_CTL; /*!< 0x00000050 Read data control */ 57 __IOM uint32_t RD_CRC_CTL; /*!< 0x00000054 Read Bus CRC control */ 58 __IOM uint32_t RD_BOUND_CTL; /*!< 0x00000058 Read boundary control */ 59 __IM uint32_t RESERVED4; 60 __IOM uint32_t WR_CMD_CTL; /*!< 0x00000060 Write command control */ 61 __IOM uint32_t WR_ADDR_CTL; /*!< 0x00000064 Write address control */ 62 __IOM uint32_t WR_MODE_CTL; /*!< 0x00000068 Write mode control */ 63 __IOM uint32_t WR_DUMMY_CTL; /*!< 0x0000006C Write dummy control */ 64 __IOM uint32_t WR_DATA_CTL; /*!< 0x00000070 Write data control */ 65 __IOM uint32_t WR_CRC_CTL; /*!< 0x00000074 Write Bus CRC control */ 66 __IM uint32_t RESERVED5[2]; 67 } SMIF_DEVICE_Type; /*!< Size = 128 (0x80) */ 68 69 /** 70 * \brief Serial Memory Interface (SMIF) 71 */ 72 typedef struct { 73 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 74 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 75 __IM uint32_t RESERVED[2]; 76 __IOM uint32_t INT_CLOCK_DELAY_TAP_SEL0; /*!< 0x00000010 Internal Clocking Delay Tap Select Register 0 */ 77 __IOM uint32_t INT_CLOCK_DELAY_TAP_SEL1; /*!< 0x00000014 Internal Clocking Delay Tap Select Register 1 */ 78 __IOM uint32_t DLP; /*!< 0x00000018 Data Learning Pattern */ 79 __IM uint32_t RESERVED1; 80 __IM uint32_t DL_STATUS0; /*!< 0x00000020 Data Learning Status Register 0 */ 81 __IM uint32_t DL_STATUS1; /*!< 0x00000024 Data Learning Status Register 1 */ 82 __IM uint32_t RESERVED2[2]; 83 __IOM uint32_t DELAY_TAP_SEL; /*!< 0x00000030 Delay Tap Select Register */ 84 __IM uint32_t RESERVED3[4]; 85 __IM uint32_t TX_CMD_FIFO_STATUS; /*!< 0x00000044 Transmitter command FIFO status */ 86 __IM uint32_t RESERVED4[2]; 87 __OM uint32_t TX_CMD_FIFO_WR; /*!< 0x00000050 Transmitter command FIFO write */ 88 __IM uint32_t RESERVED5[11]; 89 __IOM uint32_t TX_DATA_FIFO_CTL; /*!< 0x00000080 Transmitter data FIFO control */ 90 __IM uint32_t TX_DATA_FIFO_STATUS; /*!< 0x00000084 Transmitter data FIFO status */ 91 __IM uint32_t RESERVED6[2]; 92 __OM uint32_t TX_DATA_FIFO_WR1; /*!< 0x00000090 Transmitter data FIFO write */ 93 __OM uint32_t TX_DATA_FIFO_WR2; /*!< 0x00000094 Transmitter data FIFO write */ 94 __OM uint32_t TX_DATA_FIFO_WR4; /*!< 0x00000098 Transmitter data FIFO write */ 95 __OM uint32_t TX_DATA_FIFO_WR1ODD; /*!< 0x0000009C Transmitter data FIFO write */ 96 __IM uint32_t RESERVED7[8]; 97 __IOM uint32_t RX_DATA_MMIO_FIFO_CTL; /*!< 0x000000C0 Receiver data MMIO FIFO control */ 98 __IM uint32_t RX_DATA_MMIO_FIFO_STATUS; /*!< 0x000000C4 Receiver data MMIO FIFO status */ 99 __IM uint32_t RX_DATA_FIFO_STATUS; /*!< 0x000000C8 Receiver data FIFO status */ 100 __IM uint32_t RESERVED8; 101 __IM uint32_t RX_DATA_MMIO_FIFO_RD1; /*!< 0x000000D0 Receiver data MMIO FIFO read */ 102 __IM uint32_t RX_DATA_MMIO_FIFO_RD2; /*!< 0x000000D4 Receiver data MMIO FIFO read */ 103 __IM uint32_t RX_DATA_MMIO_FIFO_RD4; /*!< 0x000000D8 Receiver data MMIO FIFO read */ 104 __IM uint32_t RESERVED9; 105 __IM uint32_t RX_DATA_MMIO_FIFO_RD1_SILENT; /*!< 0x000000E0 Receiver data MMIO FIFO silent read */ 106 __IM uint32_t RESERVED10[7]; 107 __IOM uint32_t SLOW_CA_CTL; /*!< 0x00000100 Slow cache control */ 108 __IM uint32_t RESERVED11; 109 __IOM uint32_t SLOW_CA_CMD; /*!< 0x00000108 Slow cache command */ 110 __IM uint32_t RESERVED12[29]; 111 __IOM uint32_t FAST_CA_CTL; /*!< 0x00000180 Fast cache control */ 112 __IM uint32_t RESERVED13; 113 __IOM uint32_t FAST_CA_CMD; /*!< 0x00000188 Fast cache command */ 114 __IM uint32_t RESERVED14[29]; 115 __IOM uint32_t CRYPTO_CMD; /*!< 0x00000200 Cryptography Command */ 116 __IM uint32_t RESERVED15[7]; 117 __IOM uint32_t CRYPTO_INPUT0; /*!< 0x00000220 Cryptography input 0 */ 118 __IOM uint32_t CRYPTO_INPUT1; /*!< 0x00000224 Cryptography input 1 */ 119 __IOM uint32_t CRYPTO_INPUT2; /*!< 0x00000228 Cryptography input 2 */ 120 __IOM uint32_t CRYPTO_INPUT3; /*!< 0x0000022C Cryptography input 3 */ 121 __IM uint32_t RESERVED16[4]; 122 __OM uint32_t CRYPTO_KEY0; /*!< 0x00000240 Cryptography key 0 */ 123 __OM uint32_t CRYPTO_KEY1; /*!< 0x00000244 Cryptography key 1 */ 124 __OM uint32_t CRYPTO_KEY2; /*!< 0x00000248 Cryptography key 2 */ 125 __OM uint32_t CRYPTO_KEY3; /*!< 0x0000024C Cryptography key 3 */ 126 __IM uint32_t RESERVED17[4]; 127 __IOM uint32_t CRYPTO_OUTPUT0; /*!< 0x00000260 Cryptography output 0 */ 128 __IOM uint32_t CRYPTO_OUTPUT1; /*!< 0x00000264 Cryptography output 1 */ 129 __IOM uint32_t CRYPTO_OUTPUT2; /*!< 0x00000268 Cryptography output 2 */ 130 __IOM uint32_t CRYPTO_OUTPUT3; /*!< 0x0000026C Cryptography output 3 */ 131 __IM uint32_t RESERVED18[36]; 132 __IOM uint32_t CRC_CMD; /*!< 0x00000300 CRC Command */ 133 __IM uint32_t RESERVED19[7]; 134 __IOM uint32_t CRC_INPUT0; /*!< 0x00000320 CRC input 0 */ 135 __IOM uint32_t CRC_INPUT1; /*!< 0x00000324 CRC input 1 */ 136 __IM uint32_t RESERVED20[6]; 137 __IM uint32_t CRC_OUTPUT; /*!< 0x00000340 CRC output */ 138 __IM uint32_t RESERVED21[287]; 139 __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */ 140 __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */ 141 __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */ 142 __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */ 143 __IM uint32_t RESERVED22[12]; 144 SMIF_DEVICE_Type DEVICE[4]; /*!< 0x00000800 Device (only used in XIP mode) */ 145 } SMIF_Type; /*!< Size = 2560 (0xA00) */ 146 147 148 /* SMIF_DEVICE.CTL */ 149 #define SMIF_DEVICE_CTL_WR_EN_Pos 0UL 150 #define SMIF_DEVICE_CTL_WR_EN_Msk 0x1UL 151 #define SMIF_DEVICE_CTL_CRYPTO_EN_Pos 4UL 152 #define SMIF_DEVICE_CTL_CRYPTO_EN_Msk 0x10UL 153 #define SMIF_DEVICE_CTL_DATA_SEL_Pos 8UL 154 #define SMIF_DEVICE_CTL_DATA_SEL_Msk 0x300UL 155 #define SMIF_DEVICE_CTL_MERGE_TIMEOUT_Pos 12UL 156 #define SMIF_DEVICE_CTL_MERGE_TIMEOUT_Msk 0x7000UL 157 #define SMIF_DEVICE_CTL_MERGE_EN_Pos 15UL 158 #define SMIF_DEVICE_CTL_MERGE_EN_Msk 0x8000UL 159 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_Pos 16UL 160 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_Msk 0x3FFF0000UL 161 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_EN_Pos 30UL 162 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_EN_Msk 0x40000000UL 163 #define SMIF_DEVICE_CTL_ENABLED_Pos 31UL 164 #define SMIF_DEVICE_CTL_ENABLED_Msk 0x80000000UL 165 /* SMIF_DEVICE.ADDR */ 166 #define SMIF_DEVICE_ADDR_ADDR_Pos 8UL 167 #define SMIF_DEVICE_ADDR_ADDR_Msk 0xFFFFFF00UL 168 /* SMIF_DEVICE.MASK */ 169 #define SMIF_DEVICE_MASK_MASK_Pos 8UL 170 #define SMIF_DEVICE_MASK_MASK_Msk 0xFFFFFF00UL 171 /* SMIF_DEVICE.ADDR_CTL */ 172 #define SMIF_DEVICE_ADDR_CTL_SIZE3_Pos 0UL 173 #define SMIF_DEVICE_ADDR_CTL_SIZE3_Msk 0x7UL 174 #define SMIF_DEVICE_ADDR_CTL_DIV2_Pos 8UL 175 #define SMIF_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL 176 /* SMIF_DEVICE.RD_STATUS */ 177 #define SMIF_DEVICE_RD_STATUS_FS_STATUS_Pos 0UL 178 #define SMIF_DEVICE_RD_STATUS_FS_STATUS_Msk 0xFFUL 179 /* SMIF_DEVICE.RD_CMD_CTL */ 180 #define SMIF_DEVICE_RD_CMD_CTL_CODE_Pos 0UL 181 #define SMIF_DEVICE_RD_CMD_CTL_CODE_Msk 0xFFUL 182 #define SMIF_DEVICE_RD_CMD_CTL_CODEH_Pos 8UL 183 #define SMIF_DEVICE_RD_CMD_CTL_CODEH_Msk 0xFF00UL 184 #define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Pos 16UL 185 #define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Msk 0x30000UL 186 #define SMIF_DEVICE_RD_CMD_CTL_DDR_MODE_Pos 18UL 187 #define SMIF_DEVICE_RD_CMD_CTL_DDR_MODE_Msk 0x40000UL 188 #define SMIF_DEVICE_RD_CMD_CTL_PRESENT2_Pos 30UL 189 #define SMIF_DEVICE_RD_CMD_CTL_PRESENT2_Msk 0xC0000000UL 190 /* SMIF_DEVICE.RD_ADDR_CTL */ 191 #define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Pos 16UL 192 #define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Msk 0x30000UL 193 #define SMIF_DEVICE_RD_ADDR_CTL_DDR_MODE_Pos 18UL 194 #define SMIF_DEVICE_RD_ADDR_CTL_DDR_MODE_Msk 0x40000UL 195 /* SMIF_DEVICE.RD_MODE_CTL */ 196 #define SMIF_DEVICE_RD_MODE_CTL_CODE_Pos 0UL 197 #define SMIF_DEVICE_RD_MODE_CTL_CODE_Msk 0xFFUL 198 #define SMIF_DEVICE_RD_MODE_CTL_CODEH_Pos 8UL 199 #define SMIF_DEVICE_RD_MODE_CTL_CODEH_Msk 0xFF00UL 200 #define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Pos 16UL 201 #define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Msk 0x30000UL 202 #define SMIF_DEVICE_RD_MODE_CTL_DDR_MODE_Pos 18UL 203 #define SMIF_DEVICE_RD_MODE_CTL_DDR_MODE_Msk 0x40000UL 204 #define SMIF_DEVICE_RD_MODE_CTL_PRESENT2_Pos 30UL 205 #define SMIF_DEVICE_RD_MODE_CTL_PRESENT2_Msk 0xC0000000UL 206 /* SMIF_DEVICE.RD_DUMMY_CTL */ 207 #define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Pos 0UL 208 #define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Msk 0x1FUL 209 #define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT2_Pos 30UL 210 #define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT2_Msk 0xC0000000UL 211 /* SMIF_DEVICE.RD_DATA_CTL */ 212 #define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Pos 16UL 213 #define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Msk 0x30000UL 214 #define SMIF_DEVICE_RD_DATA_CTL_DDR_MODE_Pos 18UL 215 #define SMIF_DEVICE_RD_DATA_CTL_DDR_MODE_Msk 0x40000UL 216 /* SMIF_DEVICE.RD_CRC_CTL */ 217 #define SMIF_DEVICE_RD_CRC_CTL_STATUS_CHECK_MASK_Pos 0UL 218 #define SMIF_DEVICE_RD_CRC_CTL_STATUS_CHECK_MASK_Msk 0xFFUL 219 #define SMIF_DEVICE_RD_CRC_CTL_STATUS_ERROR_POL_Pos 8UL 220 #define SMIF_DEVICE_RD_CRC_CTL_STATUS_ERROR_POL_Msk 0xFF00UL 221 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_INPUT_SIZE_Pos 16UL 222 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_INPUT_SIZE_Msk 0xFF0000UL 223 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_WIDTH_Pos 24UL 224 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_WIDTH_Msk 0x3000000UL 225 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Pos 26UL 226 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Msk 0x4000000UL 227 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_INPUT_Pos 27UL 228 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_INPUT_Msk 0x8000000UL 229 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_CHECK_Pos 28UL 230 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_CHECK_Msk 0x10000000UL 231 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_PRESENT_Pos 30UL 232 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_PRESENT_Msk 0x40000000UL 233 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_PRESENT_Pos 31UL 234 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_PRESENT_Msk 0x80000000UL 235 /* SMIF_DEVICE.RD_BOUND_CTL */ 236 #define SMIF_DEVICE_RD_BOUND_CTL_SIZE5_Pos 0UL 237 #define SMIF_DEVICE_RD_BOUND_CTL_SIZE5_Msk 0x1FUL 238 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Pos 16UL 239 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Msk 0x30000UL 240 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Pos 20UL 241 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Msk 0x300000UL 242 #define SMIF_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Pos 28UL 243 #define SMIF_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Msk 0x10000000UL 244 #define SMIF_DEVICE_RD_BOUND_CTL_PRESENT_Pos 31UL 245 #define SMIF_DEVICE_RD_BOUND_CTL_PRESENT_Msk 0x80000000UL 246 /* SMIF_DEVICE.WR_CMD_CTL */ 247 #define SMIF_DEVICE_WR_CMD_CTL_CODE_Pos 0UL 248 #define SMIF_DEVICE_WR_CMD_CTL_CODE_Msk 0xFFUL 249 #define SMIF_DEVICE_WR_CMD_CTL_CODEH_Pos 8UL 250 #define SMIF_DEVICE_WR_CMD_CTL_CODEH_Msk 0xFF00UL 251 #define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Pos 16UL 252 #define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Msk 0x30000UL 253 #define SMIF_DEVICE_WR_CMD_CTL_DDR_MODE_Pos 18UL 254 #define SMIF_DEVICE_WR_CMD_CTL_DDR_MODE_Msk 0x40000UL 255 #define SMIF_DEVICE_WR_CMD_CTL_PRESENT2_Pos 30UL 256 #define SMIF_DEVICE_WR_CMD_CTL_PRESENT2_Msk 0xC0000000UL 257 /* SMIF_DEVICE.WR_ADDR_CTL */ 258 #define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Pos 16UL 259 #define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Msk 0x30000UL 260 #define SMIF_DEVICE_WR_ADDR_CTL_DDR_MODE_Pos 18UL 261 #define SMIF_DEVICE_WR_ADDR_CTL_DDR_MODE_Msk 0x40000UL 262 /* SMIF_DEVICE.WR_MODE_CTL */ 263 #define SMIF_DEVICE_WR_MODE_CTL_CODE_Pos 0UL 264 #define SMIF_DEVICE_WR_MODE_CTL_CODE_Msk 0xFFUL 265 #define SMIF_DEVICE_WR_MODE_CTL_CODEH_Pos 8UL 266 #define SMIF_DEVICE_WR_MODE_CTL_CODEH_Msk 0xFF00UL 267 #define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Pos 16UL 268 #define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Msk 0x30000UL 269 #define SMIF_DEVICE_WR_MODE_CTL_DDR_MODE_Pos 18UL 270 #define SMIF_DEVICE_WR_MODE_CTL_DDR_MODE_Msk 0x40000UL 271 #define SMIF_DEVICE_WR_MODE_CTL_PRESENT2_Pos 30UL 272 #define SMIF_DEVICE_WR_MODE_CTL_PRESENT2_Msk 0xC0000000UL 273 /* SMIF_DEVICE.WR_DUMMY_CTL */ 274 #define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Pos 0UL 275 #define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Msk 0x1FUL 276 #define SMIF_DEVICE_WR_DUMMY_CTL_RWDS_EN_Pos 17UL 277 #define SMIF_DEVICE_WR_DUMMY_CTL_RWDS_EN_Msk 0x20000UL 278 #define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT2_Pos 30UL 279 #define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT2_Msk 0xC0000000UL 280 /* SMIF_DEVICE.WR_DATA_CTL */ 281 #define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Pos 16UL 282 #define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Msk 0x30000UL 283 #define SMIF_DEVICE_WR_DATA_CTL_DDR_MODE_Pos 18UL 284 #define SMIF_DEVICE_WR_DATA_CTL_DDR_MODE_Msk 0x40000UL 285 /* SMIF_DEVICE.WR_CRC_CTL */ 286 #define SMIF_DEVICE_WR_CRC_CTL_DATA_CRC_INPUT_SIZE_Pos 16UL 287 #define SMIF_DEVICE_WR_CRC_CTL_DATA_CRC_INPUT_SIZE_Msk 0xFF0000UL 288 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_WIDTH_Pos 24UL 289 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_WIDTH_Msk 0x3000000UL 290 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Pos 26UL 291 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Msk 0x4000000UL 292 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_INPUT_Pos 27UL 293 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_INPUT_Msk 0x8000000UL 294 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_PRESENT_Pos 30UL 295 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_PRESENT_Msk 0x40000000UL 296 #define SMIF_DEVICE_WR_CRC_CTL_DATA_CRC_PRESENT_Pos 31UL 297 #define SMIF_DEVICE_WR_CRC_CTL_DATA_CRC_PRESENT_Msk 0x80000000UL 298 299 300 /* SMIF.CTL */ 301 #define SMIF_CTL_XIP_MODE_Pos 0UL 302 #define SMIF_CTL_XIP_MODE_Msk 0x1UL 303 #define SMIF_CTL_CLOCK_IF_TX_SEL_Pos 4UL 304 #define SMIF_CTL_CLOCK_IF_TX_SEL_Msk 0x10UL 305 #define SMIF_CTL_DELAY_LINE_SEL_Pos 5UL 306 #define SMIF_CTL_DELAY_LINE_SEL_Msk 0xE0UL 307 #define SMIF_CTL_DELAY_TAP_ENABLED_Pos 8UL 308 #define SMIF_CTL_DELAY_TAP_ENABLED_Msk 0x100UL 309 #define SMIF_CTL_INT_CLOCK_DL_ENABLED_Pos 9UL 310 #define SMIF_CTL_INT_CLOCK_DL_ENABLED_Msk 0x200UL 311 #define SMIF_CTL_INT_CLOCK_CAPTURE_CYCLE_Pos 10UL 312 #define SMIF_CTL_INT_CLOCK_CAPTURE_CYCLE_Msk 0xC00UL 313 #define SMIF_CTL_CLOCK_IF_RX_SEL_Pos 12UL 314 #define SMIF_CTL_CLOCK_IF_RX_SEL_Msk 0x7000UL 315 #define SMIF_CTL_DESELECT_DELAY_Pos 16UL 316 #define SMIF_CTL_DESELECT_DELAY_Msk 0x70000UL 317 #define SMIF_CTL_SELECT_SETUP_DELAY_Pos 20UL 318 #define SMIF_CTL_SELECT_SETUP_DELAY_Msk 0x300000UL 319 #define SMIF_CTL_SELECT_HOLD_DELAY_Pos 22UL 320 #define SMIF_CTL_SELECT_HOLD_DELAY_Msk 0xC00000UL 321 #define SMIF_CTL_BLOCK_Pos 24UL 322 #define SMIF_CTL_BLOCK_Msk 0x1000000UL 323 #define SMIF_CTL_ENABLED_Pos 31UL 324 #define SMIF_CTL_ENABLED_Msk 0x80000000UL 325 /* SMIF.STATUS */ 326 #define SMIF_STATUS_BUSY_Pos 31UL 327 #define SMIF_STATUS_BUSY_Msk 0x80000000UL 328 /* SMIF.INT_CLOCK_DELAY_TAP_SEL0 */ 329 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT0_Pos 0UL 330 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT0_Msk 0xFFUL 331 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT1_Pos 8UL 332 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT1_Msk 0xFF00UL 333 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT2_Pos 16UL 334 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT2_Msk 0xFF0000UL 335 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT3_Pos 24UL 336 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT3_Msk 0xFF000000UL 337 /* SMIF.INT_CLOCK_DELAY_TAP_SEL1 */ 338 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT4_Pos 0UL 339 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT4_Msk 0xFFUL 340 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT5_Pos 8UL 341 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT5_Msk 0xFF00UL 342 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT6_Pos 16UL 343 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT6_Msk 0xFF0000UL 344 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT7_Pos 24UL 345 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT7_Msk 0xFF000000UL 346 /* SMIF.DLP */ 347 #define SMIF_DLP_DLP_Pos 0UL 348 #define SMIF_DLP_DLP_Msk 0xFFUL 349 /* SMIF.DL_STATUS0 */ 350 #define SMIF_DL_STATUS0_DATA_BIT0_Pos 0UL 351 #define SMIF_DL_STATUS0_DATA_BIT0_Msk 0xFFUL 352 #define SMIF_DL_STATUS0_DATA_BIT1_Pos 8UL 353 #define SMIF_DL_STATUS0_DATA_BIT1_Msk 0xFF00UL 354 #define SMIF_DL_STATUS0_DATA_BIT2_Pos 16UL 355 #define SMIF_DL_STATUS0_DATA_BIT2_Msk 0xFF0000UL 356 #define SMIF_DL_STATUS0_DATA_BIT3_Pos 24UL 357 #define SMIF_DL_STATUS0_DATA_BIT3_Msk 0xFF000000UL 358 /* SMIF.DL_STATUS1 */ 359 #define SMIF_DL_STATUS1_DATA_BIT4_Pos 0UL 360 #define SMIF_DL_STATUS1_DATA_BIT4_Msk 0xFFUL 361 #define SMIF_DL_STATUS1_DATA_BIT5_Pos 8UL 362 #define SMIF_DL_STATUS1_DATA_BIT5_Msk 0xFF00UL 363 #define SMIF_DL_STATUS1_DATA_BIT6_Pos 16UL 364 #define SMIF_DL_STATUS1_DATA_BIT6_Msk 0xFF0000UL 365 #define SMIF_DL_STATUS1_DATA_BIT7_Pos 24UL 366 #define SMIF_DL_STATUS1_DATA_BIT7_Msk 0xFF000000UL 367 /* SMIF.DELAY_TAP_SEL */ 368 #define SMIF_DELAY_TAP_SEL_SEL_Pos 0UL 369 #define SMIF_DELAY_TAP_SEL_SEL_Msk 0xFFUL 370 /* SMIF.TX_CMD_FIFO_STATUS */ 371 #define SMIF_TX_CMD_FIFO_STATUS_USED4_Pos 0UL 372 #define SMIF_TX_CMD_FIFO_STATUS_USED4_Msk 0xFUL 373 /* SMIF.TX_CMD_FIFO_WR */ 374 #define SMIF_TX_CMD_FIFO_WR_DATA27_Pos 0UL 375 #define SMIF_TX_CMD_FIFO_WR_DATA27_Msk 0x7FFFFFFUL 376 /* SMIF.TX_DATA_FIFO_CTL */ 377 #define SMIF_TX_DATA_FIFO_CTL_TX_TRIGGER_LEVEL_Pos 0UL 378 #define SMIF_TX_DATA_FIFO_CTL_TX_TRIGGER_LEVEL_Msk 0x7UL 379 /* SMIF.TX_DATA_FIFO_STATUS */ 380 #define SMIF_TX_DATA_FIFO_STATUS_USED4_Pos 0UL 381 #define SMIF_TX_DATA_FIFO_STATUS_USED4_Msk 0xFUL 382 /* SMIF.TX_DATA_FIFO_WR1 */ 383 #define SMIF_TX_DATA_FIFO_WR1_DATA0_Pos 0UL 384 #define SMIF_TX_DATA_FIFO_WR1_DATA0_Msk 0xFFUL 385 /* SMIF.TX_DATA_FIFO_WR2 */ 386 #define SMIF_TX_DATA_FIFO_WR2_DATA0_Pos 0UL 387 #define SMIF_TX_DATA_FIFO_WR2_DATA0_Msk 0xFFUL 388 #define SMIF_TX_DATA_FIFO_WR2_DATA1_Pos 8UL 389 #define SMIF_TX_DATA_FIFO_WR2_DATA1_Msk 0xFF00UL 390 /* SMIF.TX_DATA_FIFO_WR4 */ 391 #define SMIF_TX_DATA_FIFO_WR4_DATA0_Pos 0UL 392 #define SMIF_TX_DATA_FIFO_WR4_DATA0_Msk 0xFFUL 393 #define SMIF_TX_DATA_FIFO_WR4_DATA1_Pos 8UL 394 #define SMIF_TX_DATA_FIFO_WR4_DATA1_Msk 0xFF00UL 395 #define SMIF_TX_DATA_FIFO_WR4_DATA2_Pos 16UL 396 #define SMIF_TX_DATA_FIFO_WR4_DATA2_Msk 0xFF0000UL 397 #define SMIF_TX_DATA_FIFO_WR4_DATA3_Pos 24UL 398 #define SMIF_TX_DATA_FIFO_WR4_DATA3_Msk 0xFF000000UL 399 /* SMIF.TX_DATA_FIFO_WR1ODD */ 400 #define SMIF_TX_DATA_FIFO_WR1ODD_DATA0_Pos 0UL 401 #define SMIF_TX_DATA_FIFO_WR1ODD_DATA0_Msk 0xFFUL 402 /* SMIF.RX_DATA_MMIO_FIFO_CTL */ 403 #define SMIF_RX_DATA_MMIO_FIFO_CTL_RX_TRIGGER_LEVEL_Pos 0UL 404 #define SMIF_RX_DATA_MMIO_FIFO_CTL_RX_TRIGGER_LEVEL_Msk 0x7UL 405 /* SMIF.RX_DATA_MMIO_FIFO_STATUS */ 406 #define SMIF_RX_DATA_MMIO_FIFO_STATUS_USED4_Pos 0UL 407 #define SMIF_RX_DATA_MMIO_FIFO_STATUS_USED4_Msk 0xFUL 408 /* SMIF.RX_DATA_FIFO_STATUS */ 409 #define SMIF_RX_DATA_FIFO_STATUS_USED5_Pos 0UL 410 #define SMIF_RX_DATA_FIFO_STATUS_USED5_Msk 0x1FUL 411 #define SMIF_RX_DATA_FIFO_STATUS_RX_SR_USED_Pos 8UL 412 #define SMIF_RX_DATA_FIFO_STATUS_RX_SR_USED_Msk 0x100UL 413 /* SMIF.RX_DATA_MMIO_FIFO_RD1 */ 414 #define SMIF_RX_DATA_MMIO_FIFO_RD1_DATA0_Pos 0UL 415 #define SMIF_RX_DATA_MMIO_FIFO_RD1_DATA0_Msk 0xFFUL 416 /* SMIF.RX_DATA_MMIO_FIFO_RD2 */ 417 #define SMIF_RX_DATA_MMIO_FIFO_RD2_DATA0_Pos 0UL 418 #define SMIF_RX_DATA_MMIO_FIFO_RD2_DATA0_Msk 0xFFUL 419 #define SMIF_RX_DATA_MMIO_FIFO_RD2_DATA1_Pos 8UL 420 #define SMIF_RX_DATA_MMIO_FIFO_RD2_DATA1_Msk 0xFF00UL 421 /* SMIF.RX_DATA_MMIO_FIFO_RD4 */ 422 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA0_Pos 0UL 423 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA0_Msk 0xFFUL 424 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA1_Pos 8UL 425 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA1_Msk 0xFF00UL 426 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA2_Pos 16UL 427 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA2_Msk 0xFF0000UL 428 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA3_Pos 24UL 429 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA3_Msk 0xFF000000UL 430 /* SMIF.RX_DATA_MMIO_FIFO_RD1_SILENT */ 431 #define SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT_DATA0_Pos 0UL 432 #define SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT_DATA0_Msk 0xFFUL 433 /* SMIF.SLOW_CA_CTL */ 434 #define SMIF_SLOW_CA_CTL_WAY_Pos 16UL 435 #define SMIF_SLOW_CA_CTL_WAY_Msk 0x30000UL 436 #define SMIF_SLOW_CA_CTL_SET_ADDR_Pos 24UL 437 #define SMIF_SLOW_CA_CTL_SET_ADDR_Msk 0x3000000UL 438 #define SMIF_SLOW_CA_CTL_PREF_EN_Pos 30UL 439 #define SMIF_SLOW_CA_CTL_PREF_EN_Msk 0x40000000UL 440 #define SMIF_SLOW_CA_CTL_ENABLED_Pos 31UL 441 #define SMIF_SLOW_CA_CTL_ENABLED_Msk 0x80000000UL 442 /* SMIF.SLOW_CA_CMD */ 443 #define SMIF_SLOW_CA_CMD_INV_Pos 0UL 444 #define SMIF_SLOW_CA_CMD_INV_Msk 0x1UL 445 /* SMIF.FAST_CA_CTL */ 446 #define SMIF_FAST_CA_CTL_WAY_Pos 16UL 447 #define SMIF_FAST_CA_CTL_WAY_Msk 0x30000UL 448 #define SMIF_FAST_CA_CTL_SET_ADDR_Pos 24UL 449 #define SMIF_FAST_CA_CTL_SET_ADDR_Msk 0x3000000UL 450 #define SMIF_FAST_CA_CTL_PREF_EN_Pos 30UL 451 #define SMIF_FAST_CA_CTL_PREF_EN_Msk 0x40000000UL 452 #define SMIF_FAST_CA_CTL_ENABLED_Pos 31UL 453 #define SMIF_FAST_CA_CTL_ENABLED_Msk 0x80000000UL 454 /* SMIF.FAST_CA_CMD */ 455 #define SMIF_FAST_CA_CMD_INV_Pos 0UL 456 #define SMIF_FAST_CA_CMD_INV_Msk 0x1UL 457 /* SMIF.CRYPTO_CMD */ 458 #define SMIF_CRYPTO_CMD_START_Pos 0UL 459 #define SMIF_CRYPTO_CMD_START_Msk 0x1UL 460 /* SMIF.CRYPTO_INPUT0 */ 461 #define SMIF_CRYPTO_INPUT0_INPUT_Pos 0UL 462 #define SMIF_CRYPTO_INPUT0_INPUT_Msk 0xFFFFFFFFUL 463 /* SMIF.CRYPTO_INPUT1 */ 464 #define SMIF_CRYPTO_INPUT1_INPUT_Pos 0UL 465 #define SMIF_CRYPTO_INPUT1_INPUT_Msk 0xFFFFFFFFUL 466 /* SMIF.CRYPTO_INPUT2 */ 467 #define SMIF_CRYPTO_INPUT2_INPUT_Pos 0UL 468 #define SMIF_CRYPTO_INPUT2_INPUT_Msk 0xFFFFFFFFUL 469 /* SMIF.CRYPTO_INPUT3 */ 470 #define SMIF_CRYPTO_INPUT3_INPUT_Pos 0UL 471 #define SMIF_CRYPTO_INPUT3_INPUT_Msk 0xFFFFFFFFUL 472 /* SMIF.CRYPTO_KEY0 */ 473 #define SMIF_CRYPTO_KEY0_KEY_Pos 0UL 474 #define SMIF_CRYPTO_KEY0_KEY_Msk 0xFFFFFFFFUL 475 /* SMIF.CRYPTO_KEY1 */ 476 #define SMIF_CRYPTO_KEY1_KEY_Pos 0UL 477 #define SMIF_CRYPTO_KEY1_KEY_Msk 0xFFFFFFFFUL 478 /* SMIF.CRYPTO_KEY2 */ 479 #define SMIF_CRYPTO_KEY2_KEY_Pos 0UL 480 #define SMIF_CRYPTO_KEY2_KEY_Msk 0xFFFFFFFFUL 481 /* SMIF.CRYPTO_KEY3 */ 482 #define SMIF_CRYPTO_KEY3_KEY_Pos 0UL 483 #define SMIF_CRYPTO_KEY3_KEY_Msk 0xFFFFFFFFUL 484 /* SMIF.CRYPTO_OUTPUT0 */ 485 #define SMIF_CRYPTO_OUTPUT0_OUTPUT_Pos 0UL 486 #define SMIF_CRYPTO_OUTPUT0_OUTPUT_Msk 0xFFFFFFFFUL 487 /* SMIF.CRYPTO_OUTPUT1 */ 488 #define SMIF_CRYPTO_OUTPUT1_OUTPUT_Pos 0UL 489 #define SMIF_CRYPTO_OUTPUT1_OUTPUT_Msk 0xFFFFFFFFUL 490 /* SMIF.CRYPTO_OUTPUT2 */ 491 #define SMIF_CRYPTO_OUTPUT2_OUTPUT_Pos 0UL 492 #define SMIF_CRYPTO_OUTPUT2_OUTPUT_Msk 0xFFFFFFFFUL 493 /* SMIF.CRYPTO_OUTPUT3 */ 494 #define SMIF_CRYPTO_OUTPUT3_OUTPUT_Pos 0UL 495 #define SMIF_CRYPTO_OUTPUT3_OUTPUT_Msk 0xFFFFFFFFUL 496 /* SMIF.CRC_CMD */ 497 #define SMIF_CRC_CMD_START_Pos 0UL 498 #define SMIF_CRC_CMD_START_Msk 0x1UL 499 #define SMIF_CRC_CMD_CONTINUE_Pos 1UL 500 #define SMIF_CRC_CMD_CONTINUE_Msk 0x2UL 501 /* SMIF.CRC_INPUT0 */ 502 #define SMIF_CRC_INPUT0_INPUT_Pos 0UL 503 #define SMIF_CRC_INPUT0_INPUT_Msk 0xFFFFFFFFUL 504 /* SMIF.CRC_INPUT1 */ 505 #define SMIF_CRC_INPUT1_INPUT_Pos 0UL 506 #define SMIF_CRC_INPUT1_INPUT_Msk 0xFFFFFFFFUL 507 /* SMIF.CRC_OUTPUT */ 508 #define SMIF_CRC_OUTPUT_CRC_OUTPUT_Pos 0UL 509 #define SMIF_CRC_OUTPUT_CRC_OUTPUT_Msk 0xFFUL 510 /* SMIF.INTR */ 511 #define SMIF_INTR_TR_TX_REQ_Pos 0UL 512 #define SMIF_INTR_TR_TX_REQ_Msk 0x1UL 513 #define SMIF_INTR_TR_RX_REQ_Pos 1UL 514 #define SMIF_INTR_TR_RX_REQ_Msk 0x2UL 515 #define SMIF_INTR_XIP_ALIGNMENT_ERROR_Pos 2UL 516 #define SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk 0x4UL 517 #define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Pos 3UL 518 #define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 519 #define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Pos 4UL 520 #define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 521 #define SMIF_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 522 #define SMIF_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 523 #define SMIF_INTR_DL_FAIL_Pos 8UL 524 #define SMIF_INTR_DL_FAIL_Msk 0x100UL 525 #define SMIF_INTR_DL_WARNING_Pos 12UL 526 #define SMIF_INTR_DL_WARNING_Msk 0x1000UL 527 #define SMIF_INTR_CRC_ERROR_Pos 16UL 528 #define SMIF_INTR_CRC_ERROR_Msk 0x10000UL 529 #define SMIF_INTR_FS_STATUS_ERROR_Pos 17UL 530 #define SMIF_INTR_FS_STATUS_ERROR_Msk 0x20000UL 531 /* SMIF.INTR_SET */ 532 #define SMIF_INTR_SET_TR_TX_REQ_Pos 0UL 533 #define SMIF_INTR_SET_TR_TX_REQ_Msk 0x1UL 534 #define SMIF_INTR_SET_TR_RX_REQ_Pos 1UL 535 #define SMIF_INTR_SET_TR_RX_REQ_Msk 0x2UL 536 #define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Pos 2UL 537 #define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Msk 0x4UL 538 #define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Pos 3UL 539 #define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 540 #define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Pos 4UL 541 #define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 542 #define SMIF_INTR_SET_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 543 #define SMIF_INTR_SET_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 544 #define SMIF_INTR_SET_DL_FAIL_Pos 8UL 545 #define SMIF_INTR_SET_DL_FAIL_Msk 0x100UL 546 #define SMIF_INTR_SET_DL_WARNING_Pos 12UL 547 #define SMIF_INTR_SET_DL_WARNING_Msk 0x1000UL 548 #define SMIF_INTR_SET_CRC_ERROR_Pos 16UL 549 #define SMIF_INTR_SET_CRC_ERROR_Msk 0x10000UL 550 #define SMIF_INTR_SET_FS_STATUS_ERROR_Pos 17UL 551 #define SMIF_INTR_SET_FS_STATUS_ERROR_Msk 0x20000UL 552 /* SMIF.INTR_MASK */ 553 #define SMIF_INTR_MASK_TR_TX_REQ_Pos 0UL 554 #define SMIF_INTR_MASK_TR_TX_REQ_Msk 0x1UL 555 #define SMIF_INTR_MASK_TR_RX_REQ_Pos 1UL 556 #define SMIF_INTR_MASK_TR_RX_REQ_Msk 0x2UL 557 #define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Pos 2UL 558 #define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Msk 0x4UL 559 #define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Pos 3UL 560 #define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 561 #define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Pos 4UL 562 #define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 563 #define SMIF_INTR_MASK_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 564 #define SMIF_INTR_MASK_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 565 #define SMIF_INTR_MASK_DL_FAIL_Pos 8UL 566 #define SMIF_INTR_MASK_DL_FAIL_Msk 0x100UL 567 #define SMIF_INTR_MASK_DL_WARNING_Pos 12UL 568 #define SMIF_INTR_MASK_DL_WARNING_Msk 0x1000UL 569 #define SMIF_INTR_MASK_CRC_ERROR_Pos 16UL 570 #define SMIF_INTR_MASK_CRC_ERROR_Msk 0x10000UL 571 #define SMIF_INTR_MASK_FS_STATUS_ERROR_Pos 17UL 572 #define SMIF_INTR_MASK_FS_STATUS_ERROR_Msk 0x20000UL 573 /* SMIF.INTR_MASKED */ 574 #define SMIF_INTR_MASKED_TR_TX_REQ_Pos 0UL 575 #define SMIF_INTR_MASKED_TR_TX_REQ_Msk 0x1UL 576 #define SMIF_INTR_MASKED_TR_RX_REQ_Pos 1UL 577 #define SMIF_INTR_MASKED_TR_RX_REQ_Msk 0x2UL 578 #define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Pos 2UL 579 #define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Msk 0x4UL 580 #define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Pos 3UL 581 #define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 582 #define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Pos 4UL 583 #define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 584 #define SMIF_INTR_MASKED_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 585 #define SMIF_INTR_MASKED_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 586 #define SMIF_INTR_MASKED_DL_FAIL_Pos 8UL 587 #define SMIF_INTR_MASKED_DL_FAIL_Msk 0x100UL 588 #define SMIF_INTR_MASKED_DL_WARNING_Pos 12UL 589 #define SMIF_INTR_MASKED_DL_WARNING_Msk 0x1000UL 590 #define SMIF_INTR_MASKED_CRC_ERROR_Pos 16UL 591 #define SMIF_INTR_MASKED_CRC_ERROR_Msk 0x10000UL 592 #define SMIF_INTR_MASKED_FS_STATUS_ERROR_Pos 17UL 593 #define SMIF_INTR_MASKED_FS_STATUS_ERROR_Msk 0x20000UL 594 595 596 #endif /* _CYIP_SMIF_V2_H_ */ 597 598 599 /* [] END OF FILE */ 600
