1 /***************************************************************************//**
2 * \file cyip_smartio_v3.h
3 *
4 * \brief
5 * SMARTIO IP definitions
6 *
7 ********************************************************************************
8 * \copyright
9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 *     http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26 
27 #ifndef _CYIP_SMARTIO_V3_H_
28 #define _CYIP_SMARTIO_V3_H_
29 
30 #include "cyip_headers.h"
31 
32 /*******************************************************************************
33 *                                   SMARTIO
34 *******************************************************************************/
35 
36 #define SMARTIO_PRT_SECTION_SIZE                0x00000100UL
37 #define SMARTIO_SECTION_SIZE                    0x00010000UL
38 
39 /**
40   * \brief Programmable IO port registers (SMARTIO_PRT)
41   */
42 typedef struct {
43   __IOM uint32_t CTL;                           /*!< 0x00000000 Control register */
44    __IM uint32_t RESERVED[3];
45   __IOM uint32_t SYNC_CTL;                      /*!< 0x00000010 Synchronization control register */
46    __IM uint32_t RESERVED1[3];
47   __IOM uint32_t LUT_SEL[8];                    /*!< 0x00000020 LUT component input selection */
48   __IOM uint32_t LUT_CTL[8];                    /*!< 0x00000040 LUT component control register */
49    __IM uint32_t RESERVED2[24];
50   __IOM uint32_t DU_SEL;                        /*!< 0x000000C0 Data unit component input selection */
51   __IOM uint32_t DU_CTL;                        /*!< 0x000000C4 Data unit component control register */
52    __IM uint32_t RESERVED3[10];
53   __IOM uint32_t DATA;                          /*!< 0x000000F0 Data register */
54    __IM uint32_t RESERVED4[3];
55 } SMARTIO_PRT_Type;                             /*!< Size = 256 (0x100) */
56 
57 /**
58   * \brief Programmable IO configuration (SMARTIO)
59   */
60 typedef struct {
61         SMARTIO_PRT_Type PRT[128];              /*!< 0x00000000 Programmable IO port registers */
62 } SMARTIO_Type;                                 /*!< Size = 32768 (0x8000) */
63 
64 
65 /* SMARTIO_PRT.CTL */
66 #define SMARTIO_PRT_CTL_BYPASS_Pos              0UL
67 #define SMARTIO_PRT_CTL_BYPASS_Msk              0xFFUL
68 #define SMARTIO_PRT_CTL_CLOCK_SRC_Pos           8UL
69 #define SMARTIO_PRT_CTL_CLOCK_SRC_Msk           0x1F00UL
70 #define SMARTIO_PRT_CTL_HLD_OVR_Pos             24UL
71 #define SMARTIO_PRT_CTL_HLD_OVR_Msk             0x1000000UL
72 #define SMARTIO_PRT_CTL_PIPELINE_EN_Pos         25UL
73 #define SMARTIO_PRT_CTL_PIPELINE_EN_Msk         0x2000000UL
74 #define SMARTIO_PRT_CTL_ENABLED_Pos             31UL
75 #define SMARTIO_PRT_CTL_ENABLED_Msk             0x80000000UL
76 /* SMARTIO_PRT.SYNC_CTL */
77 #define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Pos     0UL
78 #define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk     0xFFUL
79 #define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Pos   8UL
80 #define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk   0xFF00UL
81 /* SMARTIO_PRT.LUT_SEL */
82 #define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Pos     0UL
83 #define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk     0xFUL
84 #define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Pos     8UL
85 #define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk     0xF00UL
86 #define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Pos     16UL
87 #define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk     0xF0000UL
88 /* SMARTIO_PRT.LUT_CTL */
89 #define SMARTIO_PRT_LUT_CTL_LUT_Pos             0UL
90 #define SMARTIO_PRT_LUT_CTL_LUT_Msk             0xFFUL
91 #define SMARTIO_PRT_LUT_CTL_LUT_OPC_Pos         8UL
92 #define SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk         0x300UL
93 /* SMARTIO_PRT.DU_SEL */
94 #define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Pos       0UL
95 #define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk       0xFUL
96 #define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Pos       8UL
97 #define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk       0xF00UL
98 #define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Pos       16UL
99 #define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk       0xF0000UL
100 #define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Pos     24UL
101 #define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Msk     0x3000000UL
102 #define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Pos     28UL
103 #define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk     0x30000000UL
104 /* SMARTIO_PRT.DU_CTL */
105 #define SMARTIO_PRT_DU_CTL_DU_SIZE_Pos          0UL
106 #define SMARTIO_PRT_DU_CTL_DU_SIZE_Msk          0x7UL
107 #define SMARTIO_PRT_DU_CTL_DU_OPC_Pos           8UL
108 #define SMARTIO_PRT_DU_CTL_DU_OPC_Msk           0xF00UL
109 /* SMARTIO_PRT.DATA */
110 #define SMARTIO_PRT_DATA_DATA_Pos               0UL
111 #define SMARTIO_PRT_DATA_DATA_Msk               0xFFUL
112 
113 
114 #endif /* _CYIP_SMARTIO_V3_H_ */
115 
116 
117 /* [] END OF FILE */
118