1 /***************************************************************************//** 2 * \file cyip_ramc_ppu.h 3 * 4 * \brief 5 * RAMC_PPU IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_RAMC_PPU_H_ 28 #define _CYIP_RAMC_PPU_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * RAMC_PPU 34 *******************************************************************************/ 35 36 #define RAMC_PPU_SECTION_SIZE 0x00001000UL 37 38 /** 39 * \brief Power Policy Unit Registers for System RAM (RAMC_PPU) 40 */ 41 typedef struct { 42 __IOM uint32_t PWPR; /*!< 0x00000000 Power Policy Register */ 43 __IOM uint32_t PMER; /*!< 0x00000004 Power Mode Emulation Register */ 44 __IM uint32_t PWSR; /*!< 0x00000008 Power Status Register */ 45 __IM uint32_t RESERVED; 46 __IM uint32_t DISR; /*!< 0x00000010 Device Interface Input Current Status Register */ 47 __IM uint32_t MISR; /*!< 0x00000014 Miscellaneous Input Current Status Register */ 48 __IM uint32_t STSR; /*!< 0x00000018 Stored Status Register */ 49 __IOM uint32_t UNLK; /*!< 0x0000001C Unlock register */ 50 __IOM uint32_t PWCR; /*!< 0x00000020 Power Configuration Register */ 51 __IOM uint32_t PTCR; /*!< 0x00000024 Power Mode Transition Configuration Register */ 52 __IM uint32_t RESERVED1[2]; 53 __IOM uint32_t IMR; /*!< 0x00000030 Interrupt Mask Register */ 54 __IOM uint32_t AIMR; /*!< 0x00000034 Additional Interrupt Mask Register */ 55 __IOM uint32_t ISR; /*!< 0x00000038 Interrupt Status Register */ 56 __IOM uint32_t AISR; /*!< 0x0000003C Additional Interrupt Status Register */ 57 __IOM uint32_t IESR; /*!< 0x00000040 Input Edge Sensitivity Register */ 58 __IOM uint32_t OPSR; /*!< 0x00000044 Operating Mode Active Edge Sensitivity Register */ 59 __IM uint32_t RESERVED2[2]; 60 __IOM uint32_t FUNRR; /*!< 0x00000050 Functional Retention RAM Configuration Register */ 61 __IOM uint32_t FULRR; /*!< 0x00000054 Full Retention RAM Configuration Register */ 62 __IOM uint32_t MEMRR; /*!< 0x00000058 Memory Retention RAM Configuration Register */ 63 __IM uint32_t RESERVED3[65]; 64 __IOM uint32_t EDTR0; /*!< 0x00000160 Power Mode Entry Delay Register 0 */ 65 __IOM uint32_t EDTR1; /*!< 0x00000164 Power Mode Entry Delay Register 1 */ 66 __IM uint32_t RESERVED4[2]; 67 __IM uint32_t DCDR0; /*!< 0x00000170 Device Control Delay Configuration Register 0 */ 68 __IM uint32_t DCDR1; /*!< 0x00000174 Device Control Delay Configuration Register 1 */ 69 __IM uint32_t RESERVED5[910]; 70 __IM uint32_t IDR0; /*!< 0x00000FB0 PPU Identification Register 0 */ 71 __IM uint32_t IDR1; /*!< 0x00000FB4 PPU Identification Register 1 */ 72 __IM uint32_t RESERVED6[4]; 73 __IM uint32_t IIDR; /*!< 0x00000FC8 Implementation Identification Register */ 74 __IM uint32_t AIDR; /*!< 0x00000FCC Architecture Identification Register */ 75 __IM uint32_t PID4; /*!< 0x00000FD0 Implementation Defined Identification Register (PID4) */ 76 __IM uint32_t RESERVED7[3]; 77 __IM uint32_t PID0; /*!< 0x00000FE0 Implementation Defined Identification Register (PID0) */ 78 __IM uint32_t PID1; /*!< 0x00000FE4 Implementation Defined Identification Register (PID1) */ 79 __IM uint32_t PID2; /*!< 0x00000FE8 Implementation Defined Identification Register (PID2) */ 80 __IM uint32_t PID3; /*!< 0x00000FEC Implementation Defined Identification Register (PID3) */ 81 __IM uint32_t ID0; /*!< 0x00000FF0 Implementation Defined Identification Register (ID0) */ 82 __IM uint32_t ID1; /*!< 0x00000FF4 Implementation Defined Identification Register (ID1) */ 83 __IM uint32_t ID2; /*!< 0x00000FF8 Implementation Defined Identification Register (ID2) */ 84 __IM uint32_t ID3; /*!< 0x00000FFC Implementation Defined Identification Register (ID3) */ 85 } RAMC_PPU_Type; /*!< Size = 4096 (0x1000) */ 86 87 88 /* RAMC_PPU.PWPR */ 89 #define RAMC_PPU_PWPR_PWR_POLICY_Pos 0UL 90 #define RAMC_PPU_PWPR_PWR_POLICY_Msk 0xFUL 91 #define RAMC_PPU_PWPR_PWR_DYN_EN_Pos 8UL 92 #define RAMC_PPU_PWPR_PWR_DYN_EN_Msk 0x100UL 93 #define RAMC_PPU_PWPR_LOCK_EN_Pos 12UL 94 #define RAMC_PPU_PWPR_LOCK_EN_Msk 0x1000UL 95 #define RAMC_PPU_PWPR_OP_POLICY_Pos 16UL 96 #define RAMC_PPU_PWPR_OP_POLICY_Msk 0xF0000UL 97 #define RAMC_PPU_PWPR_OP_DYN_EN_Pos 24UL 98 #define RAMC_PPU_PWPR_OP_DYN_EN_Msk 0x1000000UL 99 /* RAMC_PPU.PMER */ 100 #define RAMC_PPU_PMER_EMU_EN_Pos 0UL 101 #define RAMC_PPU_PMER_EMU_EN_Msk 0x1UL 102 /* RAMC_PPU.PWSR */ 103 #define RAMC_PPU_PWSR_PWR_STATUS_Pos 0UL 104 #define RAMC_PPU_PWSR_PWR_STATUS_Msk 0xFUL 105 #define RAMC_PPU_PWSR_PWR_DYN_STATUS_Pos 8UL 106 #define RAMC_PPU_PWSR_PWR_DYN_STATUS_Msk 0x100UL 107 #define RAMC_PPU_PWSR_LOCK_STATUS_Pos 12UL 108 #define RAMC_PPU_PWSR_LOCK_STATUS_Msk 0x1000UL 109 #define RAMC_PPU_PWSR_OP_STATUS_Pos 16UL 110 #define RAMC_PPU_PWSR_OP_STATUS_Msk 0xF0000UL 111 #define RAMC_PPU_PWSR_OP_DYN_STATUS_Pos 24UL 112 #define RAMC_PPU_PWSR_OP_DYN_STATUS_Msk 0x1000000UL 113 /* RAMC_PPU.DISR */ 114 #define RAMC_PPU_DISR_PWR_DEVACTIVE_STATUS_Pos 0UL 115 #define RAMC_PPU_DISR_PWR_DEVACTIVE_STATUS_Msk 0x7FFUL 116 #define RAMC_PPU_DISR_OP_DEVACTIVE_STATUS_Pos 24UL 117 #define RAMC_PPU_DISR_OP_DEVACTIVE_STATUS_Msk 0xFF000000UL 118 /* RAMC_PPU.MISR */ 119 #define RAMC_PPU_MISR_PCSMPACCEPT_STATUS_Pos 0UL 120 #define RAMC_PPU_MISR_PCSMPACCEPT_STATUS_Msk 0x1UL 121 #define RAMC_PPU_MISR_DEVACCEPT_STATUS_Pos 8UL 122 #define RAMC_PPU_MISR_DEVACCEPT_STATUS_Msk 0xFF00UL 123 #define RAMC_PPU_MISR_DEVDENY_STATUS_Pos 16UL 124 #define RAMC_PPU_MISR_DEVDENY_STATUS_Msk 0xFF0000UL 125 /* RAMC_PPU.STSR */ 126 #define RAMC_PPU_STSR_STORED_DEVDENY_Pos 0UL 127 #define RAMC_PPU_STSR_STORED_DEVDENY_Msk 0xFFUL 128 /* RAMC_PPU.UNLK */ 129 #define RAMC_PPU_UNLK_UNLOCK_Pos 0UL 130 #define RAMC_PPU_UNLK_UNLOCK_Msk 0x1UL 131 /* RAMC_PPU.PWCR */ 132 #define RAMC_PPU_PWCR_DEVREQEN_Pos 0UL 133 #define RAMC_PPU_PWCR_DEVREQEN_Msk 0xFFUL 134 #define RAMC_PPU_PWCR_PWR_DEVACTIVEEN_Pos 8UL 135 #define RAMC_PPU_PWCR_PWR_DEVACTIVEEN_Msk 0x7FF00UL 136 #define RAMC_PPU_PWCR_OP_DEVACTIVEEN_Pos 24UL 137 #define RAMC_PPU_PWCR_OP_DEVACTIVEEN_Msk 0xFF000000UL 138 /* RAMC_PPU.PTCR */ 139 #define RAMC_PPU_PTCR_WARM_RST_DEVREQEN_Pos 0UL 140 #define RAMC_PPU_PTCR_WARM_RST_DEVREQEN_Msk 0x1UL 141 #define RAMC_PPU_PTCR_DBG_RECOV_PORST_EN_Pos 1UL 142 #define RAMC_PPU_PTCR_DBG_RECOV_PORST_EN_Msk 0x2UL 143 /* RAMC_PPU.IMR */ 144 #define RAMC_PPU_IMR_STA_POLICY_TRN_IRQ_MASK_Pos 0UL 145 #define RAMC_PPU_IMR_STA_POLICY_TRN_IRQ_MASK_Msk 0x1UL 146 #define RAMC_PPU_IMR_STA_ACCEPT_IRQ_MASK_Pos 1UL 147 #define RAMC_PPU_IMR_STA_ACCEPT_IRQ_MASK_Msk 0x2UL 148 #define RAMC_PPU_IMR_STA_DENY_IRQ_MASK_Pos 2UL 149 #define RAMC_PPU_IMR_STA_DENY_IRQ_MASK_Msk 0x4UL 150 #define RAMC_PPU_IMR_EMU_ACCEPT_IRQ_MASK_Pos 3UL 151 #define RAMC_PPU_IMR_EMU_ACCEPT_IRQ_MASK_Msk 0x8UL 152 #define RAMC_PPU_IMR_EMU_DENY_IRQ_MASK_Pos 4UL 153 #define RAMC_PPU_IMR_EMU_DENY_IRQ_MASK_Msk 0x10UL 154 #define RAMC_PPU_IMR_LOCKED_IRQ_MASK_Pos 5UL 155 #define RAMC_PPU_IMR_LOCKED_IRQ_MASK_Msk 0x20UL 156 /* RAMC_PPU.AIMR */ 157 #define RAMC_PPU_AIMR_UNSPT_POLICY_IRQ_MASK_Pos 0UL 158 #define RAMC_PPU_AIMR_UNSPT_POLICY_IRQ_MASK_Msk 0x1UL 159 #define RAMC_PPU_AIMR_DYN_ACCEPT_IRQ_MASK_Pos 1UL 160 #define RAMC_PPU_AIMR_DYN_ACCEPT_IRQ_MASK_Msk 0x2UL 161 #define RAMC_PPU_AIMR_DYN_DENY_IRQ_MASK_Pos 2UL 162 #define RAMC_PPU_AIMR_DYN_DENY_IRQ_MASK_Msk 0x4UL 163 #define RAMC_PPU_AIMR_STA_POLICY_PWR_IRQ_MASK_Pos 3UL 164 #define RAMC_PPU_AIMR_STA_POLICY_PWR_IRQ_MASK_Msk 0x8UL 165 #define RAMC_PPU_AIMR_STA_POLICY_OP_IRQ_MASK_Pos 4UL 166 #define RAMC_PPU_AIMR_STA_POLICY_OP_IRQ_MASK_Msk 0x10UL 167 /* RAMC_PPU.ISR */ 168 #define RAMC_PPU_ISR_STA_POLICY_TRN_IRQ_Pos 0UL 169 #define RAMC_PPU_ISR_STA_POLICY_TRN_IRQ_Msk 0x1UL 170 #define RAMC_PPU_ISR_STA_ACCEPT_IRQ_Pos 1UL 171 #define RAMC_PPU_ISR_STA_ACCEPT_IRQ_Msk 0x2UL 172 #define RAMC_PPU_ISR_STA_DENY_IRQ_Pos 2UL 173 #define RAMC_PPU_ISR_STA_DENY_IRQ_Msk 0x4UL 174 #define RAMC_PPU_ISR_EMU_ACCEPT_IRQ_Pos 3UL 175 #define RAMC_PPU_ISR_EMU_ACCEPT_IRQ_Msk 0x8UL 176 #define RAMC_PPU_ISR_EMU_DENY_IRQ_Pos 4UL 177 #define RAMC_PPU_ISR_EMU_DENY_IRQ_Msk 0x10UL 178 #define RAMC_PPU_ISR_LOCKED_IRQ_Pos 5UL 179 #define RAMC_PPU_ISR_LOCKED_IRQ_Msk 0x20UL 180 #define RAMC_PPU_ISR_OTHER_IRQ_Pos 7UL 181 #define RAMC_PPU_ISR_OTHER_IRQ_Msk 0x80UL 182 #define RAMC_PPU_ISR_PWR_ACTIVE_EDGE_IRQ_Pos 8UL 183 #define RAMC_PPU_ISR_PWR_ACTIVE_EDGE_IRQ_Msk 0x7FF00UL 184 #define RAMC_PPU_ISR_OP_ACTIVE_EDGE_IRQ_Pos 24UL 185 #define RAMC_PPU_ISR_OP_ACTIVE_EDGE_IRQ_Msk 0xFF000000UL 186 /* RAMC_PPU.AISR */ 187 #define RAMC_PPU_AISR_UNSPT_POLICY_IRQ_Pos 0UL 188 #define RAMC_PPU_AISR_UNSPT_POLICY_IRQ_Msk 0x1UL 189 #define RAMC_PPU_AISR_DYN_ACCEPT_IRQ_Pos 1UL 190 #define RAMC_PPU_AISR_DYN_ACCEPT_IRQ_Msk 0x2UL 191 #define RAMC_PPU_AISR_DYN_DENY_IRQ_Pos 2UL 192 #define RAMC_PPU_AISR_DYN_DENY_IRQ_Msk 0x4UL 193 #define RAMC_PPU_AISR_STA_POLICY_PWR_IRQ_Pos 3UL 194 #define RAMC_PPU_AISR_STA_POLICY_PWR_IRQ_Msk 0x8UL 195 #define RAMC_PPU_AISR_STA_POLICY_OP_IRQ_Pos 4UL 196 #define RAMC_PPU_AISR_STA_POLICY_OP_IRQ_Msk 0x10UL 197 /* RAMC_PPU.IESR */ 198 #define RAMC_PPU_IESR_DEVACTIVE00_EDGE_Pos 0UL 199 #define RAMC_PPU_IESR_DEVACTIVE00_EDGE_Msk 0x3UL 200 #define RAMC_PPU_IESR_DEVACTIVE01_EDGE_Pos 2UL 201 #define RAMC_PPU_IESR_DEVACTIVE01_EDGE_Msk 0xCUL 202 #define RAMC_PPU_IESR_DEVACTIVE02_EDGE_Pos 4UL 203 #define RAMC_PPU_IESR_DEVACTIVE02_EDGE_Msk 0x30UL 204 #define RAMC_PPU_IESR_DEVACTIVE03_EDGE_Pos 6UL 205 #define RAMC_PPU_IESR_DEVACTIVE03_EDGE_Msk 0xC0UL 206 #define RAMC_PPU_IESR_DEVACTIVE04_EDGE_Pos 8UL 207 #define RAMC_PPU_IESR_DEVACTIVE04_EDGE_Msk 0x300UL 208 #define RAMC_PPU_IESR_DEVACTIVE05_EDGE_Pos 10UL 209 #define RAMC_PPU_IESR_DEVACTIVE05_EDGE_Msk 0xC00UL 210 #define RAMC_PPU_IESR_DEVACTIVE06_EDGE_Pos 12UL 211 #define RAMC_PPU_IESR_DEVACTIVE06_EDGE_Msk 0x3000UL 212 #define RAMC_PPU_IESR_DEVACTIVE07_EDGE_Pos 14UL 213 #define RAMC_PPU_IESR_DEVACTIVE07_EDGE_Msk 0xC000UL 214 #define RAMC_PPU_IESR_DEVACTIVE08_EDGE_Pos 16UL 215 #define RAMC_PPU_IESR_DEVACTIVE08_EDGE_Msk 0x30000UL 216 #define RAMC_PPU_IESR_DEVACTIVE09_EDGE_Pos 18UL 217 #define RAMC_PPU_IESR_DEVACTIVE09_EDGE_Msk 0xC0000UL 218 #define RAMC_PPU_IESR_DEVACTIVE10_EDGE_Pos 20UL 219 #define RAMC_PPU_IESR_DEVACTIVE10_EDGE_Msk 0x300000UL 220 /* RAMC_PPU.OPSR */ 221 #define RAMC_PPU_OPSR_DEVACTIVE16_EDGE_Pos 0UL 222 #define RAMC_PPU_OPSR_DEVACTIVE16_EDGE_Msk 0x3UL 223 #define RAMC_PPU_OPSR_DEVACTIVE17_EDGE_Pos 2UL 224 #define RAMC_PPU_OPSR_DEVACTIVE17_EDGE_Msk 0xCUL 225 #define RAMC_PPU_OPSR_DEVACTIVE18_EDGE_Pos 4UL 226 #define RAMC_PPU_OPSR_DEVACTIVE18_EDGE_Msk 0x30UL 227 #define RAMC_PPU_OPSR_DEVACTIVE19_EDGE_Pos 6UL 228 #define RAMC_PPU_OPSR_DEVACTIVE19_EDGE_Msk 0xC0UL 229 #define RAMC_PPU_OPSR_DEVACTIVE20_EDGE_Pos 8UL 230 #define RAMC_PPU_OPSR_DEVACTIVE20_EDGE_Msk 0x300UL 231 #define RAMC_PPU_OPSR_DEVACTIVE21_EDGE_Pos 10UL 232 #define RAMC_PPU_OPSR_DEVACTIVE21_EDGE_Msk 0xC00UL 233 #define RAMC_PPU_OPSR_DEVACTIVE22_EDGE_Pos 12UL 234 #define RAMC_PPU_OPSR_DEVACTIVE22_EDGE_Msk 0x3000UL 235 #define RAMC_PPU_OPSR_DEVACTIVE23_EDGE_Pos 14UL 236 #define RAMC_PPU_OPSR_DEVACTIVE23_EDGE_Msk 0xC000UL 237 /* RAMC_PPU.FUNRR */ 238 #define RAMC_PPU_FUNRR_FUNC_RET_RAM_CFG_Pos 0UL 239 #define RAMC_PPU_FUNRR_FUNC_RET_RAM_CFG_Msk 0xFFUL 240 /* RAMC_PPU.FULRR */ 241 #define RAMC_PPU_FULRR_FULL_RET_RAM_CFG_Pos 0UL 242 #define RAMC_PPU_FULRR_FULL_RET_RAM_CFG_Msk 0xFFUL 243 /* RAMC_PPU.MEMRR */ 244 #define RAMC_PPU_MEMRR_MEM_RET_RAM_CFG_Pos 0UL 245 #define RAMC_PPU_MEMRR_MEM_RET_RAM_CFG_Msk 0xFFUL 246 /* RAMC_PPU.EDTR0 */ 247 #define RAMC_PPU_EDTR0_OFF_DEL_Pos 0UL 248 #define RAMC_PPU_EDTR0_OFF_DEL_Msk 0xFFUL 249 #define RAMC_PPU_EDTR0_MEM_RET_DEL_Pos 8UL 250 #define RAMC_PPU_EDTR0_MEM_RET_DEL_Msk 0xFF00UL 251 #define RAMC_PPU_EDTR0_LOGIC_RET_DEL_Pos 16UL 252 #define RAMC_PPU_EDTR0_LOGIC_RET_DEL_Msk 0xFF0000UL 253 #define RAMC_PPU_EDTR0_FULL_RET_DEL_Pos 24UL 254 #define RAMC_PPU_EDTR0_FULL_RET_DEL_Msk 0xFF000000UL 255 /* RAMC_PPU.EDTR1 */ 256 #define RAMC_PPU_EDTR1_MEM_OFF_DEL_Pos 0UL 257 #define RAMC_PPU_EDTR1_MEM_OFF_DEL_Msk 0xFFUL 258 #define RAMC_PPU_EDTR1_FUNC_RET_DEL_Pos 8UL 259 #define RAMC_PPU_EDTR1_FUNC_RET_DEL_Msk 0xFF00UL 260 /* RAMC_PPU.DCDR0 */ 261 #define RAMC_PPU_DCDR0_CLKEN_RST_DLY_Pos 0UL 262 #define RAMC_PPU_DCDR0_CLKEN_RST_DLY_Msk 0xFFUL 263 #define RAMC_PPU_DCDR0_ISO_CLKEN_DLY_Pos 8UL 264 #define RAMC_PPU_DCDR0_ISO_CLKEN_DLY_Msk 0xFF00UL 265 #define RAMC_PPU_DCDR0_RST_HWSTAT_DLY_Pos 16UL 266 #define RAMC_PPU_DCDR0_RST_HWSTAT_DLY_Msk 0xFF0000UL 267 /* RAMC_PPU.DCDR1 */ 268 #define RAMC_PPU_DCDR1_ISO_RST_DLY_Pos 0UL 269 #define RAMC_PPU_DCDR1_ISO_RST_DLY_Msk 0xFFUL 270 #define RAMC_PPU_DCDR1_CLKEN_ISO_DLY_Pos 8UL 271 #define RAMC_PPU_DCDR1_CLKEN_ISO_DLY_Msk 0xFF00UL 272 /* RAMC_PPU.IDR0 */ 273 #define RAMC_PPU_IDR0_DEVCHAN_Pos 0UL 274 #define RAMC_PPU_IDR0_DEVCHAN_Msk 0xFUL 275 #define RAMC_PPU_IDR0_NUM_OPMODE_Pos 4UL 276 #define RAMC_PPU_IDR0_NUM_OPMODE_Msk 0xF0UL 277 #define RAMC_PPU_IDR0_STA_OFF_SPT_Pos 8UL 278 #define RAMC_PPU_IDR0_STA_OFF_SPT_Msk 0x100UL 279 #define RAMC_PPU_IDR0_STA_OFF_EMU_SPT_Pos 9UL 280 #define RAMC_PPU_IDR0_STA_OFF_EMU_SPT_Msk 0x200UL 281 #define RAMC_PPU_IDR0_STA_MEM_RET_SPT_Pos 10UL 282 #define RAMC_PPU_IDR0_STA_MEM_RET_SPT_Msk 0x400UL 283 #define RAMC_PPU_IDR0_STA_MEM_RET_EMU_SPT_Pos 11UL 284 #define RAMC_PPU_IDR0_STA_MEM_RET_EMU_SPT_Msk 0x800UL 285 #define RAMC_PPU_IDR0_STA_LGC_RET_SPT_Pos 12UL 286 #define RAMC_PPU_IDR0_STA_LGC_RET_SPT_Msk 0x1000UL 287 #define RAMC_PPU_IDR0_STA_MEM_OFF_SPT_Pos 13UL 288 #define RAMC_PPU_IDR0_STA_MEM_OFF_SPT_Msk 0x2000UL 289 #define RAMC_PPU_IDR0_STA_FULL_RET_SPT_Pos 14UL 290 #define RAMC_PPU_IDR0_STA_FULL_RET_SPT_Msk 0x4000UL 291 #define RAMC_PPU_IDR0_STA_FUNC_RET_SPT_Pos 15UL 292 #define RAMC_PPU_IDR0_STA_FUNC_RET_SPT_Msk 0x8000UL 293 #define RAMC_PPU_IDR0_STA_ON_SPT_Pos 16UL 294 #define RAMC_PPU_IDR0_STA_ON_SPT_Msk 0x10000UL 295 #define RAMC_PPU_IDR0_STA_WRM_RST_SPT_Pos 17UL 296 #define RAMC_PPU_IDR0_STA_WRM_RST_SPT_Msk 0x20000UL 297 #define RAMC_PPU_IDR0_STA_DBG_RECOV_SPT_Pos 18UL 298 #define RAMC_PPU_IDR0_STA_DBG_RECOV_SPT_Msk 0x40000UL 299 #define RAMC_PPU_IDR0_DYN_OFF_SPT_Pos 20UL 300 #define RAMC_PPU_IDR0_DYN_OFF_SPT_Msk 0x100000UL 301 #define RAMC_PPU_IDR0_DYN_OFF_EMU_SPT_Pos 21UL 302 #define RAMC_PPU_IDR0_DYN_OFF_EMU_SPT_Msk 0x200000UL 303 #define RAMC_PPU_IDR0_DYN_MEM_RET_SPT_Pos 22UL 304 #define RAMC_PPU_IDR0_DYN_MEM_RET_SPT_Msk 0x400000UL 305 #define RAMC_PPU_IDR0_DYN_MEM_RET_EMU_SPT_Pos 23UL 306 #define RAMC_PPU_IDR0_DYN_MEM_RET_EMU_SPT_Msk 0x800000UL 307 #define RAMC_PPU_IDR0_DYN_LGC_RET_SPT_Pos 24UL 308 #define RAMC_PPU_IDR0_DYN_LGC_RET_SPT_Msk 0x1000000UL 309 #define RAMC_PPU_IDR0_DYN_MEM_OFF_SPT_Pos 25UL 310 #define RAMC_PPU_IDR0_DYN_MEM_OFF_SPT_Msk 0x2000000UL 311 #define RAMC_PPU_IDR0_DYN_FULL_RET_SPT_Pos 26UL 312 #define RAMC_PPU_IDR0_DYN_FULL_RET_SPT_Msk 0x4000000UL 313 #define RAMC_PPU_IDR0_DYN_FUNC_RET_SPT_Pos 27UL 314 #define RAMC_PPU_IDR0_DYN_FUNC_RET_SPT_Msk 0x8000000UL 315 #define RAMC_PPU_IDR0_DYN_ON_SPT_Pos 28UL 316 #define RAMC_PPU_IDR0_DYN_ON_SPT_Msk 0x10000000UL 317 #define RAMC_PPU_IDR0_DYN_WRM_RST_SPT_Pos 29UL 318 #define RAMC_PPU_IDR0_DYN_WRM_RST_SPT_Msk 0x20000000UL 319 /* RAMC_PPU.IDR1 */ 320 #define RAMC_PPU_IDR1_PWR_MODE_ENTRY_DEL_SPT_Pos 0UL 321 #define RAMC_PPU_IDR1_PWR_MODE_ENTRY_DEL_SPT_Msk 0x1UL 322 #define RAMC_PPU_IDR1_SW_DEV_DEL_SPT_Pos 1UL 323 #define RAMC_PPU_IDR1_SW_DEV_DEL_SPT_Msk 0x2UL 324 #define RAMC_PPU_IDR1_LOCK_SPT_Pos 2UL 325 #define RAMC_PPU_IDR1_LOCK_SPT_Msk 0x4UL 326 #define RAMC_PPU_IDR1_MEM_RET_RAM_REG_Pos 4UL 327 #define RAMC_PPU_IDR1_MEM_RET_RAM_REG_Msk 0x10UL 328 #define RAMC_PPU_IDR1_FULL_RET_RAM_REG_Pos 5UL 329 #define RAMC_PPU_IDR1_FULL_RET_RAM_REG_Msk 0x20UL 330 #define RAMC_PPU_IDR1_FUNC_RET_RAM_REG_Pos 6UL 331 #define RAMC_PPU_IDR1_FUNC_RET_RAM_REG_Msk 0x40UL 332 #define RAMC_PPU_IDR1_STA_POLICY_PWR_IRQ_SPT_Pos 8UL 333 #define RAMC_PPU_IDR1_STA_POLICY_PWR_IRQ_SPT_Msk 0x100UL 334 #define RAMC_PPU_IDR1_STA_POLICY_OP_IRQ_SPT_Pos 9UL 335 #define RAMC_PPU_IDR1_STA_POLICY_OP_IRQ_SPT_Msk 0x200UL 336 #define RAMC_PPU_IDR1_OP_ACTIVE_Pos 10UL 337 #define RAMC_PPU_IDR1_OP_ACTIVE_Msk 0x400UL 338 #define RAMC_PPU_IDR1_OFF_MEM_RET_TRANS_Pos 12UL 339 #define RAMC_PPU_IDR1_OFF_MEM_RET_TRANS_Msk 0x1000UL 340 /* RAMC_PPU.IIDR */ 341 #define RAMC_PPU_IIDR_IMPLEMENTER_Pos 0UL 342 #define RAMC_PPU_IIDR_IMPLEMENTER_Msk 0xFFFUL 343 #define RAMC_PPU_IIDR_REVISION_Pos 12UL 344 #define RAMC_PPU_IIDR_REVISION_Msk 0xF000UL 345 #define RAMC_PPU_IIDR_VARIANT_Pos 16UL 346 #define RAMC_PPU_IIDR_VARIANT_Msk 0xF0000UL 347 #define RAMC_PPU_IIDR_PRODUCT_ID_Pos 20UL 348 #define RAMC_PPU_IIDR_PRODUCT_ID_Msk 0xFFF00000UL 349 /* RAMC_PPU.AIDR */ 350 #define RAMC_PPU_AIDR_ARCH_REV_MINOR_Pos 0UL 351 #define RAMC_PPU_AIDR_ARCH_REV_MINOR_Msk 0xFUL 352 #define RAMC_PPU_AIDR_ARCH_REV_MAJOR_Pos 4UL 353 #define RAMC_PPU_AIDR_ARCH_REV_MAJOR_Msk 0xF0UL 354 /* RAMC_PPU.PID4 */ 355 #define RAMC_PPU_PID4_IMPLEMENTER_11_8_Pos 0UL 356 #define RAMC_PPU_PID4_IMPLEMENTER_11_8_Msk 0xFUL 357 /* RAMC_PPU.PID0 */ 358 #define RAMC_PPU_PID0_PRODUCT_ID_7_0_Pos 0UL 359 #define RAMC_PPU_PID0_PRODUCT_ID_7_0_Msk 0xFFUL 360 /* RAMC_PPU.PID1 */ 361 #define RAMC_PPU_PID1_PRODUCT_ID_11_8_Pos 0UL 362 #define RAMC_PPU_PID1_PRODUCT_ID_11_8_Msk 0xFUL 363 #define RAMC_PPU_PID1_IMPLEMENTER_3_0_Pos 4UL 364 #define RAMC_PPU_PID1_IMPLEMENTER_3_0_Msk 0xF0UL 365 /* RAMC_PPU.PID2 */ 366 #define RAMC_PPU_PID2_IMPLEMENTER_6_4_Pos 0UL 367 #define RAMC_PPU_PID2_IMPLEMENTER_6_4_Msk 0x7UL 368 #define RAMC_PPU_PID2_CONST_HIGH_Pos 3UL 369 #define RAMC_PPU_PID2_CONST_HIGH_Msk 0x8UL 370 #define RAMC_PPU_PID2_REV_CONST_Pos 4UL 371 #define RAMC_PPU_PID2_REV_CONST_Msk 0xF0UL 372 /* RAMC_PPU.PID3 */ 373 #define RAMC_PPU_PID3_PID3_REV_CONST_Pos 0UL 374 #define RAMC_PPU_PID3_PID3_REV_CONST_Msk 0xFUL 375 #define RAMC_PPU_PID3_PID3_REVISION_Pos 4UL 376 #define RAMC_PPU_PID3_PID3_REVISION_Msk 0xF0UL 377 /* RAMC_PPU.ID0 */ 378 #define RAMC_PPU_ID0_ID0_Pos 0UL 379 #define RAMC_PPU_ID0_ID0_Msk 0xFFUL 380 /* RAMC_PPU.ID1 */ 381 #define RAMC_PPU_ID1_ID1_Pos 0UL 382 #define RAMC_PPU_ID1_ID1_Msk 0xFFUL 383 /* RAMC_PPU.ID2 */ 384 #define RAMC_PPU_ID2_ID2_Pos 0UL 385 #define RAMC_PPU_ID2_ID2_Msk 0xFFUL 386 /* RAMC_PPU.ID3 */ 387 #define RAMC_PPU_ID3_ID3_Pos 0UL 388 #define RAMC_PPU_ID3_ID3_Msk 0xFFUL 389 390 391 #endif /* _CYIP_RAMC_PPU_H_ */ 392 393 394 /* [] END OF FILE */ 395
