1 /***************************************************************************//** 2 * \file cyip_pwrmode.h 3 * 4 * \brief 5 * PWRMODE IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PWRMODE_H_ 28 #define _CYIP_PWRMODE_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PWRMODE 34 *******************************************************************************/ 35 36 #define PWRMODE_PD_SECTION_SIZE 0x00000010UL 37 #define PWRMODE_PPU_MAIN_PPU_MAIN_SECTION_SIZE 0x00001000UL 38 #define PWRMODE_PPU_MAIN_SECTION_SIZE 0x00001000UL 39 #define PWRMODE_SECTION_SIZE 0x00010000UL 40 41 /** 42 * \brief Power Domain Dependency Sense Register (PWRMODE_PD) 43 */ 44 typedef struct { 45 __IOM uint32_t PD_SENSE; /*!< 0x00000000 Dependency Sense Register */ 46 __IM uint32_t PD_SPT; /*!< 0x00000004 Dependency Support Register */ 47 __IM uint32_t RESERVED[2]; 48 } PWRMODE_PD_Type; /*!< Size = 16 (0x10) */ 49 50 /** 51 * \brief Power Policy Unit Registers for the main power domain (VCCACT_PD) (PWRMODE_PPU_MAIN_PPU_MAIN) 52 */ 53 typedef struct { 54 __IOM uint32_t PWPR; /*!< 0x00000000 Power Policy Register */ 55 __IOM uint32_t PMER; /*!< 0x00000004 Power Mode Emulation Register */ 56 __IM uint32_t PWSR; /*!< 0x00000008 Power Status Register */ 57 __IM uint32_t RESERVED; 58 __IM uint32_t DISR; /*!< 0x00000010 Device Interface Input Current Status Register */ 59 __IM uint32_t MISR; /*!< 0x00000014 Miscellaneous Input Current Status Register */ 60 __IM uint32_t STSR; /*!< 0x00000018 Stored Status Register */ 61 __IOM uint32_t UNLK; /*!< 0x0000001C Unlock register */ 62 __IOM uint32_t PWCR; /*!< 0x00000020 Power Configuration Register */ 63 __IOM uint32_t PTCR; /*!< 0x00000024 Power Mode Transition Configuration Register */ 64 __IM uint32_t RESERVED1[2]; 65 __IOM uint32_t IMR; /*!< 0x00000030 Interrupt Mask Register */ 66 __IOM uint32_t AIMR; /*!< 0x00000034 Additional Interrupt Mask Register */ 67 __IOM uint32_t ISR; /*!< 0x00000038 Interrupt Status Register */ 68 __IOM uint32_t AISR; /*!< 0x0000003C Additional Interrupt Status Register */ 69 __IOM uint32_t IESR; /*!< 0x00000040 Input Edge Sensitivity Register */ 70 __IOM uint32_t OPSR; /*!< 0x00000044 Operating Mode Active Edge Sensitivity Register */ 71 __IM uint32_t RESERVED2[2]; 72 __IOM uint32_t FUNRR; /*!< 0x00000050 Functional Retention RAM Configuration Register */ 73 __IOM uint32_t FULRR; /*!< 0x00000054 Full Retention RAM Configuration Register */ 74 __IOM uint32_t MEMRR; /*!< 0x00000058 Memory Retention RAM Configuration Register */ 75 __IM uint32_t RESERVED3[65]; 76 __IOM uint32_t EDTR0; /*!< 0x00000160 Power Mode Entry Delay Register 0 */ 77 __IOM uint32_t EDTR1; /*!< 0x00000164 Power Mode Entry Delay Register 1 */ 78 __IM uint32_t RESERVED4[2]; 79 __IM uint32_t DCDR0; /*!< 0x00000170 Device Control Delay Configuration Register 0 */ 80 __IM uint32_t DCDR1; /*!< 0x00000174 Device Control Delay Configuration Register 1 */ 81 __IM uint32_t RESERVED5[910]; 82 __IM uint32_t IDR0; /*!< 0x00000FB0 PPU Identification Register 0 */ 83 __IM uint32_t IDR1; /*!< 0x00000FB4 PPU Identification Register 1 */ 84 __IM uint32_t RESERVED6[4]; 85 __IM uint32_t IIDR; /*!< 0x00000FC8 Implementation Identification Register */ 86 __IM uint32_t AIDR; /*!< 0x00000FCC Architecture Identification Register */ 87 __IM uint32_t RESERVED7[12]; 88 } PWRMODE_PPU_MAIN_PPU_MAIN_Type; /*!< Size = 4096 (0x1000) */ 89 90 /** 91 * \brief Power Policy Unit for Active Domain (PWRMODE_PPU_MAIN) 92 */ 93 typedef struct { 94 PWRMODE_PPU_MAIN_PPU_MAIN_Type PPU_MAIN; /*!< 0x00000000 Power Policy Unit Registers for the main power domain 95 (VCCACT_PD) */ 96 } PWRMODE_PPU_MAIN_Type; /*!< Size = 4096 (0x1000) */ 97 98 /** 99 * \brief SRSS Power Mode Control Registers (PWRMODE) 100 */ 101 typedef struct { 102 PWRMODE_PD_Type PD[16]; /*!< 0x00000000 Power Domain Dependency Sense Register */ 103 __IM uint32_t RESERVED[960]; 104 PWRMODE_PPU_MAIN_Type PPU_MAIN; /*!< 0x00001000 Power Policy Unit for Active Domain */ 105 __IOM uint32_t CLK_SELECT; /*!< 0x00002000 Clock Selection for Power Mode Components */ 106 } PWRMODE_Type; /*!< Size = 8196 (0x2004) */ 107 108 109 /* PWRMODE_PD.PD_SENSE */ 110 #define PWRMODE_PD_PD_SENSE_PD_ON_Pos 0UL 111 #define PWRMODE_PD_PD_SENSE_PD_ON_Msk 0xFFFFUL 112 /* PWRMODE_PD.PD_SPT */ 113 #define PWRMODE_PD_PD_SPT_PD_FORCE_ON_Pos 0UL 114 #define PWRMODE_PD_PD_SPT_PD_FORCE_ON_Msk 0xFFFFUL 115 #define PWRMODE_PD_PD_SPT_PD_CONFIG_ON_Pos 16UL 116 #define PWRMODE_PD_PD_SPT_PD_CONFIG_ON_Msk 0xFFFF0000UL 117 118 119 /* PWRMODE_PPU_MAIN_PPU_MAIN.PWPR */ 120 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_PWR_POLICY_Pos 0UL 121 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_PWR_POLICY_Msk 0xFUL 122 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_PWR_DYN_EN_Pos 8UL 123 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_PWR_DYN_EN_Msk 0x100UL 124 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_LOCK_EN_Pos 12UL 125 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_LOCK_EN_Msk 0x1000UL 126 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_OP_POLICY_Pos 16UL 127 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_OP_POLICY_Msk 0xF0000UL 128 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_OP_DYN_EN_Pos 24UL 129 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWPR_OP_DYN_EN_Msk 0x1000000UL 130 /* PWRMODE_PPU_MAIN_PPU_MAIN.PMER */ 131 #define PWRMODE_PPU_MAIN_PPU_MAIN_PMER_EMU_EN_Pos 0UL 132 #define PWRMODE_PPU_MAIN_PPU_MAIN_PMER_EMU_EN_Msk 0x1UL 133 /* PWRMODE_PPU_MAIN_PPU_MAIN.PWSR */ 134 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_PWR_STATUS_Pos 0UL 135 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_PWR_STATUS_Msk 0xFUL 136 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_PWR_DYN_STATUS_Pos 8UL 137 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_PWR_DYN_STATUS_Msk 0x100UL 138 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_LOCK_STATUS_Pos 12UL 139 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_LOCK_STATUS_Msk 0x1000UL 140 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_OP_STATUS_Pos 16UL 141 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_OP_STATUS_Msk 0xF0000UL 142 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_OP_DYN_STATUS_Pos 24UL 143 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWSR_OP_DYN_STATUS_Msk 0x1000000UL 144 /* PWRMODE_PPU_MAIN_PPU_MAIN.DISR */ 145 #define PWRMODE_PPU_MAIN_PPU_MAIN_DISR_PWR_DEVACTIVE_STATUS_Pos 0UL 146 #define PWRMODE_PPU_MAIN_PPU_MAIN_DISR_PWR_DEVACTIVE_STATUS_Msk 0x7FFUL 147 #define PWRMODE_PPU_MAIN_PPU_MAIN_DISR_OP_DEVACTIVE_STATUS_Pos 24UL 148 #define PWRMODE_PPU_MAIN_PPU_MAIN_DISR_OP_DEVACTIVE_STATUS_Msk 0xFF000000UL 149 /* PWRMODE_PPU_MAIN_PPU_MAIN.MISR */ 150 #define PWRMODE_PPU_MAIN_PPU_MAIN_MISR_PCSMPACCEPT_STATUS_Pos 0UL 151 #define PWRMODE_PPU_MAIN_PPU_MAIN_MISR_PCSMPACCEPT_STATUS_Msk 0x1UL 152 #define PWRMODE_PPU_MAIN_PPU_MAIN_MISR_DEVACCEPT_STATUS_Pos 8UL 153 #define PWRMODE_PPU_MAIN_PPU_MAIN_MISR_DEVACCEPT_STATUS_Msk 0xFF00UL 154 #define PWRMODE_PPU_MAIN_PPU_MAIN_MISR_DEVDENY_STATUS_Pos 16UL 155 #define PWRMODE_PPU_MAIN_PPU_MAIN_MISR_DEVDENY_STATUS_Msk 0xFF0000UL 156 /* PWRMODE_PPU_MAIN_PPU_MAIN.STSR */ 157 #define PWRMODE_PPU_MAIN_PPU_MAIN_STSR_STORED_DEVDENY_Pos 0UL 158 #define PWRMODE_PPU_MAIN_PPU_MAIN_STSR_STORED_DEVDENY_Msk 0xFFUL 159 /* PWRMODE_PPU_MAIN_PPU_MAIN.UNLK */ 160 #define PWRMODE_PPU_MAIN_PPU_MAIN_UNLK_UNLOCK_Pos 0UL 161 #define PWRMODE_PPU_MAIN_PPU_MAIN_UNLK_UNLOCK_Msk 0x1UL 162 /* PWRMODE_PPU_MAIN_PPU_MAIN.PWCR */ 163 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWCR_DEVREQEN_Pos 0UL 164 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWCR_DEVREQEN_Msk 0xFFUL 165 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWCR_PWR_DEVACTIVEEN_Pos 8UL 166 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWCR_PWR_DEVACTIVEEN_Msk 0x7FF00UL 167 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWCR_OP_DEVACTIVEEN_Pos 24UL 168 #define PWRMODE_PPU_MAIN_PPU_MAIN_PWCR_OP_DEVACTIVEEN_Msk 0xFF000000UL 169 /* PWRMODE_PPU_MAIN_PPU_MAIN.PTCR */ 170 #define PWRMODE_PPU_MAIN_PPU_MAIN_PTCR_WARM_RST_DEVREQEN_Pos 0UL 171 #define PWRMODE_PPU_MAIN_PPU_MAIN_PTCR_WARM_RST_DEVREQEN_Msk 0x1UL 172 #define PWRMODE_PPU_MAIN_PPU_MAIN_PTCR_DBG_RECOV_PORST_EN_Pos 1UL 173 #define PWRMODE_PPU_MAIN_PPU_MAIN_PTCR_DBG_RECOV_PORST_EN_Msk 0x2UL 174 /* PWRMODE_PPU_MAIN_PPU_MAIN.IMR */ 175 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_STA_POLICY_TRN_IRQ_MASK_Pos 0UL 176 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_STA_POLICY_TRN_IRQ_MASK_Msk 0x1UL 177 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_STA_ACCEPT_IRQ_MASK_Pos 1UL 178 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_STA_ACCEPT_IRQ_MASK_Msk 0x2UL 179 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_STA_DENY_IRQ_MASK_Pos 2UL 180 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_STA_DENY_IRQ_MASK_Msk 0x4UL 181 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_EMU_ACCEPT_IRQ_MASK_Pos 3UL 182 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_EMU_ACCEPT_IRQ_MASK_Msk 0x8UL 183 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_EMU_DENY_IRQ_MASK_Pos 4UL 184 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_EMU_DENY_IRQ_MASK_Msk 0x10UL 185 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_LOCKED_IRQ_MASK_Pos 5UL 186 #define PWRMODE_PPU_MAIN_PPU_MAIN_IMR_LOCKED_IRQ_MASK_Msk 0x20UL 187 /* PWRMODE_PPU_MAIN_PPU_MAIN.AIMR */ 188 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_UNSPT_POLICY_IRQ_MASK_Pos 0UL 189 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_UNSPT_POLICY_IRQ_MASK_Msk 0x1UL 190 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_DYN_ACCEPT_IRQ_MASK_Pos 1UL 191 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_DYN_ACCEPT_IRQ_MASK_Msk 0x2UL 192 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_DYN_DENY_IRQ_MASK_Pos 2UL 193 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_DYN_DENY_IRQ_MASK_Msk 0x4UL 194 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_STA_POLICY_PWR_IRQ_MASK_Pos 3UL 195 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_STA_POLICY_PWR_IRQ_MASK_Msk 0x8UL 196 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_STA_POLICY_OP_IRQ_MASK_Pos 4UL 197 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIMR_STA_POLICY_OP_IRQ_MASK_Msk 0x10UL 198 /* PWRMODE_PPU_MAIN_PPU_MAIN.ISR */ 199 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_STA_POLICY_TRN_IRQ_Pos 0UL 200 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_STA_POLICY_TRN_IRQ_Msk 0x1UL 201 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_STA_ACCEPT_IRQ_Pos 1UL 202 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_STA_ACCEPT_IRQ_Msk 0x2UL 203 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_STA_DENY_IRQ_Pos 2UL 204 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_STA_DENY_IRQ_Msk 0x4UL 205 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_EMU_ACCEPT_IRQ_Pos 3UL 206 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_EMU_ACCEPT_IRQ_Msk 0x8UL 207 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_EMU_DENY_IRQ_Pos 4UL 208 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_EMU_DENY_IRQ_Msk 0x10UL 209 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_LOCKED_IRQ_Pos 5UL 210 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_LOCKED_IRQ_Msk 0x20UL 211 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_OTHER_IRQ_Pos 7UL 212 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_OTHER_IRQ_Msk 0x80UL 213 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_PWR_ACTIVE_EDGE_IRQ_Pos 8UL 214 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_PWR_ACTIVE_EDGE_IRQ_Msk 0x7FF00UL 215 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_OP_ACTIVE_EDGE_IRQ_Pos 24UL 216 #define PWRMODE_PPU_MAIN_PPU_MAIN_ISR_OP_ACTIVE_EDGE_IRQ_Msk 0xFF000000UL 217 /* PWRMODE_PPU_MAIN_PPU_MAIN.AISR */ 218 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_UNSPT_POLICY_IRQ_Pos 0UL 219 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_UNSPT_POLICY_IRQ_Msk 0x1UL 220 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_DYN_ACCEPT_IRQ_Pos 1UL 221 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_DYN_ACCEPT_IRQ_Msk 0x2UL 222 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_DYN_DENY_IRQ_Pos 2UL 223 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_DYN_DENY_IRQ_Msk 0x4UL 224 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_STA_POLICY_PWR_IRQ_Pos 3UL 225 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_STA_POLICY_PWR_IRQ_Msk 0x8UL 226 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_STA_POLICY_OP_IRQ_Pos 4UL 227 #define PWRMODE_PPU_MAIN_PPU_MAIN_AISR_STA_POLICY_OP_IRQ_Msk 0x10UL 228 /* PWRMODE_PPU_MAIN_PPU_MAIN.IESR */ 229 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE00_EDGE_Pos 0UL 230 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE00_EDGE_Msk 0x3UL 231 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE01_EDGE_Pos 2UL 232 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE01_EDGE_Msk 0xCUL 233 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE02_EDGE_Pos 4UL 234 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE02_EDGE_Msk 0x30UL 235 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE03_EDGE_Pos 6UL 236 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE03_EDGE_Msk 0xC0UL 237 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE04_EDGE_Pos 8UL 238 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE04_EDGE_Msk 0x300UL 239 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE05_EDGE_Pos 10UL 240 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE05_EDGE_Msk 0xC00UL 241 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE06_EDGE_Pos 12UL 242 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE06_EDGE_Msk 0x3000UL 243 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE07_EDGE_Pos 14UL 244 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE07_EDGE_Msk 0xC000UL 245 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE08_EDGE_Pos 16UL 246 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE08_EDGE_Msk 0x30000UL 247 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE09_EDGE_Pos 18UL 248 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE09_EDGE_Msk 0xC0000UL 249 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE10_EDGE_Pos 20UL 250 #define PWRMODE_PPU_MAIN_PPU_MAIN_IESR_DEVACTIVE10_EDGE_Msk 0x300000UL 251 /* PWRMODE_PPU_MAIN_PPU_MAIN.OPSR */ 252 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE16_EDGE_Pos 0UL 253 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE16_EDGE_Msk 0x3UL 254 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE17_EDGE_Pos 2UL 255 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE17_EDGE_Msk 0xCUL 256 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE18_EDGE_Pos 4UL 257 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE18_EDGE_Msk 0x30UL 258 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE19_EDGE_Pos 6UL 259 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE19_EDGE_Msk 0xC0UL 260 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE20_EDGE_Pos 8UL 261 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE20_EDGE_Msk 0x300UL 262 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE21_EDGE_Pos 10UL 263 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE21_EDGE_Msk 0xC00UL 264 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE22_EDGE_Pos 12UL 265 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE22_EDGE_Msk 0x3000UL 266 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE23_EDGE_Pos 14UL 267 #define PWRMODE_PPU_MAIN_PPU_MAIN_OPSR_DEVACTIVE23_EDGE_Msk 0xC000UL 268 /* PWRMODE_PPU_MAIN_PPU_MAIN.FUNRR */ 269 #define PWRMODE_PPU_MAIN_PPU_MAIN_FUNRR_FUNC_RET_RAM_CFG_Pos 0UL 270 #define PWRMODE_PPU_MAIN_PPU_MAIN_FUNRR_FUNC_RET_RAM_CFG_Msk 0xFFUL 271 /* PWRMODE_PPU_MAIN_PPU_MAIN.FULRR */ 272 #define PWRMODE_PPU_MAIN_PPU_MAIN_FULRR_FULL_RET_RAM_CFG_Pos 0UL 273 #define PWRMODE_PPU_MAIN_PPU_MAIN_FULRR_FULL_RET_RAM_CFG_Msk 0xFFUL 274 /* PWRMODE_PPU_MAIN_PPU_MAIN.MEMRR */ 275 #define PWRMODE_PPU_MAIN_PPU_MAIN_MEMRR_MEM_RET_RAM_CFG_Pos 0UL 276 #define PWRMODE_PPU_MAIN_PPU_MAIN_MEMRR_MEM_RET_RAM_CFG_Msk 0xFFUL 277 /* PWRMODE_PPU_MAIN_PPU_MAIN.EDTR0 */ 278 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR0_OFF_DEL_Pos 0UL 279 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR0_OFF_DEL_Msk 0xFFUL 280 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR0_MEM_RET_DEL_Pos 8UL 281 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR0_MEM_RET_DEL_Msk 0xFF00UL 282 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR0_LOGIC_RET_DEL_Pos 16UL 283 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR0_LOGIC_RET_DEL_Msk 0xFF0000UL 284 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR0_FULL_RET_DEL_Pos 24UL 285 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR0_FULL_RET_DEL_Msk 0xFF000000UL 286 /* PWRMODE_PPU_MAIN_PPU_MAIN.EDTR1 */ 287 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR1_MEM_OFF_DEL_Pos 0UL 288 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR1_MEM_OFF_DEL_Msk 0xFFUL 289 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR1_FUNC_RET_DEL_Pos 8UL 290 #define PWRMODE_PPU_MAIN_PPU_MAIN_EDTR1_FUNC_RET_DEL_Msk 0xFF00UL 291 /* PWRMODE_PPU_MAIN_PPU_MAIN.DCDR0 */ 292 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR0_CLKEN_RST_DLY_Pos 0UL 293 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR0_CLKEN_RST_DLY_Msk 0xFFUL 294 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR0_ISO_CLKEN_DLY_Pos 8UL 295 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR0_ISO_CLKEN_DLY_Msk 0xFF00UL 296 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR0_RST_HWSTAT_DLY_Pos 16UL 297 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR0_RST_HWSTAT_DLY_Msk 0xFF0000UL 298 /* PWRMODE_PPU_MAIN_PPU_MAIN.DCDR1 */ 299 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR1_ISO_RST_DLY_Pos 0UL 300 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR1_ISO_RST_DLY_Msk 0xFFUL 301 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR1_CLKEN_ISO_DLY_Pos 8UL 302 #define PWRMODE_PPU_MAIN_PPU_MAIN_DCDR1_CLKEN_ISO_DLY_Msk 0xFF00UL 303 /* PWRMODE_PPU_MAIN_PPU_MAIN.IDR0 */ 304 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DEVCHAN_Pos 0UL 305 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DEVCHAN_Msk 0xFUL 306 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_NUM_OPMODE_Pos 4UL 307 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_NUM_OPMODE_Msk 0xF0UL 308 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_OFF_SPT_Pos 8UL 309 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_OFF_SPT_Msk 0x100UL 310 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_OFF_EMU_SPT_Pos 9UL 311 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_OFF_EMU_SPT_Msk 0x200UL 312 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_MEM_RET_SPT_Pos 10UL 313 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_MEM_RET_SPT_Msk 0x400UL 314 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_MEM_RET_EMU_SPT_Pos 11UL 315 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_MEM_RET_EMU_SPT_Msk 0x800UL 316 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_LGC_RET_SPT_Pos 12UL 317 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_LGC_RET_SPT_Msk 0x1000UL 318 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_MEM_OFF_SPT_Pos 13UL 319 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_MEM_OFF_SPT_Msk 0x2000UL 320 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_FULL_RET_SPT_Pos 14UL 321 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_FULL_RET_SPT_Msk 0x4000UL 322 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_FUNC_RET_SPT_Pos 15UL 323 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_FUNC_RET_SPT_Msk 0x8000UL 324 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_ON_SPT_Pos 16UL 325 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_ON_SPT_Msk 0x10000UL 326 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_WRM_RST_SPT_Pos 17UL 327 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_WRM_RST_SPT_Msk 0x20000UL 328 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_DBG_RECOV_SPT_Pos 18UL 329 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_STA_DBG_RECOV_SPT_Msk 0x40000UL 330 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_OFF_SPT_Pos 20UL 331 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_OFF_SPT_Msk 0x100000UL 332 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_OFF_EMU_SPT_Pos 21UL 333 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_OFF_EMU_SPT_Msk 0x200000UL 334 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_MEM_RET_SPT_Pos 22UL 335 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_MEM_RET_SPT_Msk 0x400000UL 336 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_MEM_RET_EMU_SPT_Pos 23UL 337 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_MEM_RET_EMU_SPT_Msk 0x800000UL 338 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_LGC_RET_SPT_Pos 24UL 339 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_LGC_RET_SPT_Msk 0x1000000UL 340 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_MEM_OFF_SPT_Pos 25UL 341 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_MEM_OFF_SPT_Msk 0x2000000UL 342 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_FULL_RET_SPT_Pos 26UL 343 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_FULL_RET_SPT_Msk 0x4000000UL 344 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_FUNC_RET_SPT_Pos 27UL 345 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_FUNC_RET_SPT_Msk 0x8000000UL 346 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_ON_SPT_Pos 28UL 347 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_ON_SPT_Msk 0x10000000UL 348 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_WRM_RST_SPT_Pos 29UL 349 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR0_DYN_WRM_RST_SPT_Msk 0x20000000UL 350 /* PWRMODE_PPU_MAIN_PPU_MAIN.IDR1 */ 351 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_PWR_MODE_ENTRY_DEL_SPT_Pos 0UL 352 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_PWR_MODE_ENTRY_DEL_SPT_Msk 0x1UL 353 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_SW_DEV_DEL_SPT_Pos 1UL 354 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_SW_DEV_DEL_SPT_Msk 0x2UL 355 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_LOCK_SPT_Pos 2UL 356 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_LOCK_SPT_Msk 0x4UL 357 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_MEM_RET_RAM_REG_Pos 4UL 358 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_MEM_RET_RAM_REG_Msk 0x10UL 359 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_FULL_RET_RAM_REG_Pos 5UL 360 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_FULL_RET_RAM_REG_Msk 0x20UL 361 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_FUNC_RET_RAM_REG_Pos 6UL 362 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_FUNC_RET_RAM_REG_Msk 0x40UL 363 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_STA_POLICY_PWR_IRQ_SPT_Pos 8UL 364 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_STA_POLICY_PWR_IRQ_SPT_Msk 0x100UL 365 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_STA_POLICY_OP_IRQ_SPT_Pos 9UL 366 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_STA_POLICY_OP_IRQ_SPT_Msk 0x200UL 367 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_OP_ACTIVE_Pos 10UL 368 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_OP_ACTIVE_Msk 0x400UL 369 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_OFF_MEM_RET_TRANS_Pos 12UL 370 #define PWRMODE_PPU_MAIN_PPU_MAIN_IDR1_OFF_MEM_RET_TRANS_Msk 0x1000UL 371 /* PWRMODE_PPU_MAIN_PPU_MAIN.IIDR */ 372 #define PWRMODE_PPU_MAIN_PPU_MAIN_IIDR_IMPLEMENTER_Pos 0UL 373 #define PWRMODE_PPU_MAIN_PPU_MAIN_IIDR_IMPLEMENTER_Msk 0xFFFUL 374 #define PWRMODE_PPU_MAIN_PPU_MAIN_IIDR_REVISION_Pos 12UL 375 #define PWRMODE_PPU_MAIN_PPU_MAIN_IIDR_REVISION_Msk 0xF000UL 376 #define PWRMODE_PPU_MAIN_PPU_MAIN_IIDR_VARIANT_Pos 16UL 377 #define PWRMODE_PPU_MAIN_PPU_MAIN_IIDR_VARIANT_Msk 0xF0000UL 378 #define PWRMODE_PPU_MAIN_PPU_MAIN_IIDR_PRODUCT_ID_Pos 20UL 379 #define PWRMODE_PPU_MAIN_PPU_MAIN_IIDR_PRODUCT_ID_Msk 0xFFF00000UL 380 /* PWRMODE_PPU_MAIN_PPU_MAIN.AIDR */ 381 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIDR_ARCH_REV_MINOR_Pos 0UL 382 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIDR_ARCH_REV_MINOR_Msk 0xFUL 383 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIDR_ARCH_REV_MAJOR_Pos 4UL 384 #define PWRMODE_PPU_MAIN_PPU_MAIN_AIDR_ARCH_REV_MAJOR_Msk 0xF0UL 385 386 387 /* PWRMODE.CLK_SELECT */ 388 #define PWRMODE_CLK_SELECT_CLK_PWR_DIV_Pos 0UL 389 #define PWRMODE_CLK_SELECT_CLK_PWR_DIV_Msk 0xFFUL 390 #define PWRMODE_CLK_SELECT_CLK_PWR_MUX_Pos 16UL 391 #define PWRMODE_CLK_SELECT_CLK_PWR_MUX_Msk 0x30000UL 392 393 394 #endif /* _CYIP_PWRMODE_H_ */ 395 396 397 /* [] END OF FILE */ 398
