1 /***************************************************************************//** 2 * \file cyip_pwm.h 3 * 4 * \brief 5 * PWM IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PWM_H_ 28 #define _CYIP_PWM_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PWM 34 *******************************************************************************/ 35 36 #define PWM_TX_SECTION_SIZE 0x00000100UL 37 #define PWM_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief PWM structure (PWM_TX) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 44 __IM uint32_t RESERVED[3]; 45 __IOM uint32_t IF_CTL; /*!< 0x00000010 Interface control */ 46 __IOM uint32_t DOUBLE_CTL; /*!< 0x00000014 Double control */ 47 __IOM uint32_t GAIN_CTL; /*!< 0x00000018 Gain control */ 48 __IM uint32_t RESERVED1; 49 __IOM uint32_t PWM_CTL0; /*!< 0x00000020 PWM control 0 */ 50 __IOM uint32_t PWM_CTL1; /*!< 0x00000024 PWM control 1 */ 51 __IOM uint32_t PWM_CTL2; /*!< 0x00000028 PWM control 2 */ 52 __IOM uint32_t PWM_CTL3; /*!< 0x0000002C PWM control 3 */ 53 __IM uint32_t RESERVED2[20]; 54 __IOM uint32_t TX_FIFO_CTL; /*!< 0x00000080 TX FIFO control */ 55 __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000084 TX FIFO status */ 56 __OM uint32_t TX_FIFO_WR; /*!< 0x00000088 TX FIFO write */ 57 __IM uint32_t RESERVED3[13]; 58 __IOM uint32_t INTR_TX; /*!< 0x000000C0 Interrupt */ 59 __IOM uint32_t INTR_TX_SET; /*!< 0x000000C4 Interrupt set */ 60 __IOM uint32_t INTR_TX_MASK; /*!< 0x000000C8 Interrupt mask */ 61 __IM uint32_t INTR_TX_MASKED; /*!< 0x000000CC Interrupt masked */ 62 __IM uint32_t RESERVED4[12]; 63 } PWM_TX_Type; /*!< Size = 256 (0x100) */ 64 65 /** 66 * \brief PWM (PWM) 67 */ 68 typedef struct { 69 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 70 __IOM uint32_t CTL_CLR; /*!< 0x00000004 Control clear */ 71 __IOM uint32_t CTL_SET; /*!< 0x00000008 Control set */ 72 __IM uint32_t RESERVED[8189]; 73 PWM_TX_Type TX[8]; /*!< 0x00008000 PWM structure */ 74 } PWM_Type; /*!< Size = 34816 (0x8800) */ 75 76 77 /* PWM_TX.CTL */ 78 #define PWM_TX_CTL_WORD_SIZE_Pos 0UL 79 #define PWM_TX_CTL_WORD_SIZE_Msk 0xFUL 80 #define PWM_TX_CTL_ENABLED_Pos 31UL 81 #define PWM_TX_CTL_ENABLED_Msk 0x80000000UL 82 /* PWM_TX.IF_CTL */ 83 #define PWM_TX_IF_CTL_CLOCK_DIV_Pos 0UL 84 #define PWM_TX_IF_CTL_CLOCK_DIV_Msk 0xFFUL 85 #define PWM_TX_IF_CTL_CLOCK_SEL_Pos 8UL 86 #define PWM_TX_IF_CTL_CLOCK_SEL_Msk 0x700UL 87 #define PWM_TX_IF_CTL_LINE_POLARITY_Pos 12UL 88 #define PWM_TX_IF_CTL_LINE_POLARITY_Msk 0xF000UL 89 /* PWM_TX.DOUBLE_CTL */ 90 #define PWM_TX_DOUBLE_CTL_MODE_Pos 0UL 91 #define PWM_TX_DOUBLE_CTL_MODE_Msk 0x1UL 92 #define PWM_TX_DOUBLE_CTL_ENABLED_Pos 31UL 93 #define PWM_TX_DOUBLE_CTL_ENABLED_Msk 0x80000000UL 94 /* PWM_TX.GAIN_CTL */ 95 #define PWM_TX_GAIN_CTL_CODE_Pos 0UL 96 #define PWM_TX_GAIN_CTL_CODE_Msk 0x7FUL 97 /* PWM_TX.PWM_CTL0 */ 98 #define PWM_TX_PWM_CTL0_FORMAT_Pos 0UL 99 #define PWM_TX_PWM_CTL0_FORMAT_Msk 0x3UL 100 #define PWM_TX_PWM_CTL0_SCALE_Pos 16UL 101 #define PWM_TX_PWM_CTL0_SCALE_Msk 0xF0000UL 102 /* PWM_TX.PWM_CTL1 */ 103 #define PWM_TX_PWM_CTL1_MIN_Pos 0UL 104 #define PWM_TX_PWM_CTL1_MIN_Msk 0xFFFFUL 105 #define PWM_TX_PWM_CTL1_MAX_Pos 16UL 106 #define PWM_TX_PWM_CTL1_MAX_Msk 0xFFFF0000UL 107 /* PWM_TX.PWM_CTL2 */ 108 #define PWM_TX_PWM_CTL2_PERIOD_Pos 0UL 109 #define PWM_TX_PWM_CTL2_PERIOD_Msk 0xFFFFUL 110 #define PWM_TX_PWM_CTL2_OFFSET_Pos 16UL 111 #define PWM_TX_PWM_CTL2_OFFSET_Msk 0xFFFF0000UL 112 /* PWM_TX.PWM_CTL3 */ 113 #define PWM_TX_PWM_CTL3_DT_Pos 0UL 114 #define PWM_TX_PWM_CTL3_DT_Msk 0xFFFFUL 115 /* PWM_TX.TX_FIFO_CTL */ 116 #define PWM_TX_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 117 #define PWM_TX_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0x3FUL 118 #define PWM_TX_TX_FIFO_CTL_MUTE_Pos 16UL 119 #define PWM_TX_TX_FIFO_CTL_MUTE_Msk 0x10000UL 120 #define PWM_TX_TX_FIFO_CTL_FREEZE_Pos 17UL 121 #define PWM_TX_TX_FIFO_CTL_FREEZE_Msk 0x20000UL 122 /* PWM_TX.TX_FIFO_STATUS */ 123 #define PWM_TX_TX_FIFO_STATUS_USED_Pos 0UL 124 #define PWM_TX_TX_FIFO_STATUS_USED_Msk 0x7FUL 125 #define PWM_TX_TX_FIFO_STATUS_RD_PTR_Pos 16UL 126 #define PWM_TX_TX_FIFO_STATUS_RD_PTR_Msk 0x3F0000UL 127 #define PWM_TX_TX_FIFO_STATUS_WR_PTR_Pos 24UL 128 #define PWM_TX_TX_FIFO_STATUS_WR_PTR_Msk 0x3F000000UL 129 /* PWM_TX.TX_FIFO_WR */ 130 #define PWM_TX_TX_FIFO_WR_DATA_Pos 0UL 131 #define PWM_TX_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL 132 /* PWM_TX.INTR_TX */ 133 #define PWM_TX_INTR_TX_FIFO_TRIGGER_Pos 0UL 134 #define PWM_TX_INTR_TX_FIFO_TRIGGER_Msk 0x1UL 135 #define PWM_TX_INTR_TX_FIFO_OVERFLOW_Pos 1UL 136 #define PWM_TX_INTR_TX_FIFO_OVERFLOW_Msk 0x2UL 137 #define PWM_TX_INTR_TX_FIFO_UNDERFLOW_Pos 2UL 138 #define PWM_TX_INTR_TX_FIFO_UNDERFLOW_Msk 0x4UL 139 #define PWM_TX_INTR_TX_IF_UNDERFLOW_Pos 8UL 140 #define PWM_TX_INTR_TX_IF_UNDERFLOW_Msk 0x100UL 141 /* PWM_TX.INTR_TX_SET */ 142 #define PWM_TX_INTR_TX_SET_FIFO_TRIGGER_Pos 0UL 143 #define PWM_TX_INTR_TX_SET_FIFO_TRIGGER_Msk 0x1UL 144 #define PWM_TX_INTR_TX_SET_FIFO_OVERFLOW_Pos 1UL 145 #define PWM_TX_INTR_TX_SET_FIFO_OVERFLOW_Msk 0x2UL 146 #define PWM_TX_INTR_TX_SET_FIFO_UNDERFLOW_Pos 2UL 147 #define PWM_TX_INTR_TX_SET_FIFO_UNDERFLOW_Msk 0x4UL 148 #define PWM_TX_INTR_TX_SET_IF_UNDERFLOW_Pos 8UL 149 #define PWM_TX_INTR_TX_SET_IF_UNDERFLOW_Msk 0x100UL 150 /* PWM_TX.INTR_TX_MASK */ 151 #define PWM_TX_INTR_TX_MASK_FIFO_TRIGGER_Pos 0UL 152 #define PWM_TX_INTR_TX_MASK_FIFO_TRIGGER_Msk 0x1UL 153 #define PWM_TX_INTR_TX_MASK_FIFO_OVERFLOW_Pos 1UL 154 #define PWM_TX_INTR_TX_MASK_FIFO_OVERFLOW_Msk 0x2UL 155 #define PWM_TX_INTR_TX_MASK_FIFO_UNDERFLOW_Pos 2UL 156 #define PWM_TX_INTR_TX_MASK_FIFO_UNDERFLOW_Msk 0x4UL 157 #define PWM_TX_INTR_TX_MASK_IF_UNDERFLOW_Pos 8UL 158 #define PWM_TX_INTR_TX_MASK_IF_UNDERFLOW_Msk 0x100UL 159 /* PWM_TX.INTR_TX_MASKED */ 160 #define PWM_TX_INTR_TX_MASKED_FIFO_TRIGGER_Pos 0UL 161 #define PWM_TX_INTR_TX_MASKED_FIFO_TRIGGER_Msk 0x1UL 162 #define PWM_TX_INTR_TX_MASKED_FIFO_OVERFLOW_Pos 1UL 163 #define PWM_TX_INTR_TX_MASKED_FIFO_OVERFLOW_Msk 0x2UL 164 #define PWM_TX_INTR_TX_MASKED_FIFO_UNDERFLOW_Pos 2UL 165 #define PWM_TX_INTR_TX_MASKED_FIFO_UNDERFLOW_Msk 0x4UL 166 #define PWM_TX_INTR_TX_MASKED_IF_UNDERFLOW_Pos 8UL 167 #define PWM_TX_INTR_TX_MASKED_IF_UNDERFLOW_Msk 0x100UL 168 169 170 /* PWM.CTL */ 171 #define PWM_CTL_ACTIVE_Pos 0UL 172 #define PWM_CTL_ACTIVE_Msk 0xFFUL 173 /* PWM.CTL_CLR */ 174 #define PWM_CTL_CLR_ACTIVE_Pos 0UL 175 #define PWM_CTL_CLR_ACTIVE_Msk 0xFFUL 176 /* PWM.CTL_SET */ 177 #define PWM_CTL_SET_ACTIVE_Pos 0UL 178 #define PWM_CTL_SET_ACTIVE_Msk 0xFFUL 179 180 181 #endif /* _CYIP_PWM_H_ */ 182 183 184 /* [] END OF FILE */ 185
