1 /***************************************************************************//** 2 * \file cyip_peri_v2.h 3 * 4 * \brief 5 * PERI IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PERI_V2_H_ 28 #define _CYIP_PERI_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PERI 34 *******************************************************************************/ 35 36 #define PERI_GR_V2_SECTION_SIZE 0x00000020UL 37 #define PERI_TR_GR_V2_SECTION_SIZE 0x00000400UL 38 #define PERI_TR_1TO1_GR_V2_SECTION_SIZE 0x00000400UL 39 #define PERI_V2_SECTION_SIZE 0x00010000UL 40 41 /** 42 * \brief Peripheral group structure (PERI_GR) 43 */ 44 typedef struct { 45 __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */ 46 __IM uint32_t RESERVED[3]; 47 __IOM uint32_t SL_CTL; /*!< 0x00000010 Slave control */ 48 __IM uint32_t RESERVED1[3]; 49 } PERI_GR_V2_Type; /*!< Size = 32 (0x20) */ 50 51 /** 52 * \brief Trigger group (PERI_TR_GR) 53 */ 54 typedef struct { 55 __IOM uint32_t TR_CTL[256]; /*!< 0x00000000 Trigger control register */ 56 } PERI_TR_GR_V2_Type; /*!< Size = 1024 (0x400) */ 57 58 /** 59 * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR) 60 */ 61 typedef struct { 62 __IOM uint32_t TR_CTL[256]; /*!< 0x00000000 Trigger control register */ 63 } PERI_TR_1TO1_GR_V2_Type; /*!< Size = 1024 (0x400) */ 64 65 /** 66 * \brief Peripheral interconnect (PERI) 67 */ 68 typedef struct { 69 __IM uint32_t RESERVED[128]; 70 __IOM uint32_t TIMEOUT_CTL; /*!< 0x00000200 Timeout control */ 71 __IM uint32_t RESERVED1[7]; 72 __IOM uint32_t TR_CMD; /*!< 0x00000220 Trigger command */ 73 __IM uint32_t RESERVED2[119]; 74 __IOM uint32_t DIV_CMD; /*!< 0x00000400 Divider command */ 75 __IM uint32_t RESERVED3[511]; 76 __IOM uint32_t CLOCK_CTL[256]; /*!< 0x00000C00 Clock control */ 77 __IOM uint32_t DIV_8_CTL[256]; /*!< 0x00001000 Divider control (for 8.0 divider) */ 78 __IOM uint32_t DIV_16_CTL[256]; /*!< 0x00001400 Divider control (for 16.0 divider) */ 79 __IOM uint32_t DIV_16_5_CTL[256]; /*!< 0x00001800 Divider control (for 16.5 divider) */ 80 __IOM uint32_t DIV_24_5_CTL[255]; /*!< 0x00001C00 Divider control (for 24.5 divider) */ 81 __IM uint32_t RESERVED4; 82 __IOM uint32_t ECC_CTL; /*!< 0x00002000 ECC control */ 83 __IM uint32_t RESERVED5[2047]; 84 PERI_GR_V2_Type GR[16]; /*!< 0x00004000 Peripheral group structure */ 85 __IM uint32_t RESERVED6[3968]; 86 PERI_TR_GR_V2_Type TR_GR[16]; /*!< 0x00008000 Trigger group */ 87 PERI_TR_1TO1_GR_V2_Type TR_1TO1_GR[16]; /*!< 0x0000C000 Trigger 1-to-1 group */ 88 } PERI_V2_Type; /*!< Size = 65536 (0x10000) */ 89 90 91 /* PERI_GR.CLOCK_CTL */ 92 #define PERI_GR_V2_CLOCK_CTL_INT8_DIV_Pos 8UL 93 #define PERI_GR_V2_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL 94 /* PERI_GR.SL_CTL */ 95 #define PERI_GR_V2_SL_CTL_ENABLED_0_Pos 0UL 96 #define PERI_GR_V2_SL_CTL_ENABLED_0_Msk 0x1UL 97 #define PERI_GR_V2_SL_CTL_ENABLED_1_Pos 1UL 98 #define PERI_GR_V2_SL_CTL_ENABLED_1_Msk 0x2UL 99 #define PERI_GR_V2_SL_CTL_ENABLED_2_Pos 2UL 100 #define PERI_GR_V2_SL_CTL_ENABLED_2_Msk 0x4UL 101 #define PERI_GR_V2_SL_CTL_ENABLED_3_Pos 3UL 102 #define PERI_GR_V2_SL_CTL_ENABLED_3_Msk 0x8UL 103 #define PERI_GR_V2_SL_CTL_ENABLED_4_Pos 4UL 104 #define PERI_GR_V2_SL_CTL_ENABLED_4_Msk 0x10UL 105 #define PERI_GR_V2_SL_CTL_ENABLED_5_Pos 5UL 106 #define PERI_GR_V2_SL_CTL_ENABLED_5_Msk 0x20UL 107 #define PERI_GR_V2_SL_CTL_ENABLED_6_Pos 6UL 108 #define PERI_GR_V2_SL_CTL_ENABLED_6_Msk 0x40UL 109 #define PERI_GR_V2_SL_CTL_ENABLED_7_Pos 7UL 110 #define PERI_GR_V2_SL_CTL_ENABLED_7_Msk 0x80UL 111 #define PERI_GR_V2_SL_CTL_ENABLED_8_Pos 8UL 112 #define PERI_GR_V2_SL_CTL_ENABLED_8_Msk 0x100UL 113 #define PERI_GR_V2_SL_CTL_ENABLED_9_Pos 9UL 114 #define PERI_GR_V2_SL_CTL_ENABLED_9_Msk 0x200UL 115 #define PERI_GR_V2_SL_CTL_ENABLED_10_Pos 10UL 116 #define PERI_GR_V2_SL_CTL_ENABLED_10_Msk 0x400UL 117 #define PERI_GR_V2_SL_CTL_ENABLED_11_Pos 11UL 118 #define PERI_GR_V2_SL_CTL_ENABLED_11_Msk 0x800UL 119 #define PERI_GR_V2_SL_CTL_ENABLED_12_Pos 12UL 120 #define PERI_GR_V2_SL_CTL_ENABLED_12_Msk 0x1000UL 121 #define PERI_GR_V2_SL_CTL_ENABLED_13_Pos 13UL 122 #define PERI_GR_V2_SL_CTL_ENABLED_13_Msk 0x2000UL 123 #define PERI_GR_V2_SL_CTL_ENABLED_14_Pos 14UL 124 #define PERI_GR_V2_SL_CTL_ENABLED_14_Msk 0x4000UL 125 #define PERI_GR_V2_SL_CTL_ENABLED_15_Pos 15UL 126 #define PERI_GR_V2_SL_CTL_ENABLED_15_Msk 0x8000UL 127 #define PERI_GR_V2_SL_CTL_DISABLED_0_Pos 16UL 128 #define PERI_GR_V2_SL_CTL_DISABLED_0_Msk 0x10000UL 129 #define PERI_GR_V2_SL_CTL_DISABLED_1_Pos 17UL 130 #define PERI_GR_V2_SL_CTL_DISABLED_1_Msk 0x20000UL 131 #define PERI_GR_V2_SL_CTL_DISABLED_2_Pos 18UL 132 #define PERI_GR_V2_SL_CTL_DISABLED_2_Msk 0x40000UL 133 #define PERI_GR_V2_SL_CTL_DISABLED_3_Pos 19UL 134 #define PERI_GR_V2_SL_CTL_DISABLED_3_Msk 0x80000UL 135 #define PERI_GR_V2_SL_CTL_DISABLED_4_Pos 20UL 136 #define PERI_GR_V2_SL_CTL_DISABLED_4_Msk 0x100000UL 137 #define PERI_GR_V2_SL_CTL_DISABLED_5_Pos 21UL 138 #define PERI_GR_V2_SL_CTL_DISABLED_5_Msk 0x200000UL 139 #define PERI_GR_V2_SL_CTL_DISABLED_6_Pos 22UL 140 #define PERI_GR_V2_SL_CTL_DISABLED_6_Msk 0x400000UL 141 #define PERI_GR_V2_SL_CTL_DISABLED_7_Pos 23UL 142 #define PERI_GR_V2_SL_CTL_DISABLED_7_Msk 0x800000UL 143 #define PERI_GR_V2_SL_CTL_DISABLED_8_Pos 24UL 144 #define PERI_GR_V2_SL_CTL_DISABLED_8_Msk 0x1000000UL 145 #define PERI_GR_V2_SL_CTL_DISABLED_9_Pos 25UL 146 #define PERI_GR_V2_SL_CTL_DISABLED_9_Msk 0x2000000UL 147 #define PERI_GR_V2_SL_CTL_DISABLED_10_Pos 26UL 148 #define PERI_GR_V2_SL_CTL_DISABLED_10_Msk 0x4000000UL 149 #define PERI_GR_V2_SL_CTL_DISABLED_11_Pos 27UL 150 #define PERI_GR_V2_SL_CTL_DISABLED_11_Msk 0x8000000UL 151 #define PERI_GR_V2_SL_CTL_DISABLED_12_Pos 28UL 152 #define PERI_GR_V2_SL_CTL_DISABLED_12_Msk 0x10000000UL 153 #define PERI_GR_V2_SL_CTL_DISABLED_13_Pos 29UL 154 #define PERI_GR_V2_SL_CTL_DISABLED_13_Msk 0x20000000UL 155 #define PERI_GR_V2_SL_CTL_DISABLED_14_Pos 30UL 156 #define PERI_GR_V2_SL_CTL_DISABLED_14_Msk 0x40000000UL 157 #define PERI_GR_V2_SL_CTL_DISABLED_15_Pos 31UL 158 #define PERI_GR_V2_SL_CTL_DISABLED_15_Msk 0x80000000UL 159 160 161 /* PERI_TR_GR.TR_CTL */ 162 #define PERI_TR_GR_V2_TR_CTL_TR_SEL_Pos 0UL 163 #define PERI_TR_GR_V2_TR_CTL_TR_SEL_Msk 0xFFUL 164 #define PERI_TR_GR_V2_TR_CTL_TR_INV_Pos 8UL 165 #define PERI_TR_GR_V2_TR_CTL_TR_INV_Msk 0x100UL 166 #define PERI_TR_GR_V2_TR_CTL_TR_EDGE_Pos 9UL 167 #define PERI_TR_GR_V2_TR_CTL_TR_EDGE_Msk 0x200UL 168 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos 12UL 169 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL 170 171 172 /* PERI_TR_1TO1_GR.TR_CTL */ 173 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Pos 0UL 174 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk 0x1UL 175 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Pos 8UL 176 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk 0x100UL 177 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Pos 9UL 178 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk 0x200UL 179 #define PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos 12UL 180 #define PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL 181 182 183 /* PERI.TIMEOUT_CTL */ 184 #define PERI_V2_TIMEOUT_CTL_TIMEOUT_Pos 0UL 185 #define PERI_V2_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL 186 /* PERI.TR_CMD */ 187 #define PERI_V2_TR_CMD_TR_SEL_Pos 0UL 188 #define PERI_V2_TR_CMD_TR_SEL_Msk 0xFFUL 189 #define PERI_V2_TR_CMD_GROUP_SEL_Pos 8UL 190 #define PERI_V2_TR_CMD_GROUP_SEL_Msk 0x1F00UL 191 #define PERI_V2_TR_CMD_TR_EDGE_Pos 29UL 192 #define PERI_V2_TR_CMD_TR_EDGE_Msk 0x20000000UL 193 #define PERI_V2_TR_CMD_OUT_SEL_Pos 30UL 194 #define PERI_V2_TR_CMD_OUT_SEL_Msk 0x40000000UL 195 #define PERI_V2_TR_CMD_ACTIVATE_Pos 31UL 196 #define PERI_V2_TR_CMD_ACTIVATE_Msk 0x80000000UL 197 /* PERI.DIV_CMD */ 198 #define PERI_V2_DIV_CMD_DIV_SEL_Pos 0UL 199 #define PERI_V2_DIV_CMD_DIV_SEL_Msk 0xFFUL 200 #define PERI_V2_DIV_CMD_TYPE_SEL_Pos 8UL 201 #define PERI_V2_DIV_CMD_TYPE_SEL_Msk 0x300UL 202 #define PERI_V2_DIV_CMD_PA_DIV_SEL_Pos 16UL 203 #define PERI_V2_DIV_CMD_PA_DIV_SEL_Msk 0xFF0000UL 204 #define PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos 24UL 205 #define PERI_V2_DIV_CMD_PA_TYPE_SEL_Msk 0x3000000UL 206 #define PERI_V2_DIV_CMD_DISABLE_Pos 30UL 207 #define PERI_V2_DIV_CMD_DISABLE_Msk 0x40000000UL 208 #define PERI_V2_DIV_CMD_ENABLE_Pos 31UL 209 #define PERI_V2_DIV_CMD_ENABLE_Msk 0x80000000UL 210 /* PERI.CLOCK_CTL */ 211 #define PERI_V2_CLOCK_CTL_DIV_SEL_Pos 0UL 212 #define PERI_V2_CLOCK_CTL_DIV_SEL_Msk 0xFFUL 213 #define PERI_V2_CLOCK_CTL_TYPE_SEL_Pos 8UL 214 #define PERI_V2_CLOCK_CTL_TYPE_SEL_Msk 0x300UL 215 /* PERI.DIV_8_CTL */ 216 #define PERI_V2_DIV_8_CTL_EN_Pos 0UL 217 #define PERI_V2_DIV_8_CTL_EN_Msk 0x1UL 218 #define PERI_V2_DIV_8_CTL_INT8_DIV_Pos 8UL 219 #define PERI_V2_DIV_8_CTL_INT8_DIV_Msk 0xFF00UL 220 /* PERI.DIV_16_CTL */ 221 #define PERI_V2_DIV_16_CTL_EN_Pos 0UL 222 #define PERI_V2_DIV_16_CTL_EN_Msk 0x1UL 223 #define PERI_V2_DIV_16_CTL_INT16_DIV_Pos 8UL 224 #define PERI_V2_DIV_16_CTL_INT16_DIV_Msk 0xFFFF00UL 225 /* PERI.DIV_16_5_CTL */ 226 #define PERI_V2_DIV_16_5_CTL_EN_Pos 0UL 227 #define PERI_V2_DIV_16_5_CTL_EN_Msk 0x1UL 228 #define PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL 229 #define PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL 230 #define PERI_V2_DIV_16_5_CTL_INT16_DIV_Pos 8UL 231 #define PERI_V2_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL 232 /* PERI.DIV_24_5_CTL */ 233 #define PERI_V2_DIV_24_5_CTL_EN_Pos 0UL 234 #define PERI_V2_DIV_24_5_CTL_EN_Msk 0x1UL 235 #define PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL 236 #define PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL 237 #define PERI_V2_DIV_24_5_CTL_INT24_DIV_Pos 8UL 238 #define PERI_V2_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL 239 /* PERI.ECC_CTL */ 240 #define PERI_V2_ECC_CTL_WORD_ADDR_Pos 0UL 241 #define PERI_V2_ECC_CTL_WORD_ADDR_Msk 0x7FFUL 242 #define PERI_V2_ECC_CTL_ECC_EN_Pos 16UL 243 #define PERI_V2_ECC_CTL_ECC_EN_Msk 0x10000UL 244 #define PERI_V2_ECC_CTL_ECC_INJ_EN_Pos 18UL 245 #define PERI_V2_ECC_CTL_ECC_INJ_EN_Msk 0x40000UL 246 #define PERI_V2_ECC_CTL_PARITY_Pos 24UL 247 #define PERI_V2_ECC_CTL_PARITY_Msk 0xFF000000UL 248 249 250 #endif /* _CYIP_PERI_V2_H_ */ 251 252 253 /* [] END OF FILE */ 254
