1 /***************************************************************************//** 2 * \file cyip_lcd_v2.h 3 * 4 * \brief 5 * LCD IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_LCD_V2_H_ 28 #define _CYIP_LCD_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * LCD 34 *******************************************************************************/ 35 36 #define LCD_V2_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief LCD Controller Block (LCD) 40 */ 41 typedef struct { 42 __IM uint32_t ID; /*!< 0x00000000 ID & Revision */ 43 __IOM uint32_t DIVIDER; /*!< 0x00000004 LCD Divider Register */ 44 __IOM uint32_t CONTROL; /*!< 0x00000008 LCD Configuration Register */ 45 __IM uint32_t RESERVED[61]; 46 __IOM uint32_t DATA0[8]; /*!< 0x00000100 LCD Pin Data Registers */ 47 __IM uint32_t RESERVED1[56]; 48 __IOM uint32_t DATA1[8]; /*!< 0x00000200 LCD Pin Data Registers */ 49 __IM uint32_t RESERVED2[56]; 50 __IOM uint32_t DATA2[8]; /*!< 0x00000300 LCD Pin Data Registers */ 51 __IM uint32_t RESERVED3[56]; 52 __IOM uint32_t DATA3[8]; /*!< 0x00000400 LCD Pin Data Registers */ 53 } LCD_V2_Type; /*!< Size = 1056 (0x420) */ 54 55 56 /* LCD.ID */ 57 #define LCD_V2_ID_ID_Pos 0UL 58 #define LCD_V2_ID_ID_Msk 0xFFFFUL 59 #define LCD_V2_ID_REVISION_Pos 16UL 60 #define LCD_V2_ID_REVISION_Msk 0xFFFF0000UL 61 /* LCD.DIVIDER */ 62 #define LCD_V2_DIVIDER_SUBFR_DIV_Pos 0UL 63 #define LCD_V2_DIVIDER_SUBFR_DIV_Msk 0xFFFFUL 64 #define LCD_V2_DIVIDER_DEAD_DIV_Pos 16UL 65 #define LCD_V2_DIVIDER_DEAD_DIV_Msk 0xFFFF0000UL 66 /* LCD.CONTROL */ 67 #define LCD_V2_CONTROL_LS_EN_Pos 0UL 68 #define LCD_V2_CONTROL_LS_EN_Msk 0x1UL 69 #define LCD_V2_CONTROL_HS_EN_Pos 1UL 70 #define LCD_V2_CONTROL_HS_EN_Msk 0x2UL 71 #define LCD_V2_CONTROL_LCD_MODE_Pos 2UL 72 #define LCD_V2_CONTROL_LCD_MODE_Msk 0x4UL 73 #define LCD_V2_CONTROL_TYPE_Pos 3UL 74 #define LCD_V2_CONTROL_TYPE_Msk 0x8UL 75 #define LCD_V2_CONTROL_OP_MODE_Pos 4UL 76 #define LCD_V2_CONTROL_OP_MODE_Msk 0x10UL 77 #define LCD_V2_CONTROL_BIAS_Pos 5UL 78 #define LCD_V2_CONTROL_BIAS_Msk 0x60UL 79 #define LCD_V2_CONTROL_CLOCK_LS_SEL_Pos 7UL 80 #define LCD_V2_CONTROL_CLOCK_LS_SEL_Msk 0x80UL 81 #define LCD_V2_CONTROL_COM_NUM_Pos 8UL 82 #define LCD_V2_CONTROL_COM_NUM_Msk 0xF00UL 83 #define LCD_V2_CONTROL_LS_EN_STAT_Pos 31UL 84 #define LCD_V2_CONTROL_LS_EN_STAT_Msk 0x80000000UL 85 /* LCD.DATA0 */ 86 #define LCD_V2_DATA0_DATA_Pos 0UL 87 #define LCD_V2_DATA0_DATA_Msk 0xFFFFFFFFUL 88 /* LCD.DATA1 */ 89 #define LCD_V2_DATA1_DATA_Pos 0UL 90 #define LCD_V2_DATA1_DATA_Msk 0xFFFFFFFFUL 91 /* LCD.DATA2 */ 92 #define LCD_V2_DATA2_DATA_Pos 0UL 93 #define LCD_V2_DATA2_DATA_Msk 0xFFFFFFFFUL 94 /* LCD.DATA3 */ 95 #define LCD_V2_DATA3_DATA_Pos 0UL 96 #define LCD_V2_DATA3_DATA_Msk 0xFFFFFFFFUL 97 98 99 #endif /* _CYIP_LCD_V2_H_ */ 100 101 102 /* [] END OF FILE */ 103
