1 /***************************************************************************//** 2 * \file cyip_eth.h 3 * 4 * \brief 5 * ETH IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_ETH_H_ 28 #define _CYIP_ETH_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * ETH 34 *******************************************************************************/ 35 36 #define ETH_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief Ethernet Interface (ETH) 40 */ 41 typedef struct { 42 __IOM uint32_t CTL; /*!< 0x00000000 MXETH Control Register */ 43 __IM uint32_t STATUS; /*!< 0x00000004 MXETH Status Register */ 44 __IM uint32_t RESERVED[1022]; 45 __IOM uint32_t NETWORK_CONTROL; /*!< 0x00001000 The network control register contains general MAC control 46 functions for both receiver and transmitter. */ 47 __IOM uint32_t NETWORK_CONFIG; /*!< 0x00001004 The network configuration register contains functions for 48 setting the mode of operation for the Gigabit Ethernet MAC. */ 49 __IM uint32_t NETWORK_STATUS; /*!< 0x00001008 The network status register returns status information with 50 respect to the PHY management interface. */ 51 __IM uint32_t USER_IO_REGISTER; /*!< 0x0000100C Not presents. Access to the register will return AHB error. */ 52 __IOM uint32_t DMA_CONFIG; /*!< 0x00001010 DMA Configuration Register */ 53 __IOM uint32_t TRANSMIT_STATUS; /*!< 0x00001014 This register, when read, provides details of the status of a 54 transmit. Once read, individual bits may be cleared by writing 1 55 to them. It is not possible to set a bit to 1 by writing to the 56 register. */ 57 __IOM uint32_t RECEIVE_Q_PTR; /*!< 0x00001018 This register holds the start address of the receive buffer 58 queue (receive buffers descriptor list). The receive buffer 59 queue base address must be initialized before receive is enabled 60 through bit 2 of the network control register. Once reception is 61 enabled, any write to the receive buffer queue base address 62 register is ignored. Reading this register returns the location 63 of the descriptor currently being accessed. This value 64 increments as buffers are used. Software should not use this 65 register for determining where to remove received frames from 66 the queue as it constantly changes as new frames are received. 67 Software should instead work its way through the buffer 68 descriptor queue checking the used bits. In terms of AMBA (AXI) 69 operation, the receive descriptors are read from memory using a 70 single 32bit AXI access. When the datapath is configured at 71 64bit, the receive descriptors should be aligned at 64-bit 72 boundaries and each pair of 32-bit descriptors is written to 73 using a single 64bit AXI access. */ 74 __IOM uint32_t TRANSMIT_Q_PTR; /*!< 0x0000101C This register holds the start address of the transmit buffer 75 queue (transmit buffers descriptor list). The transmit buffer 76 queue base address register must be initialized before transmit 77 is started through bit 9 of the network control register. Once 78 transmission has started, any write to the transmit buffer queue 79 base address register is illegal and therefore ignored. Note 80 that due to clock boundary synchronization, it takes a maximum 81 of four pclk cycles from the writing of the transmit start bit 82 before the transmitter is active. Writing to the transmit buffer 83 queue base address register during this time may produce 84 unpredictable results. Reading this register returns the 85 location of the descriptor currently being accessed. Because the 86 DMA can store data for multiple frames at once, this may not 87 necessarily be pointing to the current frame being transmitted. 88 In terms of AMBA AXI operation, the transmit descriptors are 89 written to memory using a single 32bit AHB access. When the 90 datapath is configured as 64bit, the transmit descriptors should 91 be aligned at 64-bit boundaries and each pair of 32-bit 92 descriptors is read from memory using a single AXI access. */ 93 __IOM uint32_t RECEIVE_STATUS; /*!< 0x00001020 This register, when read provides details of the status of a 94 receive. Once read, individual bits may be cleared by writing 1 95 to them. It is not possible to set a bit to 1 by writing to the 96 register. */ 97 __IOM uint32_t INT_STATUS; /*!< 0x00001024 If not configured for priority queueing, the GEM generates a 98 single interrupt. This register indicates the source of this 99 interrupt. The corresponding bit in the mask register must be 100 clear for a bit to be set. If any bit is set in this register 101 the ethernet_int signal will be asserted. For test purposes each 102 bit can be set or reset by writing to the interrupt mask 103 register. The default configuration is shown below whereby all 104 bits are reset to zero on read. Changing the validity of the 105 `gem_irq_read_clear define will instead require a one to be 106 written to the appropriate bit in order to clear it. In this 107 mode reading has no affect on the status of the bit. */ 108 __OM uint32_t INT_ENABLE; /*!< 0x00001028 At reset all interrupts are disabled. Writing a one to the 109 relevant bit location enables the required interrupt. This 110 register is write only and when read will return zero. */ 111 __IOM uint32_t INT_DISABLE; /*!< 0x0000102C Writing a 1 to the relevant bit location disables that 112 particular interrupt. This register is write only and when read 113 will return zero. */ 114 __IM uint32_t INT_MASK; /*!< 0x00001030 The interrupt mask register is a read only register indicating 115 which interrupts are masked. All bits are set at reset and can 116 be reset individually by writing to the interrupt enable 117 register or set individually by writing to the interrupt disable 118 register. Having separate address locations for enable and 119 disable saves the need for performing a read modify write when 120 updating the interrupt mask register. For test purposes there is 121 a write-only function to this register that allows the bits in 122 the interrupt status register to be set or cleared, regardless 123 of the state of the mask register. */ 124 __IOM uint32_t PHY_MANAGEMENT; /*!< 0x00001034 The PHY maintenance register is implemented as a shift 125 register. Writing to the register starts a shift operation which 126 is signalled as complete when bit-2 is set in the network status 127 register. It takes about 2000 pclk cycles to complete, when MDC 128 is set for pclk divide by 32 in the network configuration 129 register. An interrupt is generated upon completion. During this 130 time, the MSB of the register is output on the MDIO pin and the 131 LSB updated from the MDIO pin with each MDC cycle. This causes 132 transmission of a PHY management frame on MDIO. See Section 133 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift 134 operation will return the current contents of the shift 135 register. At the end of management operation, the bits will have 136 shifted back to their original locations. For a read operation, 137 the data bits will be updated with data read from the PHY. It is 138 important to write the correct values to the register to ensure 139 a valid PHY management frame is produced. The MDIO interface can 140 read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To 141 read clause 45 PHYs, bit 30 should be written with a 0 rather 142 than a 1. For a description of MDC generation, see Network 143 Configuration Register. */ 144 __IM uint32_t PAUSE_TIME; /*!< 0x00001038 Received Pause Quantum Register */ 145 __IOM uint32_t TX_PAUSE_QUANTUM; /*!< 0x0000103C Transmit Pause Quantum Register */ 146 __IOM uint32_t PBUF_TXCUTTHRU; /*!< 0x00001040 Partial store and forward is only applicable when using the DMA 147 configured in SRAM based packet buffer mode. It is also not 148 available when using multi buffer frames. TX Partial Store and 149 Forward */ 150 __IOM uint32_t PBUF_RXCUTTHRU; /*!< 0x00001044 RX Partial Store and Forward */ 151 __IOM uint32_t JUMBO_MAX_LENGTH; /*!< 0x00001048 Maximum Jumbo Frame Size. */ 152 __IM uint32_t EXTERNAL_FIFO_INTERFACE; /*!< 0x0000104C Not presents. */ 153 __IM uint32_t RESERVED1; 154 __IOM uint32_t AXI_MAX_PIPELINE; /*!< 0x00001054 Used to set the maximum amount of outstanding transactions on 155 the AXI bus between AR / R channels and AW / W channels. Cannot 156 be more than the depth of the configured AXI pipeline FIFO 157 (defined in verilog defs.v) */ 158 __IM uint32_t RSC_CONTROL; /*!< 0x00001058 Not presents. Access to the register will return AHB error. */ 159 __IOM uint32_t INT_MODERATION; /*!< 0x0000105C Used to moderate the number of transmit and receive complete 160 interrupts issued. With interrupt moderation enabled receive and 161 transmit interrupts are not generated immediately a frame is 162 transmitted or received. Instead when a receive or transmit 163 event occurs a timer is started and the interrupt is asserted 164 after it times out. This limits the frequency with which the CPU 165 receives interrupts. When interrupt moderation is enabled 166 interrupt status bit one is always used for receive and bit 7 is 167 always used for transmit even when priority queuing is enabled. 168 With interrupt moderation 800ns periods are counted. GEM 169 determines what constitutes an 800ns period by looking at the 170 tbi (bit 11), gigabit bit (10) and speed (bit 0) bits in the 171 network configuration register and counting tx_clk cycles. Bit 0 172 needs to be set to 1 for 100M operation. */ 173 __IOM uint32_t SYS_WAKE_TIME; /*!< 0x00001060 Used to pause transmission after deassertion of tx_lpi_en. Each 174 unit in this register corresponds to 64ns in gigabit mode, 320ns 175 in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted 176 transmission will pause for the set time. */ 177 __IM uint32_t RESERVED2[7]; 178 __IOM uint32_t HASH_BOTTOM; /*!< 0x00001080 The unicast hash enable and the multicast hash enable bits in 179 the network configuration register enable the reception of hash 180 matched frames. Hash Register Bottom (31 to 0 bits) */ 181 __IOM uint32_t HASH_TOP; /*!< 0x00001084 Hash Register Top (63 to 32 bits) */ 182 __IOM uint32_t SPEC_ADD1_BOTTOM; /*!< 0x00001088 The addresses stored in the specific address registers are 183 deactivated at reset or when their corresponding specific 184 address register bottom is written. They are activated when 185 specific address register top is written. */ 186 __IOM uint32_t SPEC_ADD1_TOP; /*!< 0x0000108C Specific Address Top */ 187 __IOM uint32_t SPEC_ADD2_BOTTOM; /*!< 0x00001090 The addresses stored in the specific address registers are 188 deactivated at reset or when their corresponding specific 189 address register bottom is written. They are activated when 190 specific address register top is written. */ 191 __IOM uint32_t SPEC_ADD2_TOP; /*!< 0x00001094 Specific Address Top */ 192 __IOM uint32_t SPEC_ADD3_BOTTOM; /*!< 0x00001098 The addresses stored in the specific address registers are 193 deactivated at reset or when their corresponding specific 194 address register bottom is written. They are activated when 195 specific address register top is written. */ 196 __IOM uint32_t SPEC_ADD3_TOP; /*!< 0x0000109C Specific Address Top */ 197 __IOM uint32_t SPEC_ADD4_BOTTOM; /*!< 0x000010A0 The addresses stored in the specific address registers are 198 deactivated at reset or when their corresponding specific 199 address register bottom is written. They are activated when 200 specific address register top is written. */ 201 __IOM uint32_t SPEC_ADD4_TOP; /*!< 0x000010A4 Specific Address Top */ 202 __IOM uint32_t SPEC_TYPE1; /*!< 0x000010A8 Type ID Match 1 */ 203 __IOM uint32_t SPEC_TYPE2; /*!< 0x000010AC Type ID Match 2 */ 204 __IOM uint32_t SPEC_TYPE3; /*!< 0x000010B0 Type ID Match 3 */ 205 __IOM uint32_t SPEC_TYPE4; /*!< 0x000010B4 Type ID Match 4 */ 206 __IOM uint32_t WOL_REGISTER; /*!< 0x000010B8 Wake on LAN Register. Presents in design, but feature is not 207 supported. */ 208 __IOM uint32_t STRETCH_RATIO; /*!< 0x000010BC IPG stretch register */ 209 __IOM uint32_t STACKED_VLAN; /*!< 0x000010C0 Stacked VLAN Register */ 210 __IOM uint32_t TX_PFC_PAUSE; /*!< 0x000010C4 Transmit PFC Pause Register */ 211 __IOM uint32_t MASK_ADD1_BOTTOM; /*!< 0x000010C8 Specific Address Mask 1 Bottom (31 to 0 bits) */ 212 __IOM uint32_t MASK_ADD1_TOP; /*!< 0x000010CC Specific Address Mask 1 Top (47 to 32 bits) */ 213 __IOM uint32_t DMA_ADDR_OR_MASK; /*!< 0x000010D0 Receive DMA Data Buffer Address Mask */ 214 __IOM uint32_t RX_PTP_UNICAST; /*!< 0x000010D4 PTP RX unicast IP destination address */ 215 __IOM uint32_t TX_PTP_UNICAST; /*!< 0x000010D8 PTP TX unicast IP destination address */ 216 __IOM uint32_t TSU_NSEC_CMP; /*!< 0x000010DC TSU timer comparison value nanoseconds */ 217 __IOM uint32_t TSU_SEC_CMP; /*!< 0x000010E0 TSU timer comparison value seconds (31 to 0 bits) */ 218 __IOM uint32_t TSU_MSB_SEC_CMP; /*!< 0x000010E4 TSU timer comparison value seconds (47 to 32 bits) */ 219 __IM uint32_t TSU_PTP_TX_MSB_SEC; /*!< 0x000010E8 PTP Event Frame Transmitted Seconds Register (47 to 32 bits) */ 220 __IM uint32_t TSU_PTP_RX_MSB_SEC; /*!< 0x000010EC PTP Event Frame Received Seconds Register (47 to 32 bits) */ 221 __IM uint32_t TSU_PEER_TX_MSB_SEC; /*!< 0x000010F0 PTP Peer Event Frame Transmitted Seconds Register (47 to 32 222 bits) */ 223 __IM uint32_t TSU_PEER_RX_MSB_SEC; /*!< 0x000010F4 PTP Peer Event Frame Received Seconds Register (47 to 32 bits) */ 224 __IOM uint32_t DPRAM_FILL_DBG; /*!< 0x000010F8 The fill levels for the TX & RX packet buffers can be read 225 using this register, including the fill level for each queue in 226 the TX direction. */ 227 __IM uint32_t REVISION_REG; /*!< 0x000010FC This register indicates a Cadence module identification number 228 and module revision. The value of this register is read only as 229 defined by `gem_revision_reg_value */ 230 __IM uint32_t OCTETS_TXED_BOTTOM; /*!< 0x00001100 Octets Transmitted lower bits (31 to 0 bits) */ 231 __IM uint32_t OCTETS_TXED_TOP; /*!< 0x00001104 Octets Transmitted higher bits (47 to 32 bits) */ 232 __IM uint32_t FRAMES_TXED_OK; /*!< 0x00001108 Frames Transmitted */ 233 __IM uint32_t BROADCAST_TXED; /*!< 0x0000110C Broadcast Frames Transmitted */ 234 __IM uint32_t MULTICAST_TXED; /*!< 0x00001110 Multicast Frames Transmitted */ 235 __IM uint32_t PAUSE_FRAMES_TXED; /*!< 0x00001114 Pause Frames Transmitted */ 236 __IM uint32_t FRAMES_TXED_64; /*!< 0x00001118 64 Byte Frames Transmitted */ 237 __IM uint32_t FRAMES_TXED_65; /*!< 0x0000111C 65 to 127 Byte Frames Transmitted */ 238 __IM uint32_t FRAMES_TXED_128; /*!< 0x00001120 128 to 255 Byte Frames Transmitted */ 239 __IM uint32_t FRAMES_TXED_256; /*!< 0x00001124 256 to 511 Byte Frames Transmitted */ 240 __IM uint32_t FRAMES_TXED_512; /*!< 0x00001128 512 to 1023 Byte Frames Transmitted */ 241 __IM uint32_t FRAMES_TXED_1024; /*!< 0x0000112C 1024 to 1518 Byte Frames Transmitted */ 242 __IM uint32_t FRAMES_TXED_1519; /*!< 0x00001130 Greater Than 1518 Byte Frames Transmitted */ 243 __IM uint32_t TX_UNDERRUNS; /*!< 0x00001134 Transmit Under Runs */ 244 __IM uint32_t SINGLE_COLLISIONS; /*!< 0x00001138 Single Collision Frames. Presents in design but not support. */ 245 __IM uint32_t MULTIPLE_COLLISIONS; /*!< 0x0000113C Multiple Collision Frames. Presents in design but not support. */ 246 __IM uint32_t EXCESSIVE_COLLISIONS; /*!< 0x00001140 Excessive Collisions. Presents in design but not support. */ 247 __IM uint32_t LATE_COLLISIONS; /*!< 0x00001144 Late Collisions. Presents in design but not support. */ 248 __IM uint32_t DEFERRED_FRAMES; /*!< 0x00001148 Deferred Transmission Frames. Presents in design but not 249 support. */ 250 __IM uint32_t CRS_ERRORS; /*!< 0x0000114C Carrier Sense Errors. Presents in design but not support. */ 251 __IM uint32_t OCTETS_RXED_BOTTOM; /*!< 0x00001150 Octets Received (31 to 0 bits) */ 252 __IM uint32_t OCTETS_RXED_TOP; /*!< 0x00001154 Octets Received (47 to 32 bits) */ 253 __IM uint32_t FRAMES_RXED_OK; /*!< 0x00001158 Frames Received */ 254 __IM uint32_t BROADCAST_RXED; /*!< 0x0000115C Broadcast Frames Received */ 255 __IM uint32_t MULTICAST_RXED; /*!< 0x00001160 Multicast Frames Received */ 256 __IM uint32_t PAUSE_FRAMES_RXED; /*!< 0x00001164 Pause Frames Received */ 257 __IM uint32_t FRAMES_RXED_64; /*!< 0x00001168 64 Byte Frames Received */ 258 __IM uint32_t FRAMES_RXED_65; /*!< 0x0000116C 65 to 127 Byte Frames Received */ 259 __IM uint32_t FRAMES_RXED_128; /*!< 0x00001170 128 to 255 Byte Frames Received */ 260 __IM uint32_t FRAMES_RXED_256; /*!< 0x00001174 256 to 511 Byte Frames Received */ 261 __IM uint32_t FRAMES_RXED_512; /*!< 0x00001178 512 to 1023 Byte Frames Received */ 262 __IM uint32_t FRAMES_RXED_1024; /*!< 0x0000117C 1024 to 1518 Byte Frames Received */ 263 __IM uint32_t FRAMES_RXED_1519; /*!< 0x00001180 1519 to maximum Byte Frames Received */ 264 __IM uint32_t UNDERSIZE_FRAMES; /*!< 0x00001184 Undersized Frames Received */ 265 __IM uint32_t EXCESSIVE_RX_LENGTH; /*!< 0x00001188 Oversize Frames Received */ 266 __IM uint32_t RX_JABBERS; /*!< 0x0000118C Jabbers Received */ 267 __IM uint32_t FCS_ERRORS; /*!< 0x00001190 Frame Check Sequence Errors */ 268 __IM uint32_t RX_LENGTH_ERRORS; /*!< 0x00001194 Length Field Frame Errors */ 269 __IM uint32_t RX_SYMBOL_ERRORS; /*!< 0x00001198 Receive Symbol Errors */ 270 __IM uint32_t ALIGNMENT_ERRORS; /*!< 0x0000119C Alignment Errors */ 271 __IM uint32_t RX_RESOURCE_ERRORS; /*!< 0x000011A0 Receive Resource Errors */ 272 __IM uint32_t RX_OVERRUNS; /*!< 0x000011A4 Receive Overruns */ 273 __IM uint32_t RX_IP_CK_ERRORS; /*!< 0x000011A8 IP Header Checksum Errors */ 274 __IM uint32_t RX_TCP_CK_ERRORS; /*!< 0x000011AC TCP Checksum Errors */ 275 __IM uint32_t RX_UDP_CK_ERRORS; /*!< 0x000011B0 UDP Checksum Errors */ 276 __IM uint32_t AUTO_FLUSHED_PKTS; /*!< 0x000011B4 Receive DMA Flushed Packets */ 277 __IM uint32_t RESERVED3; 278 __IOM uint32_t TSU_TIMER_INCR_SUB_NSEC; /*!< 0x000011BC 1588 Timer Increment Register sub nsec */ 279 __IOM uint32_t TSU_TIMER_MSB_SEC; /*!< 0x000011C0 1588 Timer Seconds Register (47 to 32 bits) */ 280 __IM uint32_t TSU_STROBE_MSB_SEC; /*!< 0x000011C4 1588 Timer Sync Strobe Seconds Register (47 to 32 bits) */ 281 __IM uint32_t TSU_STROBE_SEC; /*!< 0x000011C8 1588 Timer Sync Strobe Seconds Register (31 to 0 bits) */ 282 __IM uint32_t TSU_STROBE_NSEC; /*!< 0x000011CC 1588 Timer Sync Strobe Nanoseconds Register */ 283 __IOM uint32_t TSU_TIMER_SEC; /*!< 0x000011D0 1588 Timer Seconds Register (31 to 0 bits) */ 284 __IOM uint32_t TSU_TIMER_NSEC; /*!< 0x000011D4 1588 Timer Nanoseconds Register */ 285 __OM uint32_t TSU_TIMER_ADJUST; /*!< 0x000011D8 This register is used to adjust the value of the timer in the 286 TSU. It allows an integral number of nanoseconds to be added or 287 subtracted from the timer in a one-off operation. This register 288 returns all zeroes when read. */ 289 __IOM uint32_t TSU_TIMER_INCR; /*!< 0x000011DC 1588 Timer Increment Register */ 290 __IM uint32_t TSU_PTP_TX_SEC; /*!< 0x000011E0 PTP Event Frame Transmitted Seconds Register (31 to 0 bits) */ 291 __IM uint32_t TSU_PTP_TX_NSEC; /*!< 0x000011E4 PTP Event Frame Transmitted Nanoseconds Register */ 292 __IM uint32_t TSU_PTP_RX_SEC; /*!< 0x000011E8 PTP Event Frame Received Seconds Register (31 to 0 bits) */ 293 __IM uint32_t TSU_PTP_RX_NSEC; /*!< 0x000011EC PTP Event Frame Received Nanoseconds Register */ 294 __IM uint32_t TSU_PEER_TX_SEC; /*!< 0x000011F0 PTP Peer Event Frame Transmitted Seconds Register (31 to 0 295 bits) */ 296 __IM uint32_t TSU_PEER_TX_NSEC; /*!< 0x000011F4 PTP Peer Event Frame Transmitted Nanoseconds Register */ 297 __IM uint32_t TSU_PEER_RX_SEC; /*!< 0x000011F8 PTP Peer Event Frame Received Seconds Register (31 to 0 bits) */ 298 __IM uint32_t TSU_PEER_RX_NSEC; /*!< 0x000011FC PTP Peer Event Frame Received Nanoseconds Register */ 299 __IM uint32_t PCS_CONTROL; /*!< 0x00001200 Not presents. Access to the register returns AHB error. */ 300 __IM uint32_t PCS_STATUS; /*!< 0x00001204 Not presents. Access to the register returns AHB error. */ 301 __IM uint32_t RESERVED4[2]; 302 __IM uint32_t PCS_AN_ADV; /*!< 0x00001210 Not presents. Access to the register returns AHB error. */ 303 __IM uint32_t PCS_AN_LP_BASE; /*!< 0x00001214 Not presents. Access to the register returns AHB error. */ 304 __IM uint32_t PCS_AN_EXP; /*!< 0x00001218 Not presents. Access to the register returns AHB error. */ 305 __IM uint32_t PCS_AN_NP_TX; /*!< 0x0000121C Not presents. Access to the register returns AHB error. */ 306 __IM uint32_t PCS_AN_LP_NP; /*!< 0x00001220 Not presents. Access to the register returns AHB error. */ 307 __IM uint32_t RESERVED5[6]; 308 __IM uint32_t PCS_AN_EXT_STATUS; /*!< 0x0000123C Not presents. Access to the register returns AHB error. */ 309 __IM uint32_t RESERVED6[8]; 310 __IOM uint32_t TX_PAUSE_QUANTUM1; /*!< 0x00001260 Transmit Pause Quantum Register 1 */ 311 __IOM uint32_t TX_PAUSE_QUANTUM2; /*!< 0x00001264 Transmit Pause Quantum Register 2 */ 312 __IOM uint32_t TX_PAUSE_QUANTUM3; /*!< 0x00001268 Transmit Pause Quantum Register 3 */ 313 __IM uint32_t RESERVED7; 314 __IM uint32_t RX_LPI; /*!< 0x00001270 Received LPI transitions */ 315 __IM uint32_t RX_LPI_TIME; /*!< 0x00001274 Received LPI time */ 316 __IM uint32_t TX_LPI; /*!< 0x00001278 Transmit LPI transitions */ 317 __IM uint32_t TX_LPI_TIME; /*!< 0x0000127C Transmit LPI time */ 318 __IM uint32_t DESIGNCFG_DEBUG1; /*!< 0x00001280 The GEM_GXL(3PIP) has many parameterisation options to 319 configure the IP during compilation stage. This is achieved 320 using Verilog define compiler directives in an include file 321 called mxeth_defs.v. */ 322 __IM uint32_t DESIGNCFG_DEBUG2; /*!< 0x00001284 Design Configuration Register 2 */ 323 __IM uint32_t DESIGNCFG_DEBUG3; /*!< 0x00001288 Design Configuration Register 3 */ 324 __IM uint32_t DESIGNCFG_DEBUG4; /*!< 0x0000128C Design Configuration Register 4 */ 325 __IM uint32_t DESIGNCFG_DEBUG5; /*!< 0x00001290 Design Configuration Register 5 */ 326 __IM uint32_t DESIGNCFG_DEBUG6; /*!< 0x00001294 Design Configuration Register 6 */ 327 __IM uint32_t DESIGNCFG_DEBUG7; /*!< 0x00001298 Design Configuration Register 7 */ 328 __IM uint32_t DESIGNCFG_DEBUG8; /*!< 0x0000129C Design Configuration Register 8 */ 329 __IM uint32_t DESIGNCFG_DEBUG9; /*!< 0x000012A0 Design Configuration Register 9 */ 330 __IM uint32_t DESIGNCFG_DEBUG10; /*!< 0x000012A4 Design Configuration Register 10 */ 331 __IM uint32_t RESERVED8[22]; 332 __IM uint32_t SPEC_ADD5_BOTTOM; /*!< 0x00001300 Specific address registers 5 ~ 36 doesn't present. Access to 333 the register returns AHB error. */ 334 __IM uint32_t SPEC_ADD5_TOP; /*!< 0x00001304 Specific address registers 5 ~ 36 doesn't present. Access to 335 the register returns AHB error. */ 336 __IM uint32_t RESERVED9[60]; 337 __IM uint32_t SPEC_ADD36_BOTTOM; /*!< 0x000013F8 Not presents. */ 338 __IM uint32_t SPEC_ADD36_TOP; /*!< 0x000013FC Not presents. */ 339 __IM uint32_t INT_Q1_STATUS; /*!< 0x00001400 Priority queue Interrupt Status Register */ 340 __IM uint32_t INT_Q2_STATUS; /*!< 0x00001404 Priority queue Interrupt Status Register */ 341 __IM uint32_t INT_Q3_STATUS; /*!< 0x00001408 int_q3_status to int_q15_status doesn't present. Access to the 342 register returns AHB error. */ 343 __IM uint32_t RESERVED10[11]; 344 __IM uint32_t INT_Q15_STATUS; /*!< 0x00001438 Not presents. */ 345 __IM uint32_t RESERVED11; 346 __IOM uint32_t TRANSMIT_Q1_PTR; /*!< 0x00001440 This register holds the start address of the transmit buffer 347 queue (transmit buffers descriptor list). The transmit buffer 348 queue base address register must be initialized before transmit 349 is started through bit 9 of the network control register. Once 350 transmission has started, any write to the transmit buffer queue 351 base address register is illegal and therefore ignored. Note 352 that due to clock boundary synchronization, it takes a maximum 353 of four pclk cycles from the writing of the transmit start bit 354 before the transmitter is active. Writing to the transmit buffer 355 queue base address register during this time may produce 356 unpredictable results. Reading this register returns the 357 location of the descriptor currently being accessed. Because the 358 DMA can store data for multiple frames at once, this may not 359 necessarily be pointing to the current frame being transmitted. 360 In terms of AMBA AXI operation, the transmit descriptors are 361 written to memory using a single 32bit AHB access. When the 362 datapath is configured as 64bit , the transmit descriptors 363 should be aligned at 64-bit boundaries and each pair of 32-bit 364 descriptors is read from memory using a single AXI access. */ 365 __IOM uint32_t TRANSMIT_Q2_PTR; /*!< 0x00001444 This register holds the start address of the transmit buffer 366 queue (transmit buffers descriptor list). The transmit buffer 367 queue base address register must be initialized before transmit 368 is started through bit 9 of the network control register. Once 369 transmission has started, any write to the transmit buffer queue 370 base address register is illegal and therefore ignored. Note 371 that due to clock boundary synchronization, it takes a maximum 372 of four pclk cycles from the writing of the transmit start bit 373 before the transmitter is active. Writing to the transmit buffer 374 queue base address register during this time may produce 375 unpredictable results. Reading this register returns the 376 location of the descriptor currently being accessed. Because the 377 DMA can store data for multiple frames at once, this may not 378 necessarily be pointing to the current frame being transmitted. 379 In terms of AMBA AXI operation, the transmit descriptors are 380 written to memory using a single 32bit AHB access. When the 381 datapath is configured as 64bit , the transmit descriptors 382 should be aligned at 64-bit boundaries and each pair of 32-bit 383 descriptors is read from memory using a single AXI access. */ 384 __IM uint32_t TRANSMIT_Q3_PTR; /*!< 0x00001448 transmit_q3_ptr to transmit_q15_ptr doesn't present. Access to 385 the register returns AHB error. */ 386 __IM uint32_t RESERVED12[11]; 387 __IM uint32_t TRANSMIT_Q15_PTR; /*!< 0x00001478 Not presents. */ 388 __IM uint32_t RESERVED13; 389 __IOM uint32_t RECEIVE_Q1_PTR; /*!< 0x00001480 This register holds the start address of the transmit buffer 390 queue (transmit buffers descriptor list). The transmit buffer 391 queue base address register must be initialized before transmit 392 is started through bit 9 of the network control register. Once 393 transmission has started, any write to the transmit buffer queue 394 base address register is illegal and therefore ignored. Note 395 that due to clock boundary synchronization, it takes a maximum 396 of four pclk cycles from the writing of the transmit start bit 397 before the transmitter is active. Writing to the transmit buffer 398 queue base address register during this time may produce 399 unpredictable results. Reading this register returns the 400 location of the descriptor currently being accessed. Because the 401 DMA can store data for multiple frames at once, this may not 402 necessarily be pointing to the current frame being transmitted. 403 In terms of AMBA AXI operation, the transmit descriptors are 404 written to memory using a single 32bit AHB access. When the 405 datapath is configured as 64bit , the transmit descriptors 406 should be aligned at 64-bit boundaries and each pair of 32-bit 407 descriptors is read from memory using a single AXI access. */ 408 __IOM uint32_t RECEIVE_Q2_PTR; /*!< 0x00001484 This register holds the start address of the transmit buffer 409 queue (transmit buffers descriptor list). The transmit buffer 410 queue base address register must be initialized before transmit 411 is started through bit 9 of the network control register. Once 412 transmission has started, any write to the transmit buffer queue 413 base address register is illegal and therefore ignored. Note 414 that due to clock boundary synchronization, it takes a maximum 415 of four pclk cycles from the writing of the transmit start bit 416 before the transmitter is active. Writing to the transmit buffer 417 queue base address register during this time may produce 418 unpredictable results. Reading this register returns the 419 location of the descriptor currently being accessed. Because the 420 DMA can store data for multiple frames at once, this may not 421 necessarily be pointing to the current frame being transmitted. 422 In terms of AMBA AXI operation, the transmit descriptors are 423 written to memory using a single 32bit AHB access. When the 424 datapath is configured as 64bit , the transmit descriptors 425 should be aligned at 64-bit boundaries and each pair of 32-bit 426 descriptors is read from memory using a single AXI access. */ 427 __IM uint32_t RECEIVE_Q3_PTR; /*!< 0x00001488 Not presents. Start address register doesn't present for queue3 428 ~ queue7. */ 429 __IM uint32_t RESERVED14[3]; 430 __IM uint32_t RECEIVE_Q7_PTR; /*!< 0x00001498 Not presents. */ 431 __IM uint32_t RESERVED15; 432 __IOM uint32_t DMA_RXBUF_SIZE_Q1; /*!< 0x000014A0 Receive Buffer queue 1 Size */ 433 __IOM uint32_t DMA_RXBUF_SIZE_Q2; /*!< 0x000014A4 Receive Buffer queue 2 Size */ 434 __IM uint32_t DMA_RXBUF_SIZE_Q3; /*!< 0x000014A8 dma_rxbuf_size_q3 to dma_rxbuf_size_q7 doesn't present. */ 435 __IM uint32_t RESERVED16[3]; 436 __IM uint32_t DMA_RXBUF_SIZE_Q7; /*!< 0x000014B8 Not presents. */ 437 __IOM uint32_t CBS_CONTROL; /*!< 0x000014BC The IdleSlope value is defined as the rate of change of credit 438 when a packet is waiting to be sent. This must not exceed the 439 portTransmitRate which is dependent on the speed of operation, 440 eg, portTranmsitRate. 1Gb/s = 32'h07735940 (125 Mbytes/s), 441 100Mb/sec = 32'h017D7840 (25 Mnibbles/s), 10Mb/sec = 442 32'h002625A0 (2.5 Mnibbles/s). If 50 percent of bandwidth was to 443 be allocated to a particular queue in 1Gb/sec mode then the 444 IdleSlope value for that queue would be calculated as 445 32'h07735940/2. Note that Credit-Based Shaping should be 446 disabled prior to updating the IdleSlope values. As another 447 example, for a 1722 audio packet with a payload of 6 samples per 448 channel, the packet size would be 7 (preamble) + 1 (SFD) + 50 449 (packet header) + 6x4x2(payload) + 4 (CRC) = 110 bytes. For a 450 rate of 8000 packets per second, the desired rate would 110 x 451 8000 bytes per second, so the programmed idleSlope value would 452 be 880000 for a 1Gb/s connection, or 1760000 for a 100Mb/s or 453 10Mbs connection. See Figure 6.3 in the IEEE 1722 standard. In 454 practice, the actual transmission rate will be vary slightly 455 from that calculated. In this case, the idleSlope value should 456 be recalibrated based on the variance between the measured and 457 expected rate, and in this case very accurate transmission rates 458 can be achieved. */ 459 __IOM uint32_t CBS_IDLESLOPE_Q_A; /*!< 0x000014C0 queue A is the highest priority queue. This would be queue 8 in 460 an 8 queue configuration. */ 461 __IOM uint32_t CBS_IDLESLOPE_Q_B; /*!< 0x000014C4 queue B is the 2nd highest priority queue. This would be queue 462 7 in an 8 queue configuration. */ 463 __IOM uint32_t UPPER_TX_Q_BASE_ADDR; /*!< 0x000014C8 Upper 32 bits of transmit buffer descriptor queue base address. */ 464 __IOM uint32_t TX_BD_CONTROL; /*!< 0x000014CC TX BD control register */ 465 __IOM uint32_t RX_BD_CONTROL; /*!< 0x000014D0 RX BD control register */ 466 __IOM uint32_t UPPER_RX_Q_BASE_ADDR; /*!< 0x000014D4 Upper 32 bits of receive buffer descriptor queue base address. */ 467 __IM uint32_t RESERVED17[2]; 468 __IOM uint32_t HIDDEN_REG0; /*!< 0x000014E0 Hidden registers defined in edma_defs.v '`define 469 gem_cbs_port_tx_rate_10m 12'h4e0 // 10M Port TX Rate *** HIDDEN 470 Register ***'. Default value of cbs related hidden registers 471 (0x14E0~0x14E8) are depicted in cbs_control register. */ 472 __IOM uint32_t HIDDEN_REG1; /*!< 0x000014E4 Hidden registers defined in edma_defs.v '`define 473 gem_cbs_port_tx_rate_100m 12'h4e4 // 100M Port TX Rate *** 474 HIDDEN Register ***' */ 475 __IOM uint32_t HIDDEN_REG2; /*!< 0x000014E8 Hidden registers defined in edma_defs.v '`define 476 gem_cbs_port_tx_rate_1g 12'h4e8 // 1G Port TX Rate *** HIDDEN 477 Register ***' */ 478 __IOM uint32_t HIDDEN_REG3; /*!< 0x000014EC Hidden registers defined in edma_defs.v '`define gem_wd_counter 479 12'h4ec // *** HIDDEN Register ***'. */ 480 __IM uint32_t RESERVED18[2]; 481 __IOM uint32_t HIDDEN_REG4; /*!< 0x000014F8 Hidden registers defined in edma_defs.v '`define 482 gem_axi_tx_full_threshold0 12'h4f8 // AXI full threshold setting 483 *** HIDDEN Register ***'. Note. When using AXI mode with a 484 single port ram ( gem_spram == 1) mode and a 32b dma bus width ( 485 gem_dma_bus_width == 32 or bits 22 to 21 of the network_config 486 register are set to 0) the AXI hidden registers (0x14F8 and 487 0x14FC) need to be updated (these registers are used for fine 488 tuning AXI dma bursts and normally should not be touched). */ 489 __IOM uint32_t HIDDEN_REG5; /*!< 0x000014FC Hidden registers defined in edma_defs.v '`define 490 gem_axi_tx_full_threshold1 12'h4fc // AXI full threshold setting 491 *** HIDDEN Register ***'. */ 492 __IOM uint32_t SCREENING_TYPE_1_REGISTER_0; /*!< 0x00001500 Screening type 1 registers are used to allocate up to 16 493 priority queues to received frames based on certain IP or UDP 494 fields of incoming frames. Firstly, when DS/TC match enable is 495 set (bit 28), the DS (Differentiated Services) field of the 496 received IPv4 header or TCfield (traffic class) of IPv6 headers 497 are matched against bits 11 to 4. Secondly, when UDP port match 498 enable is set (bit 29), the UDP Destination Port of the received 499 UDP frame is matched against bits 27 to 12. Both UDP and DS/TC 500 matching can be enabled simultaneously or individually. If a 501 match is successful, then the queue value programmed in bits 2 502 to 0 is allocated to the frame. The required number of Type 1 503 screening registers is configured in the gem defines file. Up to 504 16 type 1 screening registers have been allocated APB address 505 space between 0x500 and 0x53C. */ 506 __IOM uint32_t SCREENING_TYPE_1_REGISTER_1; /*!< 0x00001504 screening type 1 register 1, same as 507 screening_type_1_register_0 */ 508 __IOM uint32_t SCREENING_TYPE_1_REGISTER_2; /*!< 0x00001508 screening type 1 register 2, same as 509 screening_type_1_register_0 */ 510 __IOM uint32_t SCREENING_TYPE_1_REGISTER_3; /*!< 0x0000150C screening type 1 register 3, same as 511 screening_type_1_register_0 */ 512 __IOM uint32_t SCREENING_TYPE_1_REGISTER_4; /*!< 0x00001510 screening type 1 register 4, same as 513 screening_type_1_register_0 */ 514 __IOM uint32_t SCREENING_TYPE_1_REGISTER_5; /*!< 0x00001514 screening type 1 register 5, same as 515 screening_type_1_register_0 */ 516 __IOM uint32_t SCREENING_TYPE_1_REGISTER_6; /*!< 0x00001518 screening type 1 register 6, same as 517 screening_type_1_register_0 */ 518 __IOM uint32_t SCREENING_TYPE_1_REGISTER_7; /*!< 0x0000151C screening type 1 register 7, same as 519 screening_type_1_register_0 */ 520 __IOM uint32_t SCREENING_TYPE_1_REGISTER_8; /*!< 0x00001520 screening type 1 register 8, same as 521 screening_type_1_register_0 */ 522 __IOM uint32_t SCREENING_TYPE_1_REGISTER_9; /*!< 0x00001524 screening type 1 register 9, same as 523 screening_type_1_register_0 */ 524 __IOM uint32_t SCREENING_TYPE_1_REGISTER_10; /*!< 0x00001528 screening type 1 register 10, same as 525 screening_type_1_register_0 */ 526 __IOM uint32_t SCREENING_TYPE_1_REGISTER_11; /*!< 0x0000152C screening type 1 register 11, same as 527 screening_type_1_register_0 */ 528 __IOM uint32_t SCREENING_TYPE_1_REGISTER_12; /*!< 0x00001530 screening type 1 register 12, same as 529 screening_type_1_register_0 */ 530 __IOM uint32_t SCREENING_TYPE_1_REGISTER_13; /*!< 0x00001534 screening type 1 register 13, same as 531 screening_type_1_register_0 */ 532 __IOM uint32_t SCREENING_TYPE_1_REGISTER_14; /*!< 0x00001538 screening type 1 register 14, same as 533 screening_type_1_register_0 */ 534 __IOM uint32_t SCREENING_TYPE_1_REGISTER_15; /*!< 0x0000153C screening type 1 register 15, same as 535 screening_type_1_register_0 */ 536 __IOM uint32_t SCREENING_TYPE_2_REGISTER_0; /*!< 0x00001540 Screener Type 2 match registers operate independently of 537 screener type 1 registers and offer additional match 538 capabilities, extending the capabilities into vendor specific 539 protocols. */ 540 __IOM uint32_t SCREENING_TYPE_2_REGISTER_1; /*!< 0x00001544 screening type 2 register 1, same as 541 screening_type_2_register_0 */ 542 __IOM uint32_t SCREENING_TYPE_2_REGISTER_2; /*!< 0x00001548 screening type 2 register 2, same as 543 screening_type_2_register_0 */ 544 __IOM uint32_t SCREENING_TYPE_2_REGISTER_3; /*!< 0x0000154C screening type 2 register 3, same as 545 screening_type_2_register_0 */ 546 __IOM uint32_t SCREENING_TYPE_2_REGISTER_4; /*!< 0x00001550 screening type 2 register 4, same as 547 screening_type_2_register_0 */ 548 __IOM uint32_t SCREENING_TYPE_2_REGISTER_5; /*!< 0x00001554 screening type 2 register 5, same as 549 screening_type_2_register_0 */ 550 __IOM uint32_t SCREENING_TYPE_2_REGISTER_6; /*!< 0x00001558 screening type 2 register 6, same as 551 screening_type_2_register_0 */ 552 __IOM uint32_t SCREENING_TYPE_2_REGISTER_7; /*!< 0x0000155C screening type 2 register 7, same as 553 screening_type_2_register_0 */ 554 __IOM uint32_t SCREENING_TYPE_2_REGISTER_8; /*!< 0x00001560 screening type 2 register 8, same as 555 screening_type_2_register_0 */ 556 __IOM uint32_t SCREENING_TYPE_2_REGISTER_9; /*!< 0x00001564 screening type 2 register 9, same as 557 screening_type_2_register_0 */ 558 __IOM uint32_t SCREENING_TYPE_2_REGISTER_10; /*!< 0x00001568 screening type 2 register 10, same as 559 screening_type_2_register_0 */ 560 __IOM uint32_t SCREENING_TYPE_2_REGISTER_11; /*!< 0x0000156C screening type 2 register 11, same as 561 screening_type_2_register_0 */ 562 __IOM uint32_t SCREENING_TYPE_2_REGISTER_12; /*!< 0x00001570 screening type 2 register 12, same as 563 screening_type_2_register_0 */ 564 __IOM uint32_t SCREENING_TYPE_2_REGISTER_13; /*!< 0x00001574 screening type 2 register 13, same as 565 screening_type_2_register_0 */ 566 __IOM uint32_t SCREENING_TYPE_2_REGISTER_14; /*!< 0x00001578 screening type 2 register 14, same as 567 screening_type_2_register_0 */ 568 __IOM uint32_t SCREENING_TYPE_2_REGISTER_15; /*!< 0x0000157C screening type 2 register 15, same as 569 screening_type_2_register_0 */ 570 __IOM uint32_t TX_SCHED_CTRL; /*!< 0x00001580 This register controls the transmit scheduling algorithm the 571 user can select for each active transmit queue. By default all 572 queues are initialized to fixed priority, with the top indexed 573 queue having overall priority */ 574 __IM uint32_t RESERVED19[3]; 575 __IOM uint32_t BW_RATE_LIMIT_Q0TO3; /*!< 0x00001590 This register holds the DWRR weighting value or the ETS 576 bandwidth percentage value used by the transmit scheduler for 577 queues 0 to 3. */ 578 __IOM uint32_t BW_RATE_LIMIT_Q4TO7; /*!< 0x00001594 Not presents. MXETH has only 3 queues. Access to the register 579 returns AHB error. */ 580 __IM uint32_t BW_RATE_LIMIT_Q8TO11; /*!< 0x00001598 Not presents. MXETH has only 3 queues. Access to the register 581 returns AHB error. */ 582 __IM uint32_t BW_RATE_LIMIT_Q12TO15; /*!< 0x0000159C Not presents. MXETH has only 3 queues. Access to the register 583 returns AHB error. */ 584 __IOM uint32_t TX_Q_SEG_ALLOC_Q0TO7; /*!< 0x000015A0 This register allows the user to distribute the Transmit SRAM 585 used by the DMA across the priority queues, for queues 0 to 7. 586 The SRAM itself is split into a number of evenly sized segments 587 (this is defined in the verilog configuration defs file - for 588 the configuration used to generate this register description, 589 the total number of segments was set to '16'). Those segments 590 can then be freely distributed across the active queues, in 591 powers of 2. I.e. a value of 0 would mean 1 segment has been 592 allocated to the queue. A value of 1 would mean 2 segments, a 593 value of 2 means 4 segments and so on. The reset values of these 594 registers are defined in the configuration defs file. */ 595 __IM uint32_t TX_Q_SEG_ALLOC_Q8TO15; /*!< 0x000015A4 Not presents. Access to the register returns AHB error. */ 596 __IM uint32_t RESERVED20[6]; 597 __IM uint32_t RECEIVE_Q8_PTR; /*!< 0x000015C0 receive_q8_ptr to receive_q15_ptr doesn't present. Access to 598 the register returns AHB error. */ 599 __IM uint32_t RESERVED21[6]; 600 __IM uint32_t RECEIVE_Q15_PTR; /*!< 0x000015DC Not presents. */ 601 __IM uint32_t DMA_RXBUF_SIZE_Q8; /*!< 0x000015E0 dma_rxbuf_size_q8 to dma_rxbuf_size_q15 doesn't present. Access 602 to the register returns AHB error. */ 603 __IM uint32_t RESERVED22[6]; 604 __IM uint32_t DMA_RXBUF_SIZE_Q15; /*!< 0x000015FC Not presents. */ 605 __OM uint32_t INT_Q1_ENABLE; /*!< 0x00001600 At reset all interrupts are disabled. Writing a one to the 606 relevant bit location enables the required interrupt. This 607 register is write only and when read will return zero. */ 608 __OM uint32_t INT_Q2_ENABLE; /*!< 0x00001604 At reset all interrupts are disabled. Writing a one to the 609 relevant bit location enables the required interrupt. This 610 register is write only and when read will return zero. */ 611 __IM uint32_t INT_Q3_ENABLE; /*!< 0x00001608 int_q3_enable to int_q7_enable doesn't present. Access to the 612 register returns AHB error. */ 613 __IM uint32_t RESERVED23[3]; 614 __IM uint32_t INT_Q7_ENABLE; /*!< 0x00001618 Not presents. */ 615 __IM uint32_t RESERVED24; 616 __OM uint32_t INT_Q1_DISABLE; /*!< 0x00001620 Writing a 1 to the relevant bit location disables that 617 particular interrupt. This register is write only and when read 618 will return zero. */ 619 __OM uint32_t INT_Q2_DISABLE; /*!< 0x00001624 Writing a 1 to the relevant bit location disables that 620 particular interrupt. This register is write only and when read 621 will return zero. */ 622 __IM uint32_t INT_Q3_DISABLE; /*!< 0x00001628 int_q3_disable to int_q7_disable doesn't present. Access to the 623 register returns AHB error. */ 624 __IM uint32_t RESERVED25[3]; 625 __IM uint32_t INT_Q7_DISABLE; /*!< 0x00001638 Not presents. */ 626 __IM uint32_t RESERVED26; 627 __IM uint32_t INT_Q1_MASK; /*!< 0x00001640 The interrupt mask register is a read only register indicating 628 which interrupts are masked. All bits are set at reset and can 629 be reset individually by writing to the interrupt enable 630 register or set individually by writing to the interrupt disable 631 register. Having separate address locations for enable and 632 disable saves the need for performing a read modify write when 633 updating the interrupt mask register. For test purposes there is 634 a write-only function to this register that allows the bits in 635 the interrupt status register to be set or cleared, regardless 636 of the state of the mask register. */ 637 __IM uint32_t INT_Q2_MASK; /*!< 0x00001644 The interrupt mask register is a read only register indicating 638 which interrupts are masked. All bits are set at reset and can 639 be reset individually by writing to the interrupt enable 640 register or set individually by writing to the interrupt disable 641 register. Having separate address locations for enable and 642 disable saves the need for performing a read modify write when 643 updating the interrupt mask register. For test purposes there is 644 a write-only function to this register that allows the bits in 645 the interrupt status register to be set or cleared, regardless 646 of the state of the mask register. */ 647 __IM uint32_t INT_Q3_MASK; /*!< 0x00001648 int_q3_mask to int_q7_mask doesn't present. Access to the 648 register returns AHB error. */ 649 __IM uint32_t RESERVED27[3]; 650 __IM uint32_t INT_Q7_MASK; /*!< 0x00001658 Not presents. */ 651 __IM uint32_t RESERVED28; 652 __IM uint32_t INT_Q8_ENABLE; /*!< 0x00001660 int_q8_enable to int_q15_enable doesn't present. Access to the 653 register returns AHB error. */ 654 __IM uint32_t RESERVED29[6]; 655 __IM uint32_t INT_Q15_ENABLE; /*!< 0x0000167C Not presents. */ 656 __IM uint32_t INT_Q8_DISABLE; /*!< 0x00001680 int_q8_disable to int_q15_disable doesn't present. Access to 657 the register returns AHB error. */ 658 __IM uint32_t RESERVED30[6]; 659 __IM uint32_t INT_Q15_DISABLE; /*!< 0x0000169C Not presents. */ 660 __IM uint32_t INT_Q8_MASK; /*!< 0x000016A0 int_q8_mask to int_q15_mask doesn't present. Access to the 661 register returns AHB error. */ 662 __IM uint32_t RESERVED31[6]; 663 __IM uint32_t INT_Q15_MASK; /*!< 0x000016BC Not presents. */ 664 __IM uint32_t RESERVED32[8]; 665 __IOM uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_0; /*!< 0x000016E0 Ethertype Register */ 666 __IOM uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_1; /*!< 0x000016E4 Ethertype Register */ 667 __IOM uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_2; /*!< 0x000016E8 Ethertype Register */ 668 __IOM uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_3; /*!< 0x000016EC Ethertype Register */ 669 __IOM uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_4; /*!< 0x000016F0 Ethertype Register */ 670 __IOM uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_5; /*!< 0x000016F4 Ethertype Register */ 671 __IOM uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_6; /*!< 0x000016F8 Ethertype Register */ 672 __IOM uint32_t SCREENING_TYPE_2_ETHERTYPE_REG_7; /*!< 0x000016FC Ethertype Register */ 673 __IOM uint32_t TYPE2_COMPARE_0_WORD_0; /*!< 0x00001700 'Compare A, B and C fields of the screener type 2 match 674 register are pointers to a pool of up to 32 compare registers. 675 If enabled the compare is true if the data at the OFFSET into 676 the frame, ANDed with the MASK Value if the mask is enabled, is 677 equal to the COMPARE Value. Either a 16 bit comparison or a 32 678 bit comparison is done. This selection is made via the 679 associated compare word1 register bit 9. If a 16 bit comparison 680 is selected, then a 16 bit mask is also available to the user to 681 select which bits should be compared. If the 32 bit compare 682 option is selected, then no mask is available. The byte at the 683 OFFSET number of bytes from the index start is compared thru 684 bits 7 to 0 of the configured VALUE. The byte at the OFFSET 685 number of bytes + 1 from the index start is compared thru bits 686 15 to 8 of the configured VALUE and so on. The OFFSET can be 687 configured to be from 0 to 127 bytes from either the start of 688 the frame, the byte following the therType field (last EtherType 689 in the header if the frame is VLAN tagged), the byte following 690 the IP header (IPv4 or IPv6) or from the byte following the 691 start of the TCP/UDP header. The required number of Type 2 692 screening registers up to a maximum of 32 is configurable in the 693 gem defines file and have been allocated APB address space 694 between 0x700 and 0x7fc. Note. when using RX Partial Store and 695 Forward mode and priority queues, the frame offset must be less 696 than the Partial Store and Forward watermark. If the offset is 697 higher than the watermark value it's not possible to identify 698 the priority queue before the frame is sent to the AMBA 699 interface, and an incorrect priority queue may be used. ' */ 700 __IOM uint32_t TYPE2_COMPARE_0_WORD_1; /*!< 0x00001704 'Type2 Compare Word 1' */ 701 __IOM uint32_t TYPE2_COMPARE_1_WORD_0; /*!< 0x00001708 same as type2_compare_0_word_0 */ 702 __IOM uint32_t TYPE2_COMPARE_1_WORD_1; /*!< 0x0000170C same as type2_compare_0_word_1 */ 703 __IOM uint32_t TYPE2_COMPARE_2_WORD_0; /*!< 0x00001710 same as type2_compare_0_word_0 */ 704 __IOM uint32_t TYPE2_COMPARE_2_WORD_1; /*!< 0x00001714 same as type2_compare_0_word_1 */ 705 __IOM uint32_t TYPE2_COMPARE_3_WORD_0; /*!< 0x00001718 same as type2_compare_0_word_0 */ 706 __IOM uint32_t TYPE2_COMPARE_3_WORD_1; /*!< 0x0000171C same as type2_compare_0_word_1 */ 707 __IOM uint32_t TYPE2_COMPARE_4_WORD_0; /*!< 0x00001720 same as type2_compare_0_word_0 */ 708 __IOM uint32_t TYPE2_COMPARE_4_WORD_1; /*!< 0x00001724 same as type2_compare_0_word_1 */ 709 __IOM uint32_t TYPE2_COMPARE_5_WORD_0; /*!< 0x00001728 same as type2_compare_0_word_0 */ 710 __IOM uint32_t TYPE2_COMPARE_5_WORD_1; /*!< 0x0000172C same as type2_compare_0_word_1 */ 711 __IOM uint32_t TYPE2_COMPARE_6_WORD_0; /*!< 0x00001730 same as type2_compare_0_word_0 */ 712 __IOM uint32_t TYPE2_COMPARE_6_WORD_1; /*!< 0x00001734 same as type2_compare_0_word_1 */ 713 __IOM uint32_t TYPE2_COMPARE_7_WORD_0; /*!< 0x00001738 same as type2_compare_0_word_0 */ 714 __IOM uint32_t TYPE2_COMPARE_7_WORD_1; /*!< 0x0000173C same as type2_compare_0_word_1 */ 715 __IOM uint32_t TYPE2_COMPARE_8_WORD_0; /*!< 0x00001740 same as type2_compare_0_word_0 */ 716 __IOM uint32_t TYPE2_COMPARE_8_WORD_1; /*!< 0x00001744 same as type2_compare_0_word_1 */ 717 __IOM uint32_t TYPE2_COMPARE_9_WORD_0; /*!< 0x00001748 same as type2_compare_0_word_0 */ 718 __IOM uint32_t TYPE2_COMPARE_9_WORD_1; /*!< 0x0000174C same as type2_compare_0_word_1 */ 719 __IOM uint32_t TYPE2_COMPARE_10_WORD_0; /*!< 0x00001750 same as type2_compare_0_word_0 */ 720 __IOM uint32_t TYPE2_COMPARE_10_WORD_1; /*!< 0x00001754 same as type2_compare_0_word_1 */ 721 __IOM uint32_t TYPE2_COMPARE_11_WORD_0; /*!< 0x00001758 same as type2_compare_0_word_0 */ 722 __IOM uint32_t TYPE2_COMPARE_11_WORD_1; /*!< 0x0000175C same as type2_compare_0_word_1 */ 723 __IOM uint32_t TYPE2_COMPARE_12_WORD_0; /*!< 0x00001760 same as type2_compare_0_word_0 */ 724 __IOM uint32_t TYPE2_COMPARE_12_WORD_1; /*!< 0x00001764 same as type2_compare_0_word_1 */ 725 __IOM uint32_t TYPE2_COMPARE_13_WORD_0; /*!< 0x00001768 same as type2_compare_0_word_0 */ 726 __IOM uint32_t TYPE2_COMPARE_13_WORD_1; /*!< 0x0000176C same as type2_compare_0_word_1 */ 727 __IOM uint32_t TYPE2_COMPARE_14_WORD_0; /*!< 0x00001770 same as type2_compare_0_word_0 */ 728 __IOM uint32_t TYPE2_COMPARE_14_WORD_1; /*!< 0x00001774 same as type2_compare_0_word_1 */ 729 __IOM uint32_t TYPE2_COMPARE_15_WORD_0; /*!< 0x00001778 same as type2_compare_0_word_0 */ 730 __IOM uint32_t TYPE2_COMPARE_15_WORD_1; /*!< 0x0000177C same as type2_compare_0_word_1 */ 731 __IOM uint32_t TYPE2_COMPARE_16_WORD_0; /*!< 0x00001780 same as type2_compare_0_word_0 */ 732 __IOM uint32_t TYPE2_COMPARE_16_WORD_1; /*!< 0x00001784 same as type2_compare_0_word_1 */ 733 __IOM uint32_t TYPE2_COMPARE_17_WORD_0; /*!< 0x00001788 same as type2_compare_0_word_0 */ 734 __IOM uint32_t TYPE2_COMPARE_17_WORD_1; /*!< 0x0000178C same as type2_compare_0_word_1 */ 735 __IOM uint32_t TYPE2_COMPARE_18_WORD_0; /*!< 0x00001790 same as type2_compare_0_word_0 */ 736 __IOM uint32_t TYPE2_COMPARE_18_WORD_1; /*!< 0x00001794 same as type2_compare_0_word_1 */ 737 __IOM uint32_t TYPE2_COMPARE_19_WORD_0; /*!< 0x00001798 same as type2_compare_0_word_0 */ 738 __IOM uint32_t TYPE2_COMPARE_19_WORD_1; /*!< 0x0000179C same as type2_compare_0_word_1 */ 739 __IOM uint32_t TYPE2_COMPARE_20_WORD_0; /*!< 0x000017A0 same as type2_compare_0_word_0 */ 740 __IOM uint32_t TYPE2_COMPARE_20_WORD_1; /*!< 0x000017A4 same as type2_compare_0_word_1 */ 741 __IOM uint32_t TYPE2_COMPARE_21_WORD_0; /*!< 0x000017A8 same as type2_compare_0_word_0 */ 742 __IOM uint32_t TYPE2_COMPARE_21_WORD_1; /*!< 0x000017AC same as type2_compare_0_word_1 */ 743 __IOM uint32_t TYPE2_COMPARE_22_WORD_0; /*!< 0x000017B0 same as type2_compare_0_word_0 */ 744 __IOM uint32_t TYPE2_COMPARE_22_WORD_1; /*!< 0x000017B4 same as type2_compare_0_word_1 */ 745 __IOM uint32_t TYPE2_COMPARE_23_WORD_0; /*!< 0x000017B8 same as type2_compare_0_word_0 */ 746 __IOM uint32_t TYPE2_COMPARE_23_WORD_1; /*!< 0x000017BC same as type2_compare_0_word_1 */ 747 __IOM uint32_t TYPE2_COMPARE_24_WORD_0; /*!< 0x000017C0 same as type2_compare_0_word_0 */ 748 __IOM uint32_t TYPE2_COMPARE_24_WORD_1; /*!< 0x000017C4 same as type2_compare_0_word_1 */ 749 __IOM uint32_t TYPE2_COMPARE_25_WORD_0; /*!< 0x000017C8 same as type2_compare_0_word_0 */ 750 __IOM uint32_t TYPE2_COMPARE_25_WORD_1; /*!< 0x000017CC same as type2_compare_0_word_1 */ 751 __IOM uint32_t TYPE2_COMPARE_26_WORD_0; /*!< 0x000017D0 same as type2_compare_0_word_0 */ 752 __IOM uint32_t TYPE2_COMPARE_26_WORD_1; /*!< 0x000017D4 same as type2_compare_0_word_1 */ 753 __IOM uint32_t TYPE2_COMPARE_27_WORD_0; /*!< 0x000017D8 same as type2_compare_0_word_0 */ 754 __IOM uint32_t TYPE2_COMPARE_27_WORD_1; /*!< 0x000017DC same as type2_compare_0_word_1 */ 755 __IOM uint32_t TYPE2_COMPARE_28_WORD_0; /*!< 0x000017E0 same as type2_compare_0_word_0 */ 756 __IOM uint32_t TYPE2_COMPARE_28_WORD_1; /*!< 0x000017E4 same as type2_compare_0_word_1 */ 757 __IOM uint32_t TYPE2_COMPARE_29_WORD_0; /*!< 0x000017E8 same as type2_compare_0_word_0 */ 758 __IOM uint32_t TYPE2_COMPARE_29_WORD_1; /*!< 0x000017EC same as type2_compare_0_word_1 */ 759 __IOM uint32_t TYPE2_COMPARE_30_WORD_0; /*!< 0x000017F0 same as type2_compare_0_word_0 */ 760 __IOM uint32_t TYPE2_COMPARE_30_WORD_1; /*!< 0x000017F4 same as type2_compare_0_word_1 */ 761 __IOM uint32_t TYPE2_COMPARE_31_WORD_0; /*!< 0x000017F8 same as type2_compare_0_word_0 */ 762 __IOM uint32_t TYPE2_COMPARE_31_WORD_1; /*!< 0x000017FC same as type2_compare_0_word_1 */ 763 } ETH_Type; /*!< Size = 6144 (0x1800) */ 764 765 766 /* ETH.CTL */ 767 #define ETH_CTL_ETH_MODE_Pos 0UL 768 #define ETH_CTL_ETH_MODE_Msk 0x3UL 769 #define ETH_CTL_REFCLK_SRC_SEL_Pos 2UL 770 #define ETH_CTL_REFCLK_SRC_SEL_Msk 0x4UL 771 #define ETH_CTL_REFCLK_DIV_Pos 8UL 772 #define ETH_CTL_REFCLK_DIV_Msk 0xFF00UL 773 #define ETH_CTL_ENABLED_Pos 31UL 774 #define ETH_CTL_ENABLED_Msk 0x80000000UL 775 /* ETH.STATUS */ 776 #define ETH_STATUS_PFC_NEGOTIATE_Pos 0UL 777 #define ETH_STATUS_PFC_NEGOTIATE_Msk 0x1UL 778 #define ETH_STATUS_RX_PFC_PAUSED_Pos 8UL 779 #define ETH_STATUS_RX_PFC_PAUSED_Msk 0xFF00UL 780 /* ETH.NETWORK_CONTROL */ 781 #define ETH_NETWORK_CONTROL_LOOPBACK_Pos 0UL 782 #define ETH_NETWORK_CONTROL_LOOPBACK_Msk 0x1UL 783 #define ETH_NETWORK_CONTROL_LOOPBACK_LOCAL_Pos 1UL 784 #define ETH_NETWORK_CONTROL_LOOPBACK_LOCAL_Msk 0x2UL 785 #define ETH_NETWORK_CONTROL_ENABLE_RECEIVE_Pos 2UL 786 #define ETH_NETWORK_CONTROL_ENABLE_RECEIVE_Msk 0x4UL 787 #define ETH_NETWORK_CONTROL_ENABLE_TRANSMIT_Pos 3UL 788 #define ETH_NETWORK_CONTROL_ENABLE_TRANSMIT_Msk 0x8UL 789 #define ETH_NETWORK_CONTROL_MAN_PORT_EN_Pos 4UL 790 #define ETH_NETWORK_CONTROL_MAN_PORT_EN_Msk 0x10UL 791 #define ETH_NETWORK_CONTROL_CLEAR_ALL_STATS_REGS_Pos 5UL 792 #define ETH_NETWORK_CONTROL_CLEAR_ALL_STATS_REGS_Msk 0x20UL 793 #define ETH_NETWORK_CONTROL_INC_ALL_STATS_REGS_Pos 6UL 794 #define ETH_NETWORK_CONTROL_INC_ALL_STATS_REGS_Msk 0x40UL 795 #define ETH_NETWORK_CONTROL_STATS_WRITE_EN_Pos 7UL 796 #define ETH_NETWORK_CONTROL_STATS_WRITE_EN_Msk 0x80UL 797 #define ETH_NETWORK_CONTROL_BACK_PRESSURE_Pos 8UL 798 #define ETH_NETWORK_CONTROL_BACK_PRESSURE_Msk 0x100UL 799 #define ETH_NETWORK_CONTROL_TX_START_PCLK_Pos 9UL 800 #define ETH_NETWORK_CONTROL_TX_START_PCLK_Msk 0x200UL 801 #define ETH_NETWORK_CONTROL_TX_HALT_PCLK_Pos 10UL 802 #define ETH_NETWORK_CONTROL_TX_HALT_PCLK_Msk 0x400UL 803 #define ETH_NETWORK_CONTROL_TX_PAUSE_FRAME_REQ_Pos 11UL 804 #define ETH_NETWORK_CONTROL_TX_PAUSE_FRAME_REQ_Msk 0x800UL 805 #define ETH_NETWORK_CONTROL_TX_PAUSE_FRAME_ZERO_Pos 12UL 806 #define ETH_NETWORK_CONTROL_TX_PAUSE_FRAME_ZERO_Msk 0x1000UL 807 #define ETH_NETWORK_CONTROL_REMOVED_13_Pos 13UL 808 #define ETH_NETWORK_CONTROL_REMOVED_13_Msk 0x2000UL 809 #define ETH_NETWORK_CONTROL_REMOVED_14_Pos 14UL 810 #define ETH_NETWORK_CONTROL_REMOVED_14_Msk 0x4000UL 811 #define ETH_NETWORK_CONTROL_STORE_RX_TS_Pos 15UL 812 #define ETH_NETWORK_CONTROL_STORE_RX_TS_Msk 0x8000UL 813 #define ETH_NETWORK_CONTROL_PFC_ENABLE_Pos 16UL 814 #define ETH_NETWORK_CONTROL_PFC_ENABLE_Msk 0x10000UL 815 #define ETH_NETWORK_CONTROL_TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME_Pos 17UL 816 #define ETH_NETWORK_CONTROL_TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME_Msk 0x20000UL 817 #define ETH_NETWORK_CONTROL_FLUSH_RX_PKT_PCLK_Pos 18UL 818 #define ETH_NETWORK_CONTROL_FLUSH_RX_PKT_PCLK_Msk 0x40000UL 819 #define ETH_NETWORK_CONTROL_TX_LPI_EN_Pos 19UL 820 #define ETH_NETWORK_CONTROL_TX_LPI_EN_Msk 0x80000UL 821 #define ETH_NETWORK_CONTROL_PTP_UNICAST_ENA_Pos 20UL 822 #define ETH_NETWORK_CONTROL_PTP_UNICAST_ENA_Msk 0x100000UL 823 #define ETH_NETWORK_CONTROL_ALT_SGMII_MODE_Pos 21UL 824 #define ETH_NETWORK_CONTROL_ALT_SGMII_MODE_Msk 0x200000UL 825 #define ETH_NETWORK_CONTROL_STORE_UDP_OFFSET_Pos 22UL 826 #define ETH_NETWORK_CONTROL_STORE_UDP_OFFSET_Msk 0x400000UL 827 #define ETH_NETWORK_CONTROL_EXT_TSU_PORT_ENABLE_Pos 23UL 828 #define ETH_NETWORK_CONTROL_EXT_TSU_PORT_ENABLE_Msk 0x800000UL 829 #define ETH_NETWORK_CONTROL_ONE_STEP_SYNC_MODE_Pos 24UL 830 #define ETH_NETWORK_CONTROL_ONE_STEP_SYNC_MODE_Msk 0x1000000UL 831 #define ETH_NETWORK_CONTROL_PFC_CTRL_Pos 25UL 832 #define ETH_NETWORK_CONTROL_PFC_CTRL_Msk 0x2000000UL 833 #define ETH_NETWORK_CONTROL_EXT_RXQ_SEL_EN_Pos 26UL 834 #define ETH_NETWORK_CONTROL_EXT_RXQ_SEL_EN_Msk 0x4000000UL 835 #define ETH_NETWORK_CONTROL_OSS_CORRECTION_FIELD_Pos 27UL 836 #define ETH_NETWORK_CONTROL_OSS_CORRECTION_FIELD_Msk 0x8000000UL 837 #define ETH_NETWORK_CONTROL_SEL_MII_ON_RGMII_Pos 28UL 838 #define ETH_NETWORK_CONTROL_SEL_MII_ON_RGMII_Msk 0x10000000UL 839 #define ETH_NETWORK_CONTROL_TWO_PT_FIVE_GIG_Pos 29UL 840 #define ETH_NETWORK_CONTROL_TWO_PT_FIVE_GIG_Msk 0x20000000UL 841 #define ETH_NETWORK_CONTROL_IFG_EATS_QAV_CREDIT_Pos 30UL 842 #define ETH_NETWORK_CONTROL_IFG_EATS_QAV_CREDIT_Msk 0x40000000UL 843 #define ETH_NETWORK_CONTROL_EXT_RXQ_RESERVED_31_Pos 31UL 844 #define ETH_NETWORK_CONTROL_EXT_RXQ_RESERVED_31_Msk 0x80000000UL 845 /* ETH.NETWORK_CONFIG */ 846 #define ETH_NETWORK_CONFIG_SPEED_Pos 0UL 847 #define ETH_NETWORK_CONFIG_SPEED_Msk 0x1UL 848 #define ETH_NETWORK_CONFIG_FULL_DUPLEX_Pos 1UL 849 #define ETH_NETWORK_CONFIG_FULL_DUPLEX_Msk 0x2UL 850 #define ETH_NETWORK_CONFIG_DISCARD_NON_VLAN_FRAMES_Pos 2UL 851 #define ETH_NETWORK_CONFIG_DISCARD_NON_VLAN_FRAMES_Msk 0x4UL 852 #define ETH_NETWORK_CONFIG_JUMBO_FRAMES_Pos 3UL 853 #define ETH_NETWORK_CONFIG_JUMBO_FRAMES_Msk 0x8UL 854 #define ETH_NETWORK_CONFIG_COPY_ALL_FRAMES_Pos 4UL 855 #define ETH_NETWORK_CONFIG_COPY_ALL_FRAMES_Msk 0x10UL 856 #define ETH_NETWORK_CONFIG_NO_BROADCAST_Pos 5UL 857 #define ETH_NETWORK_CONFIG_NO_BROADCAST_Msk 0x20UL 858 #define ETH_NETWORK_CONFIG_MULTICAST_HASH_ENABLE_Pos 6UL 859 #define ETH_NETWORK_CONFIG_MULTICAST_HASH_ENABLE_Msk 0x40UL 860 #define ETH_NETWORK_CONFIG_UNICAST_HASH_ENABLE_Pos 7UL 861 #define ETH_NETWORK_CONFIG_UNICAST_HASH_ENABLE_Msk 0x80UL 862 #define ETH_NETWORK_CONFIG_RECEIVE_1536_BYTE_FRAMES_Pos 8UL 863 #define ETH_NETWORK_CONFIG_RECEIVE_1536_BYTE_FRAMES_Msk 0x100UL 864 #define ETH_NETWORK_CONFIG_EXTERNAL_ADDRESS_MATCH_ENABLE_Pos 9UL 865 #define ETH_NETWORK_CONFIG_EXTERNAL_ADDRESS_MATCH_ENABLE_Msk 0x200UL 866 #define ETH_NETWORK_CONFIG_GIGABIT_MODE_ENABLE_Pos 10UL 867 #define ETH_NETWORK_CONFIG_GIGABIT_MODE_ENABLE_Msk 0x400UL 868 #define ETH_NETWORK_CONFIG_PCS_SELECT_Pos 11UL 869 #define ETH_NETWORK_CONFIG_PCS_SELECT_Msk 0x800UL 870 #define ETH_NETWORK_CONFIG_RETRY_TEST_Pos 12UL 871 #define ETH_NETWORK_CONFIG_RETRY_TEST_Msk 0x1000UL 872 #define ETH_NETWORK_CONFIG_PAUSE_ENABLE_Pos 13UL 873 #define ETH_NETWORK_CONFIG_PAUSE_ENABLE_Msk 0x2000UL 874 #define ETH_NETWORK_CONFIG_RECEIVE_BUFFER_OFFSET_Pos 14UL 875 #define ETH_NETWORK_CONFIG_RECEIVE_BUFFER_OFFSET_Msk 0xC000UL 876 #define ETH_NETWORK_CONFIG_LENGTH_FIELD_ERROR_FRAME_DISCARD_Pos 16UL 877 #define ETH_NETWORK_CONFIG_LENGTH_FIELD_ERROR_FRAME_DISCARD_Msk 0x10000UL 878 #define ETH_NETWORK_CONFIG_FCS_REMOVE_Pos 17UL 879 #define ETH_NETWORK_CONFIG_FCS_REMOVE_Msk 0x20000UL 880 #define ETH_NETWORK_CONFIG_MDC_CLOCK_DIVISION_Pos 18UL 881 #define ETH_NETWORK_CONFIG_MDC_CLOCK_DIVISION_Msk 0x1C0000UL 882 #define ETH_NETWORK_CONFIG_DATA_BUS_WIDTH_Pos 21UL 883 #define ETH_NETWORK_CONFIG_DATA_BUS_WIDTH_Msk 0x600000UL 884 #define ETH_NETWORK_CONFIG_DISABLE_COPY_OF_PAUSE_FRAMES_Pos 23UL 885 #define ETH_NETWORK_CONFIG_DISABLE_COPY_OF_PAUSE_FRAMES_Msk 0x800000UL 886 #define ETH_NETWORK_CONFIG_RECEIVE_CHECKSUM_OFFLOAD_ENABLE_Pos 24UL 887 #define ETH_NETWORK_CONFIG_RECEIVE_CHECKSUM_OFFLOAD_ENABLE_Msk 0x1000000UL 888 #define ETH_NETWORK_CONFIG_EN_HALF_DUPLEX_RX_Pos 25UL 889 #define ETH_NETWORK_CONFIG_EN_HALF_DUPLEX_RX_Msk 0x2000000UL 890 #define ETH_NETWORK_CONFIG_IGNORE_RX_FCS_Pos 26UL 891 #define ETH_NETWORK_CONFIG_IGNORE_RX_FCS_Msk 0x4000000UL 892 #define ETH_NETWORK_CONFIG_SGMII_MODE_ENABLE_Pos 27UL 893 #define ETH_NETWORK_CONFIG_SGMII_MODE_ENABLE_Msk 0x8000000UL 894 #define ETH_NETWORK_CONFIG_IPG_STRETCH_ENABLE_Pos 28UL 895 #define ETH_NETWORK_CONFIG_IPG_STRETCH_ENABLE_Msk 0x10000000UL 896 #define ETH_NETWORK_CONFIG_NSP_CHANGE_Pos 29UL 897 #define ETH_NETWORK_CONFIG_NSP_CHANGE_Msk 0x20000000UL 898 #define ETH_NETWORK_CONFIG_IGNORE_IPG_RX_ER_Pos 30UL 899 #define ETH_NETWORK_CONFIG_IGNORE_IPG_RX_ER_Msk 0x40000000UL 900 #define ETH_NETWORK_CONFIG_RESERVED_31_Pos 31UL 901 #define ETH_NETWORK_CONFIG_RESERVED_31_Msk 0x80000000UL 902 /* ETH.NETWORK_STATUS */ 903 #define ETH_NETWORK_STATUS_PCS_LINK_STATE_Pos 0UL 904 #define ETH_NETWORK_STATUS_PCS_LINK_STATE_Msk 0x1UL 905 #define ETH_NETWORK_STATUS_MDIO_IN_Pos 1UL 906 #define ETH_NETWORK_STATUS_MDIO_IN_Msk 0x2UL 907 #define ETH_NETWORK_STATUS_MAN_DONE_Pos 2UL 908 #define ETH_NETWORK_STATUS_MAN_DONE_Msk 0x4UL 909 #define ETH_NETWORK_STATUS_MAC_FULL_DUPLEX_Pos 3UL 910 #define ETH_NETWORK_STATUS_MAC_FULL_DUPLEX_Msk 0x8UL 911 #define ETH_NETWORK_STATUS_REMOVED_5_4_Pos 4UL 912 #define ETH_NETWORK_STATUS_REMOVED_5_4_Msk 0x30UL 913 #define ETH_NETWORK_STATUS_PFC_NEGOTIATE_PCLK_Pos 6UL 914 #define ETH_NETWORK_STATUS_PFC_NEGOTIATE_PCLK_Msk 0x40UL 915 #define ETH_NETWORK_STATUS_LPI_INDICATE_PCLK_Pos 7UL 916 #define ETH_NETWORK_STATUS_LPI_INDICATE_PCLK_Msk 0x80UL 917 /* ETH.USER_IO_REGISTER */ 918 #define ETH_USER_IO_REGISTER_RESERVED_31_0_Pos 0UL 919 #define ETH_USER_IO_REGISTER_RESERVED_31_0_Msk 0xFFFFFFFFUL 920 /* ETH.DMA_CONFIG */ 921 #define ETH_DMA_CONFIG_AMBA_BURST_LENGTH_Pos 0UL 922 #define ETH_DMA_CONFIG_AMBA_BURST_LENGTH_Msk 0x1FUL 923 #define ETH_DMA_CONFIG_HDR_DATA_SPLITTING_EN_Pos 5UL 924 #define ETH_DMA_CONFIG_HDR_DATA_SPLITTING_EN_Msk 0x20UL 925 #define ETH_DMA_CONFIG_ENDIAN_SWAP_MANAGEMENT_Pos 6UL 926 #define ETH_DMA_CONFIG_ENDIAN_SWAP_MANAGEMENT_Msk 0x40UL 927 #define ETH_DMA_CONFIG_ENDIAN_SWAP_PACKET_Pos 7UL 928 #define ETH_DMA_CONFIG_ENDIAN_SWAP_PACKET_Msk 0x80UL 929 #define ETH_DMA_CONFIG_RX_PBUF_SIZE_Pos 8UL 930 #define ETH_DMA_CONFIG_RX_PBUF_SIZE_Msk 0x300UL 931 #define ETH_DMA_CONFIG_TX_PBUF_SIZE_Pos 10UL 932 #define ETH_DMA_CONFIG_TX_PBUF_SIZE_Msk 0x400UL 933 #define ETH_DMA_CONFIG_TX_PBUF_TCP_EN_Pos 11UL 934 #define ETH_DMA_CONFIG_TX_PBUF_TCP_EN_Msk 0x800UL 935 #define ETH_DMA_CONFIG_INFINITE_LAST_DBUF_SIZE_EN_Pos 12UL 936 #define ETH_DMA_CONFIG_INFINITE_LAST_DBUF_SIZE_EN_Msk 0x1000UL 937 #define ETH_DMA_CONFIG_CRC_ERROR_REPORT_Pos 13UL 938 #define ETH_DMA_CONFIG_CRC_ERROR_REPORT_Msk 0x2000UL 939 #define ETH_DMA_CONFIG_RX_BUF_SIZE_Pos 16UL 940 #define ETH_DMA_CONFIG_RX_BUF_SIZE_Msk 0xFF0000UL 941 #define ETH_DMA_CONFIG_FORCE_DISCARD_ON_ERR_Pos 24UL 942 #define ETH_DMA_CONFIG_FORCE_DISCARD_ON_ERR_Msk 0x1000000UL 943 #define ETH_DMA_CONFIG_FORCE_MAX_AMBA_BURST_RX_Pos 25UL 944 #define ETH_DMA_CONFIG_FORCE_MAX_AMBA_BURST_RX_Msk 0x2000000UL 945 #define ETH_DMA_CONFIG_FORCE_MAX_AMBA_BURST_TX_Pos 26UL 946 #define ETH_DMA_CONFIG_FORCE_MAX_AMBA_BURST_TX_Msk 0x4000000UL 947 #define ETH_DMA_CONFIG_RX_BD_EXTENDED_MODE_EN_Pos 28UL 948 #define ETH_DMA_CONFIG_RX_BD_EXTENDED_MODE_EN_Msk 0x10000000UL 949 #define ETH_DMA_CONFIG_TX_BD_EXTENDED_MODE_EN_Pos 29UL 950 #define ETH_DMA_CONFIG_TX_BD_EXTENDED_MODE_EN_Msk 0x20000000UL 951 #define ETH_DMA_CONFIG_DMA_ADDR_BUS_WIDTH_1_Pos 30UL 952 #define ETH_DMA_CONFIG_DMA_ADDR_BUS_WIDTH_1_Msk 0x40000000UL 953 /* ETH.TRANSMIT_STATUS */ 954 #define ETH_TRANSMIT_STATUS_USED_BIT_READ_Pos 0UL 955 #define ETH_TRANSMIT_STATUS_USED_BIT_READ_Msk 0x1UL 956 #define ETH_TRANSMIT_STATUS_COLLISION_OCCURRED_Pos 1UL 957 #define ETH_TRANSMIT_STATUS_COLLISION_OCCURRED_Msk 0x2UL 958 #define ETH_TRANSMIT_STATUS_RETRY_LIMIT_EXCEEDED_Pos 2UL 959 #define ETH_TRANSMIT_STATUS_RETRY_LIMIT_EXCEEDED_Msk 0x4UL 960 #define ETH_TRANSMIT_STATUS_TRANSMIT_GO_Pos 3UL 961 #define ETH_TRANSMIT_STATUS_TRANSMIT_GO_Msk 0x8UL 962 #define ETH_TRANSMIT_STATUS_AMBA_ERROR123_Pos 4UL 963 #define ETH_TRANSMIT_STATUS_AMBA_ERROR123_Msk 0x10UL 964 #define ETH_TRANSMIT_STATUS_TRANSMIT_COMPLETE123_Pos 5UL 965 #define ETH_TRANSMIT_STATUS_TRANSMIT_COMPLETE123_Msk 0x20UL 966 #define ETH_TRANSMIT_STATUS_TRANSMIT_UNDER_RUN123_Pos 6UL 967 #define ETH_TRANSMIT_STATUS_TRANSMIT_UNDER_RUN123_Msk 0x40UL 968 #define ETH_TRANSMIT_STATUS_LATE_COLLISION_OCCURRED_Pos 7UL 969 #define ETH_TRANSMIT_STATUS_LATE_COLLISION_OCCURRED_Msk 0x80UL 970 #define ETH_TRANSMIT_STATUS_RESP_NOT_OK123_Pos 8UL 971 #define ETH_TRANSMIT_STATUS_RESP_NOT_OK123_Msk 0x100UL 972 /* ETH.RECEIVE_Q_PTR */ 973 #define ETH_RECEIVE_Q_PTR_DMA_RX_DIS_Q_Pos 0UL 974 #define ETH_RECEIVE_Q_PTR_DMA_RX_DIS_Q_Msk 0x1UL 975 #define ETH_RECEIVE_Q_PTR_DMA_RX_Q_PTR_Pos 2UL 976 #define ETH_RECEIVE_Q_PTR_DMA_RX_Q_PTR_Msk 0xFFFFFFFCUL 977 /* ETH.TRANSMIT_Q_PTR */ 978 #define ETH_TRANSMIT_Q_PTR_DMA_TX_DIS_Q_Pos 0UL 979 #define ETH_TRANSMIT_Q_PTR_DMA_TX_DIS_Q_Msk 0x1UL 980 #define ETH_TRANSMIT_Q_PTR_DMA_TX_Q_PTR_Pos 2UL 981 #define ETH_TRANSMIT_Q_PTR_DMA_TX_Q_PTR_Msk 0xFFFFFFFCUL 982 /* ETH.RECEIVE_STATUS */ 983 #define ETH_RECEIVE_STATUS_BUFFER_NOT_AVAILABLE_Pos 0UL 984 #define ETH_RECEIVE_STATUS_BUFFER_NOT_AVAILABLE_Msk 0x1UL 985 #define ETH_RECEIVE_STATUS_FRAME_RECEIVED_Pos 1UL 986 #define ETH_RECEIVE_STATUS_FRAME_RECEIVED_Msk 0x2UL 987 #define ETH_RECEIVE_STATUS_RECEIVE_OVERRUN123_Pos 2UL 988 #define ETH_RECEIVE_STATUS_RECEIVE_OVERRUN123_Msk 0x4UL 989 #define ETH_RECEIVE_STATUS_RESP_NOT_OK1234_Pos 3UL 990 #define ETH_RECEIVE_STATUS_RESP_NOT_OK1234_Msk 0x8UL 991 /* ETH.INT_STATUS */ 992 #define ETH_INT_STATUS_MANAGEMENT_FRAME_SENT_Pos 0UL 993 #define ETH_INT_STATUS_MANAGEMENT_FRAME_SENT_Msk 0x1UL 994 #define ETH_INT_STATUS_RECEIVE_COMPLETE_Pos 1UL 995 #define ETH_INT_STATUS_RECEIVE_COMPLETE_Msk 0x2UL 996 #define ETH_INT_STATUS_RX_USED_BIT_READ_Pos 2UL 997 #define ETH_INT_STATUS_RX_USED_BIT_READ_Msk 0x4UL 998 #define ETH_INT_STATUS_TX_USED_BIT_READ_Pos 3UL 999 #define ETH_INT_STATUS_TX_USED_BIT_READ_Msk 0x8UL 1000 #define ETH_INT_STATUS_TRANSMIT_UNDER_RUN_Pos 4UL 1001 #define ETH_INT_STATUS_TRANSMIT_UNDER_RUN_Msk 0x10UL 1002 #define ETH_INT_STATUS_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_Pos 5UL 1003 #define ETH_INT_STATUS_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_Msk 0x20UL 1004 #define ETH_INT_STATUS_AMBA_ERROR_Pos 6UL 1005 #define ETH_INT_STATUS_AMBA_ERROR_Msk 0x40UL 1006 #define ETH_INT_STATUS_TRANSMIT_COMPLETE_Pos 7UL 1007 #define ETH_INT_STATUS_TRANSMIT_COMPLETE_Msk 0x80UL 1008 #define ETH_INT_STATUS_REMOVED_9_Pos 9UL 1009 #define ETH_INT_STATUS_REMOVED_9_Msk 0x200UL 1010 #define ETH_INT_STATUS_RECEIVE_OVERRUN_Pos 10UL 1011 #define ETH_INT_STATUS_RECEIVE_OVERRUN_Msk 0x400UL 1012 #define ETH_INT_STATUS_RESP_NOT_OK_Pos 11UL 1013 #define ETH_INT_STATUS_RESP_NOT_OK_Msk 0x800UL 1014 #define ETH_INT_STATUS_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED_Pos 12UL 1015 #define ETH_INT_STATUS_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED_Msk 0x1000UL 1016 #define ETH_INT_STATUS_PAUSE_TIME_ELAPSED_Pos 13UL 1017 #define ETH_INT_STATUS_PAUSE_TIME_ELAPSED_Msk 0x2000UL 1018 #define ETH_INT_STATUS_PAUSE_FRAME_TRANSMITTED_Pos 14UL 1019 #define ETH_INT_STATUS_PAUSE_FRAME_TRANSMITTED_Msk 0x4000UL 1020 #define ETH_INT_STATUS_REMOVED_15_Pos 15UL 1021 #define ETH_INT_STATUS_REMOVED_15_Msk 0x8000UL 1022 #define ETH_INT_STATUS_REMOVED_16_Pos 16UL 1023 #define ETH_INT_STATUS_REMOVED_16_Msk 0x10000UL 1024 #define ETH_INT_STATUS_REMOVED_17_Pos 17UL 1025 #define ETH_INT_STATUS_REMOVED_17_Msk 0x20000UL 1026 #define ETH_INT_STATUS_PTP_DELAY_REQ_FRAME_RECEIVED_Pos 18UL 1027 #define ETH_INT_STATUS_PTP_DELAY_REQ_FRAME_RECEIVED_Msk 0x40000UL 1028 #define ETH_INT_STATUS_PTP_SYNC_FRAME_RECEIVED_Pos 19UL 1029 #define ETH_INT_STATUS_PTP_SYNC_FRAME_RECEIVED_Msk 0x80000UL 1030 #define ETH_INT_STATUS_PTP_DELAY_REQ_FRAME_TRANSMITTED_Pos 20UL 1031 #define ETH_INT_STATUS_PTP_DELAY_REQ_FRAME_TRANSMITTED_Msk 0x100000UL 1032 #define ETH_INT_STATUS_PTP_SYNC_FRAME_TRANSMITTED_Pos 21UL 1033 #define ETH_INT_STATUS_PTP_SYNC_FRAME_TRANSMITTED_Msk 0x200000UL 1034 #define ETH_INT_STATUS_PTP_PDELAY_REQ_FRAME_RECEIVED_Pos 22UL 1035 #define ETH_INT_STATUS_PTP_PDELAY_REQ_FRAME_RECEIVED_Msk 0x400000UL 1036 #define ETH_INT_STATUS_PTP_PDELAY_RESP_FRAME_RECEIVED_Pos 23UL 1037 #define ETH_INT_STATUS_PTP_PDELAY_RESP_FRAME_RECEIVED_Msk 0x800000UL 1038 #define ETH_INT_STATUS_PTP_PDELAY_REQ_FRAME_TRANSMITTED_Pos 24UL 1039 #define ETH_INT_STATUS_PTP_PDELAY_REQ_FRAME_TRANSMITTED_Msk 0x1000000UL 1040 #define ETH_INT_STATUS_PTP_PDELAY_RESP_FRAME_TRANSMITTED_Pos 25UL 1041 #define ETH_INT_STATUS_PTP_PDELAY_RESP_FRAME_TRANSMITTED_Msk 0x2000000UL 1042 #define ETH_INT_STATUS_TSU_SECONDS_REGISTER_INCREMENT_Pos 26UL 1043 #define ETH_INT_STATUS_TSU_SECONDS_REGISTER_INCREMENT_Msk 0x4000000UL 1044 #define ETH_INT_STATUS_RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE_Pos 27UL 1045 #define ETH_INT_STATUS_RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE_Msk 0x8000000UL 1046 #define ETH_INT_STATUS_REMOVED_28_Pos 28UL 1047 #define ETH_INT_STATUS_REMOVED_28_Msk 0x10000000UL 1048 #define ETH_INT_STATUS_TSU_TIMER_COMPARISON_INTERRUPT_Pos 29UL 1049 #define ETH_INT_STATUS_TSU_TIMER_COMPARISON_INTERRUPT_Msk 0x20000000UL 1050 /* ETH.INT_ENABLE */ 1051 #define ETH_INT_ENABLE_ENABLE_MANAGEMENT_DONE_INTERRUPT_Pos 0UL 1052 #define ETH_INT_ENABLE_ENABLE_MANAGEMENT_DONE_INTERRUPT_Msk 0x1UL 1053 #define ETH_INT_ENABLE_ENABLE_RECEIVE_COMPLETE_INTERRUPT_Pos 1UL 1054 #define ETH_INT_ENABLE_ENABLE_RECEIVE_COMPLETE_INTERRUPT_Msk 0x2UL 1055 #define ETH_INT_ENABLE_ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT_Pos 2UL 1056 #define ETH_INT_ENABLE_ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT_Msk 0x4UL 1057 #define ETH_INT_ENABLE_ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT_Pos 3UL 1058 #define ETH_INT_ENABLE_ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT_Msk 0x8UL 1059 #define ETH_INT_ENABLE_ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_Pos 4UL 1060 #define ETH_INT_ENABLE_ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_Msk 0x10UL 1061 #define ETH_INT_ENABLE_ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Pos 5UL 1062 #define ETH_INT_ENABLE_ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Msk 0x20UL 1063 #define ETH_INT_ENABLE_ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Pos 6UL 1064 #define ETH_INT_ENABLE_ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Msk 0x40UL 1065 #define ETH_INT_ENABLE_ENABLE_TRANSMIT_COMPLETE_INTERRUPT_Pos 7UL 1066 #define ETH_INT_ENABLE_ENABLE_TRANSMIT_COMPLETE_INTERRUPT_Msk 0x80UL 1067 #define ETH_INT_ENABLE_UNUSED_8_Pos 8UL 1068 #define ETH_INT_ENABLE_UNUSED_8_Msk 0x100UL 1069 #define ETH_INT_ENABLE_UNUSED_9_Pos 9UL 1070 #define ETH_INT_ENABLE_UNUSED_9_Msk 0x200UL 1071 #define ETH_INT_ENABLE_ENABLE_RECEIVE_OVERRUN_INTERRUPT_Pos 10UL 1072 #define ETH_INT_ENABLE_ENABLE_RECEIVE_OVERRUN_INTERRUPT_Msk 0x400UL 1073 #define ETH_INT_ENABLE_ENABLE_RESP_NOT_OK_INTERRUPT_Pos 11UL 1074 #define ETH_INT_ENABLE_ENABLE_RESP_NOT_OK_INTERRUPT_Msk 0x800UL 1075 #define ETH_INT_ENABLE_ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_Pos 12UL 1076 #define ETH_INT_ENABLE_ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_Msk 0x1000UL 1077 #define ETH_INT_ENABLE_ENABLE_PAUSE_TIME_ZERO_INTERRUPT_Pos 13UL 1078 #define ETH_INT_ENABLE_ENABLE_PAUSE_TIME_ZERO_INTERRUPT_Msk 0x2000UL 1079 #define ETH_INT_ENABLE_ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT_Pos 14UL 1080 #define ETH_INT_ENABLE_ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT_Msk 0x4000UL 1081 #define ETH_INT_ENABLE_UNUSED_15_Pos 15UL 1082 #define ETH_INT_ENABLE_UNUSED_15_Msk 0x8000UL 1083 #define ETH_INT_ENABLE_UNUSED_16_Pos 16UL 1084 #define ETH_INT_ENABLE_UNUSED_16_Msk 0x10000UL 1085 #define ETH_INT_ENABLE_UNUSED_17_Pos 17UL 1086 #define ETH_INT_ENABLE_UNUSED_17_Msk 0x20000UL 1087 #define ETH_INT_ENABLE_ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED_Pos 18UL 1088 #define ETH_INT_ENABLE_ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED_Msk 0x40000UL 1089 #define ETH_INT_ENABLE_ENABLE_PTP_SYNC_FRAME_RECEIVED_Pos 19UL 1090 #define ETH_INT_ENABLE_ENABLE_PTP_SYNC_FRAME_RECEIVED_Msk 0x80000UL 1091 #define ETH_INT_ENABLE_ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED_Pos 20UL 1092 #define ETH_INT_ENABLE_ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED_Msk 0x100000UL 1093 #define ETH_INT_ENABLE_ENABLE_PTP_SYNC_FRAME_TRANSMITTED_Pos 21UL 1094 #define ETH_INT_ENABLE_ENABLE_PTP_SYNC_FRAME_TRANSMITTED_Msk 0x200000UL 1095 #define ETH_INT_ENABLE_ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED_Pos 22UL 1096 #define ETH_INT_ENABLE_ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED_Msk 0x400000UL 1097 #define ETH_INT_ENABLE_ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED_Pos 23UL 1098 #define ETH_INT_ENABLE_ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED_Msk 0x800000UL 1099 #define ETH_INT_ENABLE_ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED_Pos 24UL 1100 #define ETH_INT_ENABLE_ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED_Msk 0x1000000UL 1101 #define ETH_INT_ENABLE_ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED_Pos 25UL 1102 #define ETH_INT_ENABLE_ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED_Msk 0x2000000UL 1103 #define ETH_INT_ENABLE_ENABLE_TSU_SECONDS_REGISTER_INCREMENT_Pos 26UL 1104 #define ETH_INT_ENABLE_ENABLE_TSU_SECONDS_REGISTER_INCREMENT_Msk 0x4000000UL 1105 #define ETH_INT_ENABLE_ENABLE_RX_LPI_INDICATION_INTERRUPT_Pos 27UL 1106 #define ETH_INT_ENABLE_ENABLE_RX_LPI_INDICATION_INTERRUPT_Msk 0x8000000UL 1107 #define ETH_INT_ENABLE_UNUSED_28_Pos 28UL 1108 #define ETH_INT_ENABLE_UNUSED_28_Msk 0x10000000UL 1109 #define ETH_INT_ENABLE_ENABLE_TSU_TIMER_COMPARISON_INTERRUPT_Pos 29UL 1110 #define ETH_INT_ENABLE_ENABLE_TSU_TIMER_COMPARISON_INTERRUPT_Msk 0x20000000UL 1111 /* ETH.INT_DISABLE */ 1112 #define ETH_INT_DISABLE_DISABLE_MANAGEMENT_DONE_INTERRUPT_Pos 0UL 1113 #define ETH_INT_DISABLE_DISABLE_MANAGEMENT_DONE_INTERRUPT_Msk 0x1UL 1114 #define ETH_INT_DISABLE_DISABLE_RECEIVE_COMPLETE_INTERRUPT_Pos 1UL 1115 #define ETH_INT_DISABLE_DISABLE_RECEIVE_COMPLETE_INTERRUPT_Msk 0x2UL 1116 #define ETH_INT_DISABLE_DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT_Pos 2UL 1117 #define ETH_INT_DISABLE_DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT_Msk 0x4UL 1118 #define ETH_INT_DISABLE_DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT_Pos 3UL 1119 #define ETH_INT_DISABLE_DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT_Msk 0x8UL 1120 #define ETH_INT_DISABLE_DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_Pos 4UL 1121 #define ETH_INT_DISABLE_DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_Msk 0x10UL 1122 #define ETH_INT_DISABLE_DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Pos 5UL 1123 #define ETH_INT_DISABLE_DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Msk 0x20UL 1124 #define ETH_INT_DISABLE_DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Pos 6UL 1125 #define ETH_INT_DISABLE_DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Msk 0x40UL 1126 #define ETH_INT_DISABLE_DISABLE_TRANSMIT_COMPLETE_INTERRUPT_Pos 7UL 1127 #define ETH_INT_DISABLE_DISABLE_TRANSMIT_COMPLETE_INTERRUPT_Msk 0x80UL 1128 #define ETH_INT_DISABLE_UNUSED_8_Pos 8UL 1129 #define ETH_INT_DISABLE_UNUSED_8_Msk 0x100UL 1130 #define ETH_INT_DISABLE_UNUSED_9_Pos 9UL 1131 #define ETH_INT_DISABLE_UNUSED_9_Msk 0x200UL 1132 #define ETH_INT_DISABLE_DISABLE_RECEIVE_OVERRUN_INTERRUPT_Pos 10UL 1133 #define ETH_INT_DISABLE_DISABLE_RECEIVE_OVERRUN_INTERRUPT_Msk 0x400UL 1134 #define ETH_INT_DISABLE_DISABLE_RESP_NOT_OK_INTERRUPT_Pos 11UL 1135 #define ETH_INT_DISABLE_DISABLE_RESP_NOT_OK_INTERRUPT_Msk 0x800UL 1136 #define ETH_INT_DISABLE_DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_Pos 12UL 1137 #define ETH_INT_DISABLE_DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_Msk 0x1000UL 1138 #define ETH_INT_DISABLE_DISABLE_PAUSE_TIME_ZERO_INTERRUPT_Pos 13UL 1139 #define ETH_INT_DISABLE_DISABLE_PAUSE_TIME_ZERO_INTERRUPT_Msk 0x2000UL 1140 #define ETH_INT_DISABLE_DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT_Pos 14UL 1141 #define ETH_INT_DISABLE_DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT_Msk 0x4000UL 1142 #define ETH_INT_DISABLE_UNUSED_15_Pos 15UL 1143 #define ETH_INT_DISABLE_UNUSED_15_Msk 0x8000UL 1144 #define ETH_INT_DISABLE_UNUSED_16_Pos 16UL 1145 #define ETH_INT_DISABLE_UNUSED_16_Msk 0x10000UL 1146 #define ETH_INT_DISABLE_UNUSED_17_Pos 17UL 1147 #define ETH_INT_DISABLE_UNUSED_17_Msk 0x20000UL 1148 #define ETH_INT_DISABLE_DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED_Pos 18UL 1149 #define ETH_INT_DISABLE_DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED_Msk 0x40000UL 1150 #define ETH_INT_DISABLE_DISABLE_PTP_SYNC_FRAME_RECEIVED_Pos 19UL 1151 #define ETH_INT_DISABLE_DISABLE_PTP_SYNC_FRAME_RECEIVED_Msk 0x80000UL 1152 #define ETH_INT_DISABLE_DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED_Pos 20UL 1153 #define ETH_INT_DISABLE_DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED_Msk 0x100000UL 1154 #define ETH_INT_DISABLE_DISABLE_PTP_SYNC_FRAME_TRANSMITTED_Pos 21UL 1155 #define ETH_INT_DISABLE_DISABLE_PTP_SYNC_FRAME_TRANSMITTED_Msk 0x200000UL 1156 #define ETH_INT_DISABLE_DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED_Pos 22UL 1157 #define ETH_INT_DISABLE_DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED_Msk 0x400000UL 1158 #define ETH_INT_DISABLE_DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED_Pos 23UL 1159 #define ETH_INT_DISABLE_DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED_Msk 0x800000UL 1160 #define ETH_INT_DISABLE_DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED_Pos 24UL 1161 #define ETH_INT_DISABLE_DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED_Msk 0x1000000UL 1162 #define ETH_INT_DISABLE_DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED_Pos 25UL 1163 #define ETH_INT_DISABLE_DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED_Msk 0x2000000UL 1164 #define ETH_INT_DISABLE_DISABLE_TSU_SECONDS_REGISTER_INCREMENT_Pos 26UL 1165 #define ETH_INT_DISABLE_DISABLE_TSU_SECONDS_REGISTER_INCREMENT_Msk 0x4000000UL 1166 #define ETH_INT_DISABLE_DISABLE_RX_LPI_INDICATION_INTERRUPT_Pos 27UL 1167 #define ETH_INT_DISABLE_DISABLE_RX_LPI_INDICATION_INTERRUPT_Msk 0x8000000UL 1168 #define ETH_INT_DISABLE_UNUSED_28_Pos 28UL 1169 #define ETH_INT_DISABLE_UNUSED_28_Msk 0x10000000UL 1170 #define ETH_INT_DISABLE_DISABLE_TSU_TIMER_COMPARISON_INTERRUPT_Pos 29UL 1171 #define ETH_INT_DISABLE_DISABLE_TSU_TIMER_COMPARISON_INTERRUPT_Msk 0x20000000UL 1172 #define ETH_INT_DISABLE_RESERVED_30_30_Pos 30UL 1173 #define ETH_INT_DISABLE_RESERVED_30_30_Msk 0x40000000UL 1174 #define ETH_INT_DISABLE_RESERVED_31_31_Pos 31UL 1175 #define ETH_INT_DISABLE_RESERVED_31_31_Msk 0x80000000UL 1176 /* ETH.INT_MASK */ 1177 #define ETH_INT_MASK_MANAGEMENT_DONE_INTERRUPT_MASK_Pos 0UL 1178 #define ETH_INT_MASK_MANAGEMENT_DONE_INTERRUPT_MASK_Msk 0x1UL 1179 #define ETH_INT_MASK_RECEIVE_COMPLETE_INTERRUPT_MASK_Pos 1UL 1180 #define ETH_INT_MASK_RECEIVE_COMPLETE_INTERRUPT_MASK_Msk 0x2UL 1181 #define ETH_INT_MASK_RECEIVE_USED_BIT_READ_INTERRUPT_MASK_Pos 2UL 1182 #define ETH_INT_MASK_RECEIVE_USED_BIT_READ_INTERRUPT_MASK_Msk 0x4UL 1183 #define ETH_INT_MASK_TRANSMIT_USED_BIT_READ_INTERRUPT_MASK_Pos 3UL 1184 #define ETH_INT_MASK_TRANSMIT_USED_BIT_READ_INTERRUPT_MASK_Msk 0x8UL 1185 #define ETH_INT_MASK_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK_Pos 4UL 1186 #define ETH_INT_MASK_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK_Msk 0x10UL 1187 #define ETH_INT_MASK_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK_Pos 5UL 1188 #define ETH_INT_MASK_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK_Msk 0x20UL 1189 #define ETH_INT_MASK_AMBA_ERROR_INTERRUPT_MASK_Pos 6UL 1190 #define ETH_INT_MASK_AMBA_ERROR_INTERRUPT_MASK_Msk 0x40UL 1191 #define ETH_INT_MASK_TRANSMIT_COMPLETE_INTERRUPT_MASK_Pos 7UL 1192 #define ETH_INT_MASK_TRANSMIT_COMPLETE_INTERRUPT_MASK_Msk 0x80UL 1193 #define ETH_INT_MASK_UNUSED_8_Pos 8UL 1194 #define ETH_INT_MASK_UNUSED_8_Msk 0x100UL 1195 #define ETH_INT_MASK_UNUSED_9_Pos 9UL 1196 #define ETH_INT_MASK_UNUSED_9_Msk 0x200UL 1197 #define ETH_INT_MASK_RECEIVE_OVERRUN_INTERRUPT_MASK_Pos 10UL 1198 #define ETH_INT_MASK_RECEIVE_OVERRUN_INTERRUPT_MASK_Msk 0x400UL 1199 #define ETH_INT_MASK_RESP_NOT_OK_INTERRUPT_MASK_Pos 11UL 1200 #define ETH_INT_MASK_RESP_NOT_OK_INTERRUPT_MASK_Msk 0x800UL 1201 #define ETH_INT_MASK_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK_Pos 12UL 1202 #define ETH_INT_MASK_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK_Msk 0x1000UL 1203 #define ETH_INT_MASK_PAUSE_TIME_ZERO_INTERRUPT_MASK_Pos 13UL 1204 #define ETH_INT_MASK_PAUSE_TIME_ZERO_INTERRUPT_MASK_Msk 0x2000UL 1205 #define ETH_INT_MASK_PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK_Pos 14UL 1206 #define ETH_INT_MASK_PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK_Msk 0x4000UL 1207 #define ETH_INT_MASK_UNUSED_15_Pos 15UL 1208 #define ETH_INT_MASK_UNUSED_15_Msk 0x8000UL 1209 #define ETH_INT_MASK_UNUSED_16_Pos 16UL 1210 #define ETH_INT_MASK_UNUSED_16_Msk 0x10000UL 1211 #define ETH_INT_MASK_UNUSED_17_Pos 17UL 1212 #define ETH_INT_MASK_UNUSED_17_Msk 0x20000UL 1213 #define ETH_INT_MASK_PTP_DELAY_REQ_FRAME_RECEIVED_MASK_Pos 18UL 1214 #define ETH_INT_MASK_PTP_DELAY_REQ_FRAME_RECEIVED_MASK_Msk 0x40000UL 1215 #define ETH_INT_MASK_PTP_SYNC_FRAME_RECEIVED_MASK_Pos 19UL 1216 #define ETH_INT_MASK_PTP_SYNC_FRAME_RECEIVED_MASK_Msk 0x80000UL 1217 #define ETH_INT_MASK_PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK_Pos 20UL 1218 #define ETH_INT_MASK_PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK_Msk 0x100000UL 1219 #define ETH_INT_MASK_PTP_SYNC_FRAME_TRANSMITTED_MASK_Pos 21UL 1220 #define ETH_INT_MASK_PTP_SYNC_FRAME_TRANSMITTED_MASK_Msk 0x200000UL 1221 #define ETH_INT_MASK_PTP_PDELAY_REQ_FRAME_RECEIVED_MASK_Pos 22UL 1222 #define ETH_INT_MASK_PTP_PDELAY_REQ_FRAME_RECEIVED_MASK_Msk 0x400000UL 1223 #define ETH_INT_MASK_PTP_PDELAY_RESP_FRAME_RECEIVED_MASK_Pos 23UL 1224 #define ETH_INT_MASK_PTP_PDELAY_RESP_FRAME_RECEIVED_MASK_Msk 0x800000UL 1225 #define ETH_INT_MASK_PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK_Pos 24UL 1226 #define ETH_INT_MASK_PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK_Msk 0x1000000UL 1227 #define ETH_INT_MASK_PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK_Pos 25UL 1228 #define ETH_INT_MASK_PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK_Msk 0x2000000UL 1229 #define ETH_INT_MASK_TSU_SECONDS_REGISTER_INCREMENT_MASK_Pos 26UL 1230 #define ETH_INT_MASK_TSU_SECONDS_REGISTER_INCREMENT_MASK_Msk 0x4000000UL 1231 #define ETH_INT_MASK_RX_LPI_INDICATION_MASK_Pos 27UL 1232 #define ETH_INT_MASK_RX_LPI_INDICATION_MASK_Msk 0x8000000UL 1233 #define ETH_INT_MASK_UNUSED_28_Pos 28UL 1234 #define ETH_INT_MASK_UNUSED_28_Msk 0x10000000UL 1235 #define ETH_INT_MASK_TSU_TIMER_COMPARISON_MASK_Pos 29UL 1236 #define ETH_INT_MASK_TSU_TIMER_COMPARISON_MASK_Msk 0x20000000UL 1237 /* ETH.PHY_MANAGEMENT */ 1238 #define ETH_PHY_MANAGEMENT_PHY_WRITE_READ_DATA_Pos 0UL 1239 #define ETH_PHY_MANAGEMENT_PHY_WRITE_READ_DATA_Msk 0xFFFFUL 1240 #define ETH_PHY_MANAGEMENT_WRITE10_Pos 16UL 1241 #define ETH_PHY_MANAGEMENT_WRITE10_Msk 0x30000UL 1242 #define ETH_PHY_MANAGEMENT_REGISTER_ADDRESS_Pos 18UL 1243 #define ETH_PHY_MANAGEMENT_REGISTER_ADDRESS_Msk 0x7C0000UL 1244 #define ETH_PHY_MANAGEMENT_PHY_ADDRESS_Pos 23UL 1245 #define ETH_PHY_MANAGEMENT_PHY_ADDRESS_Msk 0xF800000UL 1246 #define ETH_PHY_MANAGEMENT_OPERATION_Pos 28UL 1247 #define ETH_PHY_MANAGEMENT_OPERATION_Msk 0x30000000UL 1248 #define ETH_PHY_MANAGEMENT_WRITE1_Pos 30UL 1249 #define ETH_PHY_MANAGEMENT_WRITE1_Msk 0x40000000UL 1250 #define ETH_PHY_MANAGEMENT_WRITE0_Pos 31UL 1251 #define ETH_PHY_MANAGEMENT_WRITE0_Msk 0x80000000UL 1252 /* ETH.PAUSE_TIME */ 1253 #define ETH_PAUSE_TIME_QUANTUM_Pos 0UL 1254 #define ETH_PAUSE_TIME_QUANTUM_Msk 0xFFFFUL 1255 /* ETH.TX_PAUSE_QUANTUM */ 1256 #define ETH_TX_PAUSE_QUANTUM_QUANTUM_Pos 0UL 1257 #define ETH_TX_PAUSE_QUANTUM_QUANTUM_Msk 0xFFFFUL 1258 #define ETH_TX_PAUSE_QUANTUM_QUANTUM_P1_Pos 16UL 1259 #define ETH_TX_PAUSE_QUANTUM_QUANTUM_P1_Msk 0xFFFF0000UL 1260 /* ETH.PBUF_TXCUTTHRU */ 1261 #define ETH_PBUF_TXCUTTHRU_DMA_TX_CUTTHRU_THRESHOLD_Pos 0UL 1262 #define ETH_PBUF_TXCUTTHRU_DMA_TX_CUTTHRU_THRESHOLD_Msk 0x1FFUL 1263 #define ETH_PBUF_TXCUTTHRU_DMA_TX_CUTTHRU_Pos 31UL 1264 #define ETH_PBUF_TXCUTTHRU_DMA_TX_CUTTHRU_Msk 0x80000000UL 1265 /* ETH.PBUF_RXCUTTHRU */ 1266 #define ETH_PBUF_RXCUTTHRU_DMA_RX_CUTTHRU_THRESHOLD_Pos 0UL 1267 #define ETH_PBUF_RXCUTTHRU_DMA_RX_CUTTHRU_THRESHOLD_Msk 0xFFUL 1268 #define ETH_PBUF_RXCUTTHRU_DMA_RX_CUTTHRU_Pos 31UL 1269 #define ETH_PBUF_RXCUTTHRU_DMA_RX_CUTTHRU_Msk 0x80000000UL 1270 /* ETH.JUMBO_MAX_LENGTH */ 1271 #define ETH_JUMBO_MAX_LENGTH_JUMBO_MAX_LENGTH_Pos 0UL 1272 #define ETH_JUMBO_MAX_LENGTH_JUMBO_MAX_LENGTH_Msk 0x3FFFUL 1273 /* ETH.EXTERNAL_FIFO_INTERFACE */ 1274 #define ETH_EXTERNAL_FIFO_INTERFACE_REMOVED_31_0_Pos 0UL 1275 #define ETH_EXTERNAL_FIFO_INTERFACE_REMOVED_31_0_Msk 0xFFFFFFFFUL 1276 /* ETH.AXI_MAX_PIPELINE */ 1277 #define ETH_AXI_MAX_PIPELINE_AR2R_MAX_PIPELINE_Pos 0UL 1278 #define ETH_AXI_MAX_PIPELINE_AR2R_MAX_PIPELINE_Msk 0xFFUL 1279 #define ETH_AXI_MAX_PIPELINE_AW2W_MAX_PIPELINE_Pos 8UL 1280 #define ETH_AXI_MAX_PIPELINE_AW2W_MAX_PIPELINE_Msk 0xFF00UL 1281 #define ETH_AXI_MAX_PIPELINE_USE_AW2B_FILL_Pos 16UL 1282 #define ETH_AXI_MAX_PIPELINE_USE_AW2B_FILL_Msk 0x10000UL 1283 /* ETH.RSC_CONTROL */ 1284 #define ETH_RSC_CONTROL_REMOVED_31_0_Pos 0UL 1285 #define ETH_RSC_CONTROL_REMOVED_31_0_Msk 0xFFFFFFFFUL 1286 /* ETH.INT_MODERATION */ 1287 #define ETH_INT_MODERATION_RX_INT_MODERATION_Pos 0UL 1288 #define ETH_INT_MODERATION_RX_INT_MODERATION_Msk 0xFFUL 1289 #define ETH_INT_MODERATION_TX_INT_MODERATION_Pos 16UL 1290 #define ETH_INT_MODERATION_TX_INT_MODERATION_Msk 0xFF0000UL 1291 /* ETH.SYS_WAKE_TIME */ 1292 #define ETH_SYS_WAKE_TIME_SYS_WAKE_TIME_Pos 0UL 1293 #define ETH_SYS_WAKE_TIME_SYS_WAKE_TIME_Msk 0xFFFFUL 1294 /* ETH.HASH_BOTTOM */ 1295 #define ETH_HASH_BOTTOM_ADDRESS_HASH_B_Pos 0UL 1296 #define ETH_HASH_BOTTOM_ADDRESS_HASH_B_Msk 0xFFFFFFFFUL 1297 /* ETH.HASH_TOP */ 1298 #define ETH_HASH_TOP_ADDRESS_HASH_T_Pos 0UL 1299 #define ETH_HASH_TOP_ADDRESS_HASH_T_Msk 0xFFFFFFFFUL 1300 /* ETH.SPEC_ADD1_BOTTOM */ 1301 #define ETH_SPEC_ADD1_BOTTOM_ADDRESS_ADD1_B_Pos 0UL 1302 #define ETH_SPEC_ADD1_BOTTOM_ADDRESS_ADD1_B_Msk 0xFFFFFFFFUL 1303 /* ETH.SPEC_ADD1_TOP */ 1304 #define ETH_SPEC_ADD1_TOP_ADDRESS_TOP_Pos 0UL 1305 #define ETH_SPEC_ADD1_TOP_ADDRESS_TOP_Msk 0xFFFFUL 1306 #define ETH_SPEC_ADD1_TOP_FILTER_TYPE_Pos 16UL 1307 #define ETH_SPEC_ADD1_TOP_FILTER_TYPE_Msk 0x10000UL 1308 /* ETH.SPEC_ADD2_BOTTOM */ 1309 #define ETH_SPEC_ADD2_BOTTOM_ADDRESS_BOTTOM_Pos 0UL 1310 #define ETH_SPEC_ADD2_BOTTOM_ADDRESS_BOTTOM_Msk 0xFFFFFFFFUL 1311 /* ETH.SPEC_ADD2_TOP */ 1312 #define ETH_SPEC_ADD2_TOP_ADDRESS_TOP_Pos 0UL 1313 #define ETH_SPEC_ADD2_TOP_ADDRESS_TOP_Msk 0xFFFFUL 1314 #define ETH_SPEC_ADD2_TOP_FILTER_TYPE_Pos 16UL 1315 #define ETH_SPEC_ADD2_TOP_FILTER_TYPE_Msk 0x10000UL 1316 #define ETH_SPEC_ADD2_TOP_FILTER_BYTE_MASK_Pos 24UL 1317 #define ETH_SPEC_ADD2_TOP_FILTER_BYTE_MASK_Msk 0x3F000000UL 1318 /* ETH.SPEC_ADD3_BOTTOM */ 1319 #define ETH_SPEC_ADD3_BOTTOM_ADDRESS_BOTTOM_Pos 0UL 1320 #define ETH_SPEC_ADD3_BOTTOM_ADDRESS_BOTTOM_Msk 0xFFFFFFFFUL 1321 /* ETH.SPEC_ADD3_TOP */ 1322 #define ETH_SPEC_ADD3_TOP_ADDRESS_TOP_Pos 0UL 1323 #define ETH_SPEC_ADD3_TOP_ADDRESS_TOP_Msk 0xFFFFUL 1324 #define ETH_SPEC_ADD3_TOP_FILTER_TYPE_Pos 16UL 1325 #define ETH_SPEC_ADD3_TOP_FILTER_TYPE_Msk 0x10000UL 1326 #define ETH_SPEC_ADD3_TOP_FILTER_BYTE_MASK_Pos 24UL 1327 #define ETH_SPEC_ADD3_TOP_FILTER_BYTE_MASK_Msk 0x3F000000UL 1328 /* ETH.SPEC_ADD4_BOTTOM */ 1329 #define ETH_SPEC_ADD4_BOTTOM_ADDRESS_BOTTOM_Pos 0UL 1330 #define ETH_SPEC_ADD4_BOTTOM_ADDRESS_BOTTOM_Msk 0xFFFFFFFFUL 1331 /* ETH.SPEC_ADD4_TOP */ 1332 #define ETH_SPEC_ADD4_TOP_ADDRESS_TOP_Pos 0UL 1333 #define ETH_SPEC_ADD4_TOP_ADDRESS_TOP_Msk 0xFFFFUL 1334 #define ETH_SPEC_ADD4_TOP_FILTER_TYPE_Pos 16UL 1335 #define ETH_SPEC_ADD4_TOP_FILTER_TYPE_Msk 0x10000UL 1336 #define ETH_SPEC_ADD4_TOP_FILTER_BYTE_MASK_Pos 24UL 1337 #define ETH_SPEC_ADD4_TOP_FILTER_BYTE_MASK_Msk 0x3F000000UL 1338 /* ETH.SPEC_TYPE1 */ 1339 #define ETH_SPEC_TYPE1_MATCH_Pos 0UL 1340 #define ETH_SPEC_TYPE1_MATCH_Msk 0xFFFFUL 1341 #define ETH_SPEC_TYPE1_ENABLE_COPY_Pos 31UL 1342 #define ETH_SPEC_TYPE1_ENABLE_COPY_Msk 0x80000000UL 1343 /* ETH.SPEC_TYPE2 */ 1344 #define ETH_SPEC_TYPE2_MATCH_Pos 0UL 1345 #define ETH_SPEC_TYPE2_MATCH_Msk 0xFFFFUL 1346 #define ETH_SPEC_TYPE2_ENABLE_COPY_Pos 31UL 1347 #define ETH_SPEC_TYPE2_ENABLE_COPY_Msk 0x80000000UL 1348 /* ETH.SPEC_TYPE3 */ 1349 #define ETH_SPEC_TYPE3_MATCH_Pos 0UL 1350 #define ETH_SPEC_TYPE3_MATCH_Msk 0xFFFFUL 1351 #define ETH_SPEC_TYPE3_ENABLE_COPY_Pos 31UL 1352 #define ETH_SPEC_TYPE3_ENABLE_COPY_Msk 0x80000000UL 1353 /* ETH.SPEC_TYPE4 */ 1354 #define ETH_SPEC_TYPE4_MATCH_Pos 0UL 1355 #define ETH_SPEC_TYPE4_MATCH_Msk 0xFFFFUL 1356 #define ETH_SPEC_TYPE4_ENABLE_COPY_Pos 31UL 1357 #define ETH_SPEC_TYPE4_ENABLE_COPY_Msk 0x80000000UL 1358 /* ETH.WOL_REGISTER */ 1359 #define ETH_WOL_REGISTER_ADDR_Pos 0UL 1360 #define ETH_WOL_REGISTER_ADDR_Msk 0xFFFFUL 1361 #define ETH_WOL_REGISTER_WOL_MASK_0_Pos 16UL 1362 #define ETH_WOL_REGISTER_WOL_MASK_0_Msk 0x10000UL 1363 #define ETH_WOL_REGISTER_WOL_MASK_1_Pos 17UL 1364 #define ETH_WOL_REGISTER_WOL_MASK_1_Msk 0x20000UL 1365 #define ETH_WOL_REGISTER_WOL_MASK_2_Pos 18UL 1366 #define ETH_WOL_REGISTER_WOL_MASK_2_Msk 0x40000UL 1367 #define ETH_WOL_REGISTER_WOL_MASK_3_Pos 19UL 1368 #define ETH_WOL_REGISTER_WOL_MASK_3_Msk 0x80000UL 1369 /* ETH.STRETCH_RATIO */ 1370 #define ETH_STRETCH_RATIO_IPG_STRETCH_Pos 0UL 1371 #define ETH_STRETCH_RATIO_IPG_STRETCH_Msk 0xFFFFUL 1372 /* ETH.STACKED_VLAN */ 1373 #define ETH_STACKED_VLAN_MATCH_Pos 0UL 1374 #define ETH_STACKED_VLAN_MATCH_Msk 0xFFFFUL 1375 #define ETH_STACKED_VLAN_ENABLE_PROCESSING_Pos 31UL 1376 #define ETH_STACKED_VLAN_ENABLE_PROCESSING_Msk 0x80000000UL 1377 /* ETH.TX_PFC_PAUSE */ 1378 #define ETH_TX_PFC_PAUSE_VECTOR_ENABLE_Pos 0UL 1379 #define ETH_TX_PFC_PAUSE_VECTOR_ENABLE_Msk 0xFFUL 1380 #define ETH_TX_PFC_PAUSE_VECTOR_Pos 8UL 1381 #define ETH_TX_PFC_PAUSE_VECTOR_Msk 0xFF00UL 1382 /* ETH.MASK_ADD1_BOTTOM */ 1383 #define ETH_MASK_ADD1_BOTTOM_ADDRESS_MASK_BOTTOM_Pos 0UL 1384 #define ETH_MASK_ADD1_BOTTOM_ADDRESS_MASK_BOTTOM_Msk 0xFFFFFFFFUL 1385 /* ETH.MASK_ADD1_TOP */ 1386 #define ETH_MASK_ADD1_TOP_ADDRESS_MASK_TOP_Pos 0UL 1387 #define ETH_MASK_ADD1_TOP_ADDRESS_MASK_TOP_Msk 0xFFFFUL 1388 /* ETH.DMA_ADDR_OR_MASK */ 1389 #define ETH_DMA_ADDR_OR_MASK_MASK_ENABLE_Pos 0UL 1390 #define ETH_DMA_ADDR_OR_MASK_MASK_ENABLE_Msk 0xFUL 1391 #define ETH_DMA_ADDR_OR_MASK_MASK_VALUE_DA_Pos 28UL 1392 #define ETH_DMA_ADDR_OR_MASK_MASK_VALUE_DA_Msk 0xF0000000UL 1393 /* ETH.RX_PTP_UNICAST */ 1394 #define ETH_RX_PTP_UNICAST_ADDRESS_UNICAST_Pos 0UL 1395 #define ETH_RX_PTP_UNICAST_ADDRESS_UNICAST_Msk 0xFFFFFFFFUL 1396 /* ETH.TX_PTP_UNICAST */ 1397 #define ETH_TX_PTP_UNICAST_ADDRESS_UNICAST_Pos 0UL 1398 #define ETH_TX_PTP_UNICAST_ADDRESS_UNICAST_Msk 0xFFFFFFFFUL 1399 /* ETH.TSU_NSEC_CMP */ 1400 #define ETH_TSU_NSEC_CMP_COMPARISON_NSEC_Pos 0UL 1401 #define ETH_TSU_NSEC_CMP_COMPARISON_NSEC_Msk 0x3FFFFFUL 1402 /* ETH.TSU_SEC_CMP */ 1403 #define ETH_TSU_SEC_CMP_COMPARISON_SEC_Pos 0UL 1404 #define ETH_TSU_SEC_CMP_COMPARISON_SEC_Msk 0xFFFFFFFFUL 1405 /* ETH.TSU_MSB_SEC_CMP */ 1406 #define ETH_TSU_MSB_SEC_CMP_COMPARISON_MSB_SEC_Pos 0UL 1407 #define ETH_TSU_MSB_SEC_CMP_COMPARISON_MSB_SEC_Msk 0xFFFFUL 1408 /* ETH.TSU_PTP_TX_MSB_SEC */ 1409 #define ETH_TSU_PTP_TX_MSB_SEC_TIMER_SECONDS_Pos 0UL 1410 #define ETH_TSU_PTP_TX_MSB_SEC_TIMER_SECONDS_Msk 0xFFFFUL 1411 /* ETH.TSU_PTP_RX_MSB_SEC */ 1412 #define ETH_TSU_PTP_RX_MSB_SEC_TIMER_SECONDS_Pos 0UL 1413 #define ETH_TSU_PTP_RX_MSB_SEC_TIMER_SECONDS_Msk 0xFFFFUL 1414 /* ETH.TSU_PEER_TX_MSB_SEC */ 1415 #define ETH_TSU_PEER_TX_MSB_SEC_TIMER_SECONDS_Pos 0UL 1416 #define ETH_TSU_PEER_TX_MSB_SEC_TIMER_SECONDS_Msk 0xFFFFUL 1417 /* ETH.TSU_PEER_RX_MSB_SEC */ 1418 #define ETH_TSU_PEER_RX_MSB_SEC_TIMER_SECONDS_Pos 0UL 1419 #define ETH_TSU_PEER_RX_MSB_SEC_TIMER_SECONDS_Msk 0xFFFFUL 1420 /* ETH.DPRAM_FILL_DBG */ 1421 #define ETH_DPRAM_FILL_DBG_DMA_TX_RX_FILL_LEVEL_SELECT_Pos 0UL 1422 #define ETH_DPRAM_FILL_DBG_DMA_TX_RX_FILL_LEVEL_SELECT_Msk 0x1UL 1423 #define ETH_DPRAM_FILL_DBG_DMA_TX_Q_FILL_LEVEL_SELECT_Pos 4UL 1424 #define ETH_DPRAM_FILL_DBG_DMA_TX_Q_FILL_LEVEL_SELECT_Msk 0xF0UL 1425 #define ETH_DPRAM_FILL_DBG_DMA_TX_RX_FILL_LEVEL_Pos 16UL 1426 #define ETH_DPRAM_FILL_DBG_DMA_TX_RX_FILL_LEVEL_Msk 0xFFFF0000UL 1427 /* ETH.REVISION_REG */ 1428 #define ETH_REVISION_REG_MODULE_REVISION_Pos 0UL 1429 #define ETH_REVISION_REG_MODULE_REVISION_Msk 0xFFFFUL 1430 #define ETH_REVISION_REG_MODULE_IDENTIFICATION_NUMBER_Pos 16UL 1431 #define ETH_REVISION_REG_MODULE_IDENTIFICATION_NUMBER_Msk 0xFFF0000UL 1432 #define ETH_REVISION_REG_FIX_NUMBER_Pos 28UL 1433 #define ETH_REVISION_REG_FIX_NUMBER_Msk 0xF0000000UL 1434 /* ETH.OCTETS_TXED_BOTTOM */ 1435 #define ETH_OCTETS_TXED_BOTTOM_COUNT_BOTTOM_Pos 0UL 1436 #define ETH_OCTETS_TXED_BOTTOM_COUNT_BOTTOM_Msk 0xFFFFFFFFUL 1437 /* ETH.OCTETS_TXED_TOP */ 1438 #define ETH_OCTETS_TXED_TOP_COUNT_TOP_Pos 0UL 1439 #define ETH_OCTETS_TXED_TOP_COUNT_TOP_Msk 0xFFFFUL 1440 /* ETH.FRAMES_TXED_OK */ 1441 #define ETH_FRAMES_TXED_OK_COUNT_OK_Pos 0UL 1442 #define ETH_FRAMES_TXED_OK_COUNT_OK_Msk 0xFFFFFFFFUL 1443 /* ETH.BROADCAST_TXED */ 1444 #define ETH_BROADCAST_TXED_COUNT_BROADCAST_Pos 0UL 1445 #define ETH_BROADCAST_TXED_COUNT_BROADCAST_Msk 0xFFFFFFFFUL 1446 /* ETH.MULTICAST_TXED */ 1447 #define ETH_MULTICAST_TXED_COUNT_MULTICAST_Pos 0UL 1448 #define ETH_MULTICAST_TXED_COUNT_MULTICAST_Msk 0xFFFFFFFFUL 1449 /* ETH.PAUSE_FRAMES_TXED */ 1450 #define ETH_PAUSE_FRAMES_TXED_COUNT_PAUSE_Pos 0UL 1451 #define ETH_PAUSE_FRAMES_TXED_COUNT_PAUSE_Msk 0xFFFFUL 1452 /* ETH.FRAMES_TXED_64 */ 1453 #define ETH_FRAMES_TXED_64_COUNT_64_Pos 0UL 1454 #define ETH_FRAMES_TXED_64_COUNT_64_Msk 0xFFFFFFFFUL 1455 /* ETH.FRAMES_TXED_65 */ 1456 #define ETH_FRAMES_TXED_65_COUNT_65_Pos 0UL 1457 #define ETH_FRAMES_TXED_65_COUNT_65_Msk 0xFFFFFFFFUL 1458 /* ETH.FRAMES_TXED_128 */ 1459 #define ETH_FRAMES_TXED_128_COUNT_128_Pos 0UL 1460 #define ETH_FRAMES_TXED_128_COUNT_128_Msk 0xFFFFFFFFUL 1461 /* ETH.FRAMES_TXED_256 */ 1462 #define ETH_FRAMES_TXED_256_COUNT_256_Pos 0UL 1463 #define ETH_FRAMES_TXED_256_COUNT_256_Msk 0xFFFFFFFFUL 1464 /* ETH.FRAMES_TXED_512 */ 1465 #define ETH_FRAMES_TXED_512_COUNT_512_Pos 0UL 1466 #define ETH_FRAMES_TXED_512_COUNT_512_Msk 0xFFFFFFFFUL 1467 /* ETH.FRAMES_TXED_1024 */ 1468 #define ETH_FRAMES_TXED_1024_COUNT_1024_Pos 0UL 1469 #define ETH_FRAMES_TXED_1024_COUNT_1024_Msk 0xFFFFFFFFUL 1470 /* ETH.FRAMES_TXED_1519 */ 1471 #define ETH_FRAMES_TXED_1519_COUNT_1519_Pos 0UL 1472 #define ETH_FRAMES_TXED_1519_COUNT_1519_Msk 0xFFFFFFFFUL 1473 /* ETH.TX_UNDERRUNS */ 1474 #define ETH_TX_UNDERRUNS_COUNT_UN_Pos 0UL 1475 #define ETH_TX_UNDERRUNS_COUNT_UN_Msk 0x3FFUL 1476 /* ETH.SINGLE_COLLISIONS */ 1477 #define ETH_SINGLE_COLLISIONS_COUNT14_Pos 0UL 1478 #define ETH_SINGLE_COLLISIONS_COUNT14_Msk 0x3FFFFUL 1479 /* ETH.MULTIPLE_COLLISIONS */ 1480 #define ETH_MULTIPLE_COLLISIONS_COUNT15_Pos 0UL 1481 #define ETH_MULTIPLE_COLLISIONS_COUNT15_Msk 0x3FFFFUL 1482 /* ETH.EXCESSIVE_COLLISIONS */ 1483 #define ETH_EXCESSIVE_COLLISIONS_COUNT16_Pos 0UL 1484 #define ETH_EXCESSIVE_COLLISIONS_COUNT16_Msk 0x3FFUL 1485 /* ETH.LATE_COLLISIONS */ 1486 #define ETH_LATE_COLLISIONS_COUNT17_Pos 0UL 1487 #define ETH_LATE_COLLISIONS_COUNT17_Msk 0x3FFUL 1488 /* ETH.DEFERRED_FRAMES */ 1489 #define ETH_DEFERRED_FRAMES_COUNT18_Pos 0UL 1490 #define ETH_DEFERRED_FRAMES_COUNT18_Msk 0x3FFFFUL 1491 /* ETH.CRS_ERRORS */ 1492 #define ETH_CRS_ERRORS_COUNT19_Pos 0UL 1493 #define ETH_CRS_ERRORS_COUNT19_Msk 0x3FFUL 1494 /* ETH.OCTETS_RXED_BOTTOM */ 1495 #define ETH_OCTETS_RXED_BOTTOM_COUNT_BOTTOM_Pos 0UL 1496 #define ETH_OCTETS_RXED_BOTTOM_COUNT_BOTTOM_Msk 0xFFFFFFFFUL 1497 /* ETH.OCTETS_RXED_TOP */ 1498 #define ETH_OCTETS_RXED_TOP_COUNT_TOP_Pos 0UL 1499 #define ETH_OCTETS_RXED_TOP_COUNT_TOP_Msk 0xFFFFUL 1500 /* ETH.FRAMES_RXED_OK */ 1501 #define ETH_FRAMES_RXED_OK_COUNT_OK_Pos 0UL 1502 #define ETH_FRAMES_RXED_OK_COUNT_OK_Msk 0xFFFFFFFFUL 1503 /* ETH.BROADCAST_RXED */ 1504 #define ETH_BROADCAST_RXED_COUNT_BROADCAST_Pos 0UL 1505 #define ETH_BROADCAST_RXED_COUNT_BROADCAST_Msk 0xFFFFFFFFUL 1506 /* ETH.MULTICAST_RXED */ 1507 #define ETH_MULTICAST_RXED_COUNT_MULTICAST_Pos 0UL 1508 #define ETH_MULTICAST_RXED_COUNT_MULTICAST_Msk 0xFFFFFFFFUL 1509 /* ETH.PAUSE_FRAMES_RXED */ 1510 #define ETH_PAUSE_FRAMES_RXED_COUNT_PAUSE_Pos 0UL 1511 #define ETH_PAUSE_FRAMES_RXED_COUNT_PAUSE_Msk 0xFFFFUL 1512 /* ETH.FRAMES_RXED_64 */ 1513 #define ETH_FRAMES_RXED_64_COUNT_64_Pos 0UL 1514 #define ETH_FRAMES_RXED_64_COUNT_64_Msk 0xFFFFFFFFUL 1515 /* ETH.FRAMES_RXED_65 */ 1516 #define ETH_FRAMES_RXED_65_COUNT_65_Pos 0UL 1517 #define ETH_FRAMES_RXED_65_COUNT_65_Msk 0xFFFFFFFFUL 1518 /* ETH.FRAMES_RXED_128 */ 1519 #define ETH_FRAMES_RXED_128_COUNT_128_Pos 0UL 1520 #define ETH_FRAMES_RXED_128_COUNT_128_Msk 0xFFFFFFFFUL 1521 /* ETH.FRAMES_RXED_256 */ 1522 #define ETH_FRAMES_RXED_256_COUNT_256_Pos 0UL 1523 #define ETH_FRAMES_RXED_256_COUNT_256_Msk 0xFFFFFFFFUL 1524 /* ETH.FRAMES_RXED_512 */ 1525 #define ETH_FRAMES_RXED_512_COUNT_512_Pos 0UL 1526 #define ETH_FRAMES_RXED_512_COUNT_512_Msk 0xFFFFFFFFUL 1527 /* ETH.FRAMES_RXED_1024 */ 1528 #define ETH_FRAMES_RXED_1024_COUNT_1024_Pos 0UL 1529 #define ETH_FRAMES_RXED_1024_COUNT_1024_Msk 0xFFFFFFFFUL 1530 /* ETH.FRAMES_RXED_1519 */ 1531 #define ETH_FRAMES_RXED_1519_COUNT_1519_Pos 0UL 1532 #define ETH_FRAMES_RXED_1519_COUNT_1519_Msk 0xFFFFFFFFUL 1533 /* ETH.UNDERSIZE_FRAMES */ 1534 #define ETH_UNDERSIZE_FRAMES_COUNT_UNDERSIZE_Pos 0UL 1535 #define ETH_UNDERSIZE_FRAMES_COUNT_UNDERSIZE_Msk 0x3FFUL 1536 /* ETH.EXCESSIVE_RX_LENGTH */ 1537 #define ETH_EXCESSIVE_RX_LENGTH_COUNT_OVERSIZE_Pos 0UL 1538 #define ETH_EXCESSIVE_RX_LENGTH_COUNT_OVERSIZE_Msk 0x3FFUL 1539 /* ETH.RX_JABBERS */ 1540 #define ETH_RX_JABBERS_COUNT_JABBERS_Pos 0UL 1541 #define ETH_RX_JABBERS_COUNT_JABBERS_Msk 0x3FFUL 1542 /* ETH.FCS_ERRORS */ 1543 #define ETH_FCS_ERRORS_COUNT_FCS_ERR_Pos 0UL 1544 #define ETH_FCS_ERRORS_COUNT_FCS_ERR_Msk 0x3FFUL 1545 /* ETH.RX_LENGTH_ERRORS */ 1546 #define ETH_RX_LENGTH_ERRORS_COUNT_LENGTH_ERR_Pos 0UL 1547 #define ETH_RX_LENGTH_ERRORS_COUNT_LENGTH_ERR_Msk 0x3FFUL 1548 /* ETH.RX_SYMBOL_ERRORS */ 1549 #define ETH_RX_SYMBOL_ERRORS_COUNT_SYMBOL_ERR_Pos 0UL 1550 #define ETH_RX_SYMBOL_ERRORS_COUNT_SYMBOL_ERR_Msk 0x3FFUL 1551 /* ETH.ALIGNMENT_ERRORS */ 1552 #define ETH_ALIGNMENT_ERRORS_COUNT_ALIGNMENT_ERROR_Pos 0UL 1553 #define ETH_ALIGNMENT_ERRORS_COUNT_ALIGNMENT_ERROR_Msk 0x3FFUL 1554 /* ETH.RX_RESOURCE_ERRORS */ 1555 #define ETH_RX_RESOURCE_ERRORS_COUNT_RESOURCE_ERR_Pos 0UL 1556 #define ETH_RX_RESOURCE_ERRORS_COUNT_RESOURCE_ERR_Msk 0x3FFFFUL 1557 /* ETH.RX_OVERRUNS */ 1558 #define ETH_RX_OVERRUNS_COUNT_OVERRUN_Pos 0UL 1559 #define ETH_RX_OVERRUNS_COUNT_OVERRUN_Msk 0x3FFUL 1560 /* ETH.RX_IP_CK_ERRORS */ 1561 #define ETH_RX_IP_CK_ERRORS_COUNT_IPCK_ERR_Pos 0UL 1562 #define ETH_RX_IP_CK_ERRORS_COUNT_IPCK_ERR_Msk 0xFFUL 1563 /* ETH.RX_TCP_CK_ERRORS */ 1564 #define ETH_RX_TCP_CK_ERRORS_COUNT_TCPCK_ERR_Pos 0UL 1565 #define ETH_RX_TCP_CK_ERRORS_COUNT_TCPCK_ERR_Msk 0xFFUL 1566 /* ETH.RX_UDP_CK_ERRORS */ 1567 #define ETH_RX_UDP_CK_ERRORS_COUNT_UDPCK_ERR_Pos 0UL 1568 #define ETH_RX_UDP_CK_ERRORS_COUNT_UDPCK_ERR_Msk 0xFFUL 1569 /* ETH.AUTO_FLUSHED_PKTS */ 1570 #define ETH_AUTO_FLUSHED_PKTS_COUNT_FLUSHED_Pos 0UL 1571 #define ETH_AUTO_FLUSHED_PKTS_COUNT_FLUSHED_Msk 0xFFFFUL 1572 /* ETH.TSU_TIMER_INCR_SUB_NSEC */ 1573 #define ETH_TSU_TIMER_INCR_SUB_NSEC_SUB_NS_INCR_Pos 0UL 1574 #define ETH_TSU_TIMER_INCR_SUB_NSEC_SUB_NS_INCR_Msk 0xFFFFUL 1575 #define ETH_TSU_TIMER_INCR_SUB_NSEC_SUB_NS_INCR_LSB_Pos 24UL 1576 #define ETH_TSU_TIMER_INCR_SUB_NSEC_SUB_NS_INCR_LSB_Msk 0xFF000000UL 1577 /* ETH.TSU_TIMER_MSB_SEC */ 1578 #define ETH_TSU_TIMER_MSB_SEC_TIMER_MSB_SEC_Pos 0UL 1579 #define ETH_TSU_TIMER_MSB_SEC_TIMER_MSB_SEC_Msk 0xFFFFUL 1580 /* ETH.TSU_STROBE_MSB_SEC */ 1581 #define ETH_TSU_STROBE_MSB_SEC_STROBE_MSB_SEC_Pos 0UL 1582 #define ETH_TSU_STROBE_MSB_SEC_STROBE_MSB_SEC_Msk 0xFFFFUL 1583 /* ETH.TSU_STROBE_SEC */ 1584 #define ETH_TSU_STROBE_SEC_STROBE_SEC_Pos 0UL 1585 #define ETH_TSU_STROBE_SEC_STROBE_SEC_Msk 0xFFFFFFFFUL 1586 /* ETH.TSU_STROBE_NSEC */ 1587 #define ETH_TSU_STROBE_NSEC_STROBE_NSEC_Pos 0UL 1588 #define ETH_TSU_STROBE_NSEC_STROBE_NSEC_Msk 0x3FFFFFFFUL 1589 /* ETH.TSU_TIMER_SEC */ 1590 #define ETH_TSU_TIMER_SEC_TIMER_SEC_Pos 0UL 1591 #define ETH_TSU_TIMER_SEC_TIMER_SEC_Msk 0xFFFFFFFFUL 1592 /* ETH.TSU_TIMER_NSEC */ 1593 #define ETH_TSU_TIMER_NSEC_TIMER_NSEC_Pos 0UL 1594 #define ETH_TSU_TIMER_NSEC_TIMER_NSEC_Msk 0x3FFFFFFFUL 1595 /* ETH.TSU_TIMER_ADJUST */ 1596 #define ETH_TSU_TIMER_ADJUST_INCREMENT_VALUE_Pos 0UL 1597 #define ETH_TSU_TIMER_ADJUST_INCREMENT_VALUE_Msk 0x3FFFFFFFUL 1598 #define ETH_TSU_TIMER_ADJUST_ADD_SUBTRACT_Pos 31UL 1599 #define ETH_TSU_TIMER_ADJUST_ADD_SUBTRACT_Msk 0x80000000UL 1600 /* ETH.TSU_TIMER_INCR */ 1601 #define ETH_TSU_TIMER_INCR_NS_INCREMENT_Pos 0UL 1602 #define ETH_TSU_TIMER_INCR_NS_INCREMENT_Msk 0xFFUL 1603 #define ETH_TSU_TIMER_INCR_ALT_NS_INCR_Pos 8UL 1604 #define ETH_TSU_TIMER_INCR_ALT_NS_INCR_Msk 0xFF00UL 1605 #define ETH_TSU_TIMER_INCR_NUM_INCS_Pos 16UL 1606 #define ETH_TSU_TIMER_INCR_NUM_INCS_Msk 0xFF0000UL 1607 /* ETH.TSU_PTP_TX_SEC */ 1608 #define ETH_TSU_PTP_TX_SEC_TIMER_PTP_SEC_Pos 0UL 1609 #define ETH_TSU_PTP_TX_SEC_TIMER_PTP_SEC_Msk 0xFFFFFFFFUL 1610 /* ETH.TSU_PTP_TX_NSEC */ 1611 #define ETH_TSU_PTP_TX_NSEC_TIMER_PTP_NSEC_Pos 0UL 1612 #define ETH_TSU_PTP_TX_NSEC_TIMER_PTP_NSEC_Msk 0x3FFFFFFFUL 1613 /* ETH.TSU_PTP_RX_SEC */ 1614 #define ETH_TSU_PTP_RX_SEC_TIMER_PTP_SEC_Pos 0UL 1615 #define ETH_TSU_PTP_RX_SEC_TIMER_PTP_SEC_Msk 0xFFFFFFFFUL 1616 /* ETH.TSU_PTP_RX_NSEC */ 1617 #define ETH_TSU_PTP_RX_NSEC_TIMER_PTP_NSEC_Pos 0UL 1618 #define ETH_TSU_PTP_RX_NSEC_TIMER_PTP_NSEC_Msk 0x3FFFFFFFUL 1619 /* ETH.TSU_PEER_TX_SEC */ 1620 #define ETH_TSU_PEER_TX_SEC_TIMER_PEER_SEC_Pos 0UL 1621 #define ETH_TSU_PEER_TX_SEC_TIMER_PEER_SEC_Msk 0xFFFFFFFFUL 1622 /* ETH.TSU_PEER_TX_NSEC */ 1623 #define ETH_TSU_PEER_TX_NSEC_TIMER_PEER_NSEC_Pos 0UL 1624 #define ETH_TSU_PEER_TX_NSEC_TIMER_PEER_NSEC_Msk 0x3FFFFFFFUL 1625 /* ETH.TSU_PEER_RX_SEC */ 1626 #define ETH_TSU_PEER_RX_SEC_TIMER_PEER_SEC_Pos 0UL 1627 #define ETH_TSU_PEER_RX_SEC_TIMER_PEER_SEC_Msk 0xFFFFFFFFUL 1628 /* ETH.TSU_PEER_RX_NSEC */ 1629 #define ETH_TSU_PEER_RX_NSEC_TIMER_PEER_NSEC_Pos 0UL 1630 #define ETH_TSU_PEER_RX_NSEC_TIMER_PEER_NSEC_Msk 0x3FFFFFFFUL 1631 /* ETH.PCS_CONTROL */ 1632 #define ETH_PCS_CONTROL_REMOVED_31_0_Pos 0UL 1633 #define ETH_PCS_CONTROL_REMOVED_31_0_Msk 0xFFFFFFFFUL 1634 /* ETH.PCS_STATUS */ 1635 #define ETH_PCS_STATUS_REMOVED_31_0_Pos 0UL 1636 #define ETH_PCS_STATUS_REMOVED_31_0_Msk 0xFFFFFFFFUL 1637 /* ETH.PCS_AN_ADV */ 1638 #define ETH_PCS_AN_ADV_REMOVED_31_0_Pos 0UL 1639 #define ETH_PCS_AN_ADV_REMOVED_31_0_Msk 0xFFFFFFFFUL 1640 /* ETH.PCS_AN_LP_BASE */ 1641 #define ETH_PCS_AN_LP_BASE_REMOVED_31_0_Pos 0UL 1642 #define ETH_PCS_AN_LP_BASE_REMOVED_31_0_Msk 0xFFFFFFFFUL 1643 /* ETH.PCS_AN_EXP */ 1644 #define ETH_PCS_AN_EXP_REMOVED_31_0_Pos 0UL 1645 #define ETH_PCS_AN_EXP_REMOVED_31_0_Msk 0xFFFFFFFFUL 1646 /* ETH.PCS_AN_NP_TX */ 1647 #define ETH_PCS_AN_NP_TX_REMOVED_31_0_Pos 0UL 1648 #define ETH_PCS_AN_NP_TX_REMOVED_31_0_Msk 0xFFFFFFFFUL 1649 /* ETH.PCS_AN_LP_NP */ 1650 #define ETH_PCS_AN_LP_NP_REMOVED_31_0_Pos 0UL 1651 #define ETH_PCS_AN_LP_NP_REMOVED_31_0_Msk 0xFFFFFFFFUL 1652 /* ETH.PCS_AN_EXT_STATUS */ 1653 #define ETH_PCS_AN_EXT_STATUS_REMOVED_31_0_Pos 0UL 1654 #define ETH_PCS_AN_EXT_STATUS_REMOVED_31_0_Msk 0xFFFFFFFFUL 1655 /* ETH.TX_PAUSE_QUANTUM1 */ 1656 #define ETH_TX_PAUSE_QUANTUM1_QUANTUM_P2_Pos 0UL 1657 #define ETH_TX_PAUSE_QUANTUM1_QUANTUM_P2_Msk 0xFFFFUL 1658 #define ETH_TX_PAUSE_QUANTUM1_QUANTUM_P3_Pos 16UL 1659 #define ETH_TX_PAUSE_QUANTUM1_QUANTUM_P3_Msk 0xFFFF0000UL 1660 /* ETH.TX_PAUSE_QUANTUM2 */ 1661 #define ETH_TX_PAUSE_QUANTUM2_QUANTUM_P4_Pos 0UL 1662 #define ETH_TX_PAUSE_QUANTUM2_QUANTUM_P4_Msk 0xFFFFUL 1663 #define ETH_TX_PAUSE_QUANTUM2_QUANTUM_P5_Pos 16UL 1664 #define ETH_TX_PAUSE_QUANTUM2_QUANTUM_P5_Msk 0xFFFF0000UL 1665 /* ETH.TX_PAUSE_QUANTUM3 */ 1666 #define ETH_TX_PAUSE_QUANTUM3_QUANTUM_P6_Pos 0UL 1667 #define ETH_TX_PAUSE_QUANTUM3_QUANTUM_P6_Msk 0xFFFFUL 1668 #define ETH_TX_PAUSE_QUANTUM3_QUANTUM_P7_Pos 16UL 1669 #define ETH_TX_PAUSE_QUANTUM3_QUANTUM_P7_Msk 0xFFFF0000UL 1670 /* ETH.RX_LPI */ 1671 #define ETH_RX_LPI_COUNT_LPI_Pos 0UL 1672 #define ETH_RX_LPI_COUNT_LPI_Msk 0xFFFFUL 1673 /* ETH.RX_LPI_TIME */ 1674 #define ETH_RX_LPI_TIME_LPI_TIME_Pos 0UL 1675 #define ETH_RX_LPI_TIME_LPI_TIME_Msk 0xFFFFFFUL 1676 /* ETH.TX_LPI */ 1677 #define ETH_TX_LPI_COUNT_LPI_Pos 0UL 1678 #define ETH_TX_LPI_COUNT_LPI_Msk 0xFFFFUL 1679 /* ETH.TX_LPI_TIME */ 1680 #define ETH_TX_LPI_TIME_LPI_TIME_Pos 0UL 1681 #define ETH_TX_LPI_TIME_LPI_TIME_Msk 0xFFFFFFUL 1682 /* ETH.DESIGNCFG_DEBUG1 */ 1683 #define ETH_DESIGNCFG_DEBUG1_NO_PCS_Pos 0UL 1684 #define ETH_DESIGNCFG_DEBUG1_NO_PCS_Msk 0x1UL 1685 #define ETH_DESIGNCFG_DEBUG1_EXCLUDE_QBV_Pos 1UL 1686 #define ETH_DESIGNCFG_DEBUG1_EXCLUDE_QBV_Msk 0x2UL 1687 #define ETH_DESIGNCFG_DEBUG1_RESERVED_2_Pos 2UL 1688 #define ETH_DESIGNCFG_DEBUG1_RESERVED_2_Msk 0xCUL 1689 #define ETH_DESIGNCFG_DEBUG1_INT_LOOPBACK_Pos 4UL 1690 #define ETH_DESIGNCFG_DEBUG1_INT_LOOPBACK_Msk 0x10UL 1691 #define ETH_DESIGNCFG_DEBUG1_RESERVED_5_Pos 5UL 1692 #define ETH_DESIGNCFG_DEBUG1_RESERVED_5_Msk 0x20UL 1693 #define ETH_DESIGNCFG_DEBUG1_EXT_FIFO_INTERFACE_Pos 6UL 1694 #define ETH_DESIGNCFG_DEBUG1_EXT_FIFO_INTERFACE_Msk 0x40UL 1695 #define ETH_DESIGNCFG_DEBUG1_RESERVED_7_Pos 7UL 1696 #define ETH_DESIGNCFG_DEBUG1_RESERVED_7_Msk 0x80UL 1697 #define ETH_DESIGNCFG_DEBUG1_RESERVED_8_Pos 8UL 1698 #define ETH_DESIGNCFG_DEBUG1_RESERVED_8_Msk 0x100UL 1699 #define ETH_DESIGNCFG_DEBUG1_USER_IO_Pos 9UL 1700 #define ETH_DESIGNCFG_DEBUG1_USER_IO_Msk 0x200UL 1701 #define ETH_DESIGNCFG_DEBUG1_USER_OUT_WIDTH_Pos 10UL 1702 #define ETH_DESIGNCFG_DEBUG1_USER_OUT_WIDTH_Msk 0x7C00UL 1703 #define ETH_DESIGNCFG_DEBUG1_USER_IN_WIDTH_Pos 15UL 1704 #define ETH_DESIGNCFG_DEBUG1_USER_IN_WIDTH_Msk 0xF8000UL 1705 #define ETH_DESIGNCFG_DEBUG1_RESERVED_20_Pos 20UL 1706 #define ETH_DESIGNCFG_DEBUG1_RESERVED_20_Msk 0x100000UL 1707 #define ETH_DESIGNCFG_DEBUG1_NO_STATS_Pos 21UL 1708 #define ETH_DESIGNCFG_DEBUG1_NO_STATS_Msk 0x200000UL 1709 #define ETH_DESIGNCFG_DEBUG1_NO_SNAPSHOT_Pos 22UL 1710 #define ETH_DESIGNCFG_DEBUG1_NO_SNAPSHOT_Msk 0x400000UL 1711 #define ETH_DESIGNCFG_DEBUG1_IRQ_READ_CLEAR_Pos 23UL 1712 #define ETH_DESIGNCFG_DEBUG1_IRQ_READ_CLEAR_Msk 0x800000UL 1713 #define ETH_DESIGNCFG_DEBUG1_EXCLUDE_CBS_Pos 24UL 1714 #define ETH_DESIGNCFG_DEBUG1_EXCLUDE_CBS_Msk 0x1000000UL 1715 #define ETH_DESIGNCFG_DEBUG1_DMA_BUS_WIDTH_Pos 25UL 1716 #define ETH_DESIGNCFG_DEBUG1_DMA_BUS_WIDTH_Msk 0xE000000UL 1717 #define ETH_DESIGNCFG_DEBUG1_AXI_CACHE_VALUE_Pos 28UL 1718 #define ETH_DESIGNCFG_DEBUG1_AXI_CACHE_VALUE_Msk 0xF0000000UL 1719 /* ETH.DESIGNCFG_DEBUG2 */ 1720 #define ETH_DESIGNCFG_DEBUG2_JUMBO_MAX_LENGTH_Pos 0UL 1721 #define ETH_DESIGNCFG_DEBUG2_JUMBO_MAX_LENGTH_Msk 0x3FFFUL 1722 #define ETH_DESIGNCFG_DEBUG2_HPROT_VALUE_Pos 16UL 1723 #define ETH_DESIGNCFG_DEBUG2_HPROT_VALUE_Msk 0xF0000UL 1724 #define ETH_DESIGNCFG_DEBUG2_RX_PKT_BUFFER_Pos 20UL 1725 #define ETH_DESIGNCFG_DEBUG2_RX_PKT_BUFFER_Msk 0x100000UL 1726 #define ETH_DESIGNCFG_DEBUG2_TX_PKT_BUFFER_Pos 21UL 1727 #define ETH_DESIGNCFG_DEBUG2_TX_PKT_BUFFER_Msk 0x200000UL 1728 #define ETH_DESIGNCFG_DEBUG2_RX_PBUF_ADDR_Pos 22UL 1729 #define ETH_DESIGNCFG_DEBUG2_RX_PBUF_ADDR_Msk 0x3C00000UL 1730 #define ETH_DESIGNCFG_DEBUG2_TX_PBUF_ADDR_Pos 26UL 1731 #define ETH_DESIGNCFG_DEBUG2_TX_PBUF_ADDR_Msk 0x3C000000UL 1732 #define ETH_DESIGNCFG_DEBUG2_AXI_Pos 30UL 1733 #define ETH_DESIGNCFG_DEBUG2_AXI_Msk 0x40000000UL 1734 #define ETH_DESIGNCFG_DEBUG2_SPRAM_Pos 31UL 1735 #define ETH_DESIGNCFG_DEBUG2_SPRAM_Msk 0x80000000UL 1736 /* ETH.DESIGNCFG_DEBUG3 */ 1737 #define ETH_DESIGNCFG_DEBUG3_NUM_SPEC_ADD_FILTERS_Pos 24UL 1738 #define ETH_DESIGNCFG_DEBUG3_NUM_SPEC_ADD_FILTERS_Msk 0x3F000000UL 1739 /* ETH.DESIGNCFG_DEBUG4 */ 1740 #define ETH_DESIGNCFG_DEBUG4_RESERVED_31_0_Pos 0UL 1741 #define ETH_DESIGNCFG_DEBUG4_RESERVED_31_0_Msk 0xFFFFFFFFUL 1742 /* ETH.DESIGNCFG_DEBUG5 */ 1743 #define ETH_DESIGNCFG_DEBUG5_RX_FIFO_CNT_WIDTH_Pos 0UL 1744 #define ETH_DESIGNCFG_DEBUG5_RX_FIFO_CNT_WIDTH_Msk 0xFUL 1745 #define ETH_DESIGNCFG_DEBUG5_TX_FIFO_CNT_WIDTH_Pos 4UL 1746 #define ETH_DESIGNCFG_DEBUG5_TX_FIFO_CNT_WIDTH_Msk 0xF0UL 1747 #define ETH_DESIGNCFG_DEBUG5_TSU_Pos 8UL 1748 #define ETH_DESIGNCFG_DEBUG5_TSU_Msk 0x100UL 1749 #define ETH_DESIGNCFG_DEBUG5_PHY_IDENT_Pos 9UL 1750 #define ETH_DESIGNCFG_DEBUG5_PHY_IDENT_Msk 0x200UL 1751 #define ETH_DESIGNCFG_DEBUG5_DMA_BUS_WIDTH_DEF_Pos 10UL 1752 #define ETH_DESIGNCFG_DEBUG5_DMA_BUS_WIDTH_DEF_Msk 0xC00UL 1753 #define ETH_DESIGNCFG_DEBUG5_MDC_CLOCK_DIV_Pos 12UL 1754 #define ETH_DESIGNCFG_DEBUG5_MDC_CLOCK_DIV_Msk 0x7000UL 1755 #define ETH_DESIGNCFG_DEBUG5_ENDIAN_SWAP_DEF_Pos 15UL 1756 #define ETH_DESIGNCFG_DEBUG5_ENDIAN_SWAP_DEF_Msk 0x18000UL 1757 #define ETH_DESIGNCFG_DEBUG5_RX_PBUF_SIZE_DEF_Pos 17UL 1758 #define ETH_DESIGNCFG_DEBUG5_RX_PBUF_SIZE_DEF_Msk 0x60000UL 1759 #define ETH_DESIGNCFG_DEBUG5_TX_PBUF_SIZE_DEF_Pos 19UL 1760 #define ETH_DESIGNCFG_DEBUG5_TX_PBUF_SIZE_DEF_Msk 0x80000UL 1761 #define ETH_DESIGNCFG_DEBUG5_RX_BUFFER_LENGTH_DEF_Pos 20UL 1762 #define ETH_DESIGNCFG_DEBUG5_RX_BUFFER_LENGTH_DEF_Msk 0xFF00000UL 1763 #define ETH_DESIGNCFG_DEBUG5_TSU_CLK_Pos 28UL 1764 #define ETH_DESIGNCFG_DEBUG5_TSU_CLK_Msk 0x10000000UL 1765 #define ETH_DESIGNCFG_DEBUG5_AXI_PROT_VALUE_Pos 29UL 1766 #define ETH_DESIGNCFG_DEBUG5_AXI_PROT_VALUE_Msk 0xE0000000UL 1767 /* ETH.DESIGNCFG_DEBUG6 */ 1768 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE1_Pos 1UL 1769 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE1_Msk 0x2UL 1770 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE2_Pos 2UL 1771 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE2_Msk 0x4UL 1772 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE3_Pos 3UL 1773 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE3_Msk 0x8UL 1774 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE4_Pos 4UL 1775 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE4_Msk 0x10UL 1776 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE5_Pos 5UL 1777 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE5_Msk 0x20UL 1778 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE6_Pos 6UL 1779 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE6_Msk 0x40UL 1780 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE7_Pos 7UL 1781 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE7_Msk 0x80UL 1782 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE8_Pos 8UL 1783 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE8_Msk 0x100UL 1784 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE9_Pos 9UL 1785 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE9_Msk 0x200UL 1786 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE10_Pos 10UL 1787 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE10_Msk 0x400UL 1788 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE11_Pos 11UL 1789 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE11_Msk 0x800UL 1790 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE12_Pos 12UL 1791 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE12_Msk 0x1000UL 1792 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE13_Pos 13UL 1793 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE13_Msk 0x2000UL 1794 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE14_Pos 14UL 1795 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE14_Msk 0x4000UL 1796 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE15_Pos 15UL 1797 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE15_Msk 0x8000UL 1798 #define ETH_DESIGNCFG_DEBUG6_TX_PBUF_QUEUE_SEGMENT_SIZE_Pos 16UL 1799 #define ETH_DESIGNCFG_DEBUG6_TX_PBUF_QUEUE_SEGMENT_SIZE_Msk 0xF0000UL 1800 #define ETH_DESIGNCFG_DEBUG6_EXT_TSU_TIMER_Pos 20UL 1801 #define ETH_DESIGNCFG_DEBUG6_EXT_TSU_TIMER_Msk 0x100000UL 1802 #define ETH_DESIGNCFG_DEBUG6_TX_ADD_FIFO_IF_Pos 21UL 1803 #define ETH_DESIGNCFG_DEBUG6_TX_ADD_FIFO_IF_Msk 0x200000UL 1804 #define ETH_DESIGNCFG_DEBUG6_HOST_IF_SOFT_SELECT_Pos 22UL 1805 #define ETH_DESIGNCFG_DEBUG6_HOST_IF_SOFT_SELECT_Msk 0x400000UL 1806 #define ETH_DESIGNCFG_DEBUG6_DMA_ADDR_WIDTH_IS_64B_Pos 23UL 1807 #define ETH_DESIGNCFG_DEBUG6_DMA_ADDR_WIDTH_IS_64B_Msk 0x800000UL 1808 #define ETH_DESIGNCFG_DEBUG6_PFC_MULTI_QUANTUM_Pos 24UL 1809 #define ETH_DESIGNCFG_DEBUG6_PFC_MULTI_QUANTUM_Msk 0x1000000UL 1810 #define ETH_DESIGNCFG_DEBUG6_PBUF_CUTTHRU_Pos 25UL 1811 #define ETH_DESIGNCFG_DEBUG6_PBUF_CUTTHRU_Msk 0x2000000UL 1812 #define ETH_DESIGNCFG_DEBUG6_PBUF_RSC_Pos 26UL 1813 #define ETH_DESIGNCFG_DEBUG6_PBUF_RSC_Msk 0x4000000UL 1814 #define ETH_DESIGNCFG_DEBUG6_PBUF_LSO_Pos 27UL 1815 #define ETH_DESIGNCFG_DEBUG6_PBUF_LSO_Msk 0x8000000UL 1816 /* ETH.DESIGNCFG_DEBUG7 */ 1817 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q0_Pos 0UL 1818 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q0_Msk 0xFUL 1819 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q1_Pos 4UL 1820 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q1_Msk 0xF0UL 1821 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q2_Pos 8UL 1822 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q2_Msk 0xF00UL 1823 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q3_Pos 12UL 1824 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q3_Msk 0xF000UL 1825 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q4_Pos 16UL 1826 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q4_Msk 0xF0000UL 1827 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q5_Pos 20UL 1828 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q5_Msk 0xF00000UL 1829 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q6_Pos 24UL 1830 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q6_Msk 0xF000000UL 1831 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q7_Pos 28UL 1832 #define ETH_DESIGNCFG_DEBUG7_X_PBUF_NUM_SEGMENTS_Q7_Msk 0xF0000000UL 1833 /* ETH.DESIGNCFG_DEBUG8 */ 1834 #define ETH_DESIGNCFG_DEBUG8_NUM_SCR2_COMPARE_REGS_Pos 0UL 1835 #define ETH_DESIGNCFG_DEBUG8_NUM_SCR2_COMPARE_REGS_Msk 0xFFUL 1836 #define ETH_DESIGNCFG_DEBUG8_NUM_SCR2_ETHTYPE_REGS_Pos 8UL 1837 #define ETH_DESIGNCFG_DEBUG8_NUM_SCR2_ETHTYPE_REGS_Msk 0xFF00UL 1838 #define ETH_DESIGNCFG_DEBUG8_NUM_TYPE2_SCREENERS_Pos 16UL 1839 #define ETH_DESIGNCFG_DEBUG8_NUM_TYPE2_SCREENERS_Msk 0xFF0000UL 1840 #define ETH_DESIGNCFG_DEBUG8_NUM_TYPE1_SCREENERS_Pos 24UL 1841 #define ETH_DESIGNCFG_DEBUG8_NUM_TYPE1_SCREENERS_Msk 0xFF000000UL 1842 /* ETH.DESIGNCFG_DEBUG9 */ 1843 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q8_Pos 0UL 1844 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q8_Msk 0xFUL 1845 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q9_Pos 4UL 1846 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q9_Msk 0xF0UL 1847 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q10_Pos 8UL 1848 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q10_Msk 0xF00UL 1849 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q11_Pos 12UL 1850 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q11_Msk 0xF000UL 1851 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q12_Pos 16UL 1852 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q12_Msk 0xF0000UL 1853 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q13_Pos 20UL 1854 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q13_Msk 0xF00000UL 1855 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q14_Pos 24UL 1856 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q14_Msk 0xF000000UL 1857 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q15_Pos 28UL 1858 #define ETH_DESIGNCFG_DEBUG9_TX_PBUF_NUM_SEGMENTS_Q15_Msk 0xF0000000UL 1859 /* ETH.DESIGNCFG_DEBUG10 */ 1860 #define ETH_DESIGNCFG_DEBUG10_AXI_RX_DESCR_WR_BUFF_BITS_Pos 0UL 1861 #define ETH_DESIGNCFG_DEBUG10_AXI_RX_DESCR_WR_BUFF_BITS_Msk 0xFUL 1862 #define ETH_DESIGNCFG_DEBUG10_AXI_TX_DESCR_WR_BUFF_BITS_Pos 4UL 1863 #define ETH_DESIGNCFG_DEBUG10_AXI_TX_DESCR_WR_BUFF_BITS_Msk 0xF0UL 1864 #define ETH_DESIGNCFG_DEBUG10_AXI_RX_DESCR_RD_BUFF_BITS_Pos 8UL 1865 #define ETH_DESIGNCFG_DEBUG10_AXI_RX_DESCR_RD_BUFF_BITS_Msk 0xF00UL 1866 #define ETH_DESIGNCFG_DEBUG10_AXI_TX_DESCR_RD_BUFF_BITS_Pos 12UL 1867 #define ETH_DESIGNCFG_DEBUG10_AXI_TX_DESCR_RD_BUFF_BITS_Msk 0xF000UL 1868 #define ETH_DESIGNCFG_DEBUG10_AXI_ACCESS_PIPELINE_BITS_Pos 16UL 1869 #define ETH_DESIGNCFG_DEBUG10_AXI_ACCESS_PIPELINE_BITS_Msk 0xF0000UL 1870 #define ETH_DESIGNCFG_DEBUG10_RX_PBUF_DATA_Pos 20UL 1871 #define ETH_DESIGNCFG_DEBUG10_RX_PBUF_DATA_Msk 0xF00000UL 1872 #define ETH_DESIGNCFG_DEBUG10_TX_PBUF_DATA_Pos 24UL 1873 #define ETH_DESIGNCFG_DEBUG10_TX_PBUF_DATA_Msk 0xF000000UL 1874 #define ETH_DESIGNCFG_DEBUG10_EMAC_BUS_WIDTH_Pos 28UL 1875 #define ETH_DESIGNCFG_DEBUG10_EMAC_BUS_WIDTH_Msk 0xF0000000UL 1876 /* ETH.SPEC_ADD5_BOTTOM */ 1877 #define ETH_SPEC_ADD5_BOTTOM_RESERVED_31_0_Pos 0UL 1878 #define ETH_SPEC_ADD5_BOTTOM_RESERVED_31_0_Msk 0xFFFFFFFFUL 1879 /* ETH.SPEC_ADD5_TOP */ 1880 #define ETH_SPEC_ADD5_TOP_RESERVED_31_0_Pos 0UL 1881 #define ETH_SPEC_ADD5_TOP_RESERVED_31_0_Msk 0xFFFFFFFFUL 1882 /* ETH.SPEC_ADD36_BOTTOM */ 1883 #define ETH_SPEC_ADD36_BOTTOM_RESERVED_31_0_Pos 0UL 1884 #define ETH_SPEC_ADD36_BOTTOM_RESERVED_31_0_Msk 0xFFFFFFFFUL 1885 /* ETH.SPEC_ADD36_TOP */ 1886 #define ETH_SPEC_ADD36_TOP_RESERVED_31_0_Pos 0UL 1887 #define ETH_SPEC_ADD36_TOP_RESERVED_31_0_Msk 0xFFFFFFFFUL 1888 /* ETH.INT_Q1_STATUS */ 1889 #define ETH_INT_Q1_STATUS_RECEIVE_COMPLETE_Pos 1UL 1890 #define ETH_INT_Q1_STATUS_RECEIVE_COMPLETE_Msk 0x2UL 1891 #define ETH_INT_Q1_STATUS_RX_USED_BIT_READ_Pos 2UL 1892 #define ETH_INT_Q1_STATUS_RX_USED_BIT_READ_Msk 0x4UL 1893 #define ETH_INT_Q1_STATUS_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_Pos 5UL 1894 #define ETH_INT_Q1_STATUS_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_Msk 0x20UL 1895 #define ETH_INT_Q1_STATUS_AMBA_ERROR_Pos 6UL 1896 #define ETH_INT_Q1_STATUS_AMBA_ERROR_Msk 0x40UL 1897 #define ETH_INT_Q1_STATUS_TRANSMIT_COMPLETE_Pos 7UL 1898 #define ETH_INT_Q1_STATUS_TRANSMIT_COMPLETE_Msk 0x80UL 1899 #define ETH_INT_Q1_STATUS_RESP_NOT_OK_Pos 11UL 1900 #define ETH_INT_Q1_STATUS_RESP_NOT_OK_Msk 0x800UL 1901 /* ETH.INT_Q2_STATUS */ 1902 #define ETH_INT_Q2_STATUS_RECEIVE_COMPLETE_Pos 1UL 1903 #define ETH_INT_Q2_STATUS_RECEIVE_COMPLETE_Msk 0x2UL 1904 #define ETH_INT_Q2_STATUS_RX_USED_BIT_READ_Pos 2UL 1905 #define ETH_INT_Q2_STATUS_RX_USED_BIT_READ_Msk 0x4UL 1906 #define ETH_INT_Q2_STATUS_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_Pos 5UL 1907 #define ETH_INT_Q2_STATUS_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_Msk 0x20UL 1908 #define ETH_INT_Q2_STATUS_AMBA_ERROR_Pos 6UL 1909 #define ETH_INT_Q2_STATUS_AMBA_ERROR_Msk 0x40UL 1910 #define ETH_INT_Q2_STATUS_TRANSMIT_COMPLETE_Pos 7UL 1911 #define ETH_INT_Q2_STATUS_TRANSMIT_COMPLETE_Msk 0x80UL 1912 #define ETH_INT_Q2_STATUS_RESP_NOT_OK_Pos 11UL 1913 #define ETH_INT_Q2_STATUS_RESP_NOT_OK_Msk 0x800UL 1914 /* ETH.INT_Q3_STATUS */ 1915 #define ETH_INT_Q3_STATUS_REMOVED_31_0_Pos 0UL 1916 #define ETH_INT_Q3_STATUS_REMOVED_31_0_Msk 0xFFFFFFFFUL 1917 /* ETH.INT_Q15_STATUS */ 1918 #define ETH_INT_Q15_STATUS_REMOVED_31_0_Pos 0UL 1919 #define ETH_INT_Q15_STATUS_REMOVED_31_0_Msk 0xFFFFFFFFUL 1920 /* ETH.TRANSMIT_Q1_PTR */ 1921 #define ETH_TRANSMIT_Q1_PTR_DMA_TX_DIS_Q_Pos 0UL 1922 #define ETH_TRANSMIT_Q1_PTR_DMA_TX_DIS_Q_Msk 0x1UL 1923 #define ETH_TRANSMIT_Q1_PTR_DMA_TX_Q_PTR_Pos 2UL 1924 #define ETH_TRANSMIT_Q1_PTR_DMA_TX_Q_PTR_Msk 0xFFFFFFFCUL 1925 /* ETH.TRANSMIT_Q2_PTR */ 1926 #define ETH_TRANSMIT_Q2_PTR_DMA_TX_DIS_Q_Pos 0UL 1927 #define ETH_TRANSMIT_Q2_PTR_DMA_TX_DIS_Q_Msk 0x1UL 1928 #define ETH_TRANSMIT_Q2_PTR_DMA_TX_Q_PTR_Pos 2UL 1929 #define ETH_TRANSMIT_Q2_PTR_DMA_TX_Q_PTR_Msk 0xFFFFFFFCUL 1930 /* ETH.TRANSMIT_Q3_PTR */ 1931 #define ETH_TRANSMIT_Q3_PTR_REMOVED_31_0_Pos 0UL 1932 #define ETH_TRANSMIT_Q3_PTR_REMOVED_31_0_Msk 0xFFFFFFFFUL 1933 /* ETH.TRANSMIT_Q15_PTR */ 1934 #define ETH_TRANSMIT_Q15_PTR_REMOVED_31_0_Pos 0UL 1935 #define ETH_TRANSMIT_Q15_PTR_REMOVED_31_0_Msk 0xFFFFFFFFUL 1936 /* ETH.RECEIVE_Q1_PTR */ 1937 #define ETH_RECEIVE_Q1_PTR_DMA_RX_DIS_Q_Pos 0UL 1938 #define ETH_RECEIVE_Q1_PTR_DMA_RX_DIS_Q_Msk 0x1UL 1939 #define ETH_RECEIVE_Q1_PTR_DMA_RX_Q_PTR_Pos 2UL 1940 #define ETH_RECEIVE_Q1_PTR_DMA_RX_Q_PTR_Msk 0xFFFFFFFCUL 1941 /* ETH.RECEIVE_Q2_PTR */ 1942 #define ETH_RECEIVE_Q2_PTR_DMA_RX_DIS_Q_Pos 0UL 1943 #define ETH_RECEIVE_Q2_PTR_DMA_RX_DIS_Q_Msk 0x1UL 1944 #define ETH_RECEIVE_Q2_PTR_DMA_RX_Q_PTR_Pos 2UL 1945 #define ETH_RECEIVE_Q2_PTR_DMA_RX_Q_PTR_Msk 0xFFFFFFFCUL 1946 /* ETH.RECEIVE_Q3_PTR */ 1947 #define ETH_RECEIVE_Q3_PTR_REMOVED_31_0_Pos 0UL 1948 #define ETH_RECEIVE_Q3_PTR_REMOVED_31_0_Msk 0xFFFFFFFFUL 1949 /* ETH.RECEIVE_Q7_PTR */ 1950 #define ETH_RECEIVE_Q7_PTR_REMOVED_31_0_Pos 0UL 1951 #define ETH_RECEIVE_Q7_PTR_REMOVED_31_0_Msk 0xFFFFFFFFUL 1952 /* ETH.DMA_RXBUF_SIZE_Q1 */ 1953 #define ETH_DMA_RXBUF_SIZE_Q1_DMA_RX_Q_BUF_SIZE_Pos 0UL 1954 #define ETH_DMA_RXBUF_SIZE_Q1_DMA_RX_Q_BUF_SIZE_Msk 0xFFUL 1955 /* ETH.DMA_RXBUF_SIZE_Q2 */ 1956 #define ETH_DMA_RXBUF_SIZE_Q2_DMA_RX_Q_BUF_SIZE_Pos 0UL 1957 #define ETH_DMA_RXBUF_SIZE_Q2_DMA_RX_Q_BUF_SIZE_Msk 0xFFUL 1958 /* ETH.DMA_RXBUF_SIZE_Q3 */ 1959 #define ETH_DMA_RXBUF_SIZE_Q3_REMOVED_31_0_Pos 0UL 1960 #define ETH_DMA_RXBUF_SIZE_Q3_REMOVED_31_0_Msk 0xFFFFFFFFUL 1961 /* ETH.DMA_RXBUF_SIZE_Q7 */ 1962 #define ETH_DMA_RXBUF_SIZE_Q7_REMOVED_31_0_Pos 0UL 1963 #define ETH_DMA_RXBUF_SIZE_Q7_REMOVED_31_0_Msk 0xFFFFFFFFUL 1964 /* ETH.CBS_CONTROL */ 1965 #define ETH_CBS_CONTROL_CBS_ENABLE_QUEUE_A_Pos 0UL 1966 #define ETH_CBS_CONTROL_CBS_ENABLE_QUEUE_A_Msk 0x1UL 1967 #define ETH_CBS_CONTROL_CBS_ENABLE_QUEUE_B_Pos 1UL 1968 #define ETH_CBS_CONTROL_CBS_ENABLE_QUEUE_B_Msk 0x2UL 1969 /* ETH.CBS_IDLESLOPE_Q_A */ 1970 #define ETH_CBS_IDLESLOPE_Q_A_IDLESLOPE_A_Pos 0UL 1971 #define ETH_CBS_IDLESLOPE_Q_A_IDLESLOPE_A_Msk 0xFFFFFFFFUL 1972 /* ETH.CBS_IDLESLOPE_Q_B */ 1973 #define ETH_CBS_IDLESLOPE_Q_B_IDLESLOPE_B_Pos 0UL 1974 #define ETH_CBS_IDLESLOPE_Q_B_IDLESLOPE_B_Msk 0xFFFFFFFFUL 1975 /* ETH.UPPER_TX_Q_BASE_ADDR */ 1976 #define ETH_UPPER_TX_Q_BASE_ADDR_UPPER_TX_Q_BASE_ADDR_Pos 0UL 1977 #define ETH_UPPER_TX_Q_BASE_ADDR_UPPER_TX_Q_BASE_ADDR_Msk 0xFFFFFFFFUL 1978 /* ETH.TX_BD_CONTROL */ 1979 #define ETH_TX_BD_CONTROL_TX_BD_TS_MODE_Pos 4UL 1980 #define ETH_TX_BD_CONTROL_TX_BD_TS_MODE_Msk 0x30UL 1981 /* ETH.RX_BD_CONTROL */ 1982 #define ETH_RX_BD_CONTROL_RX_BD_TS_MODE_Pos 4UL 1983 #define ETH_RX_BD_CONTROL_RX_BD_TS_MODE_Msk 0x30UL 1984 /* ETH.UPPER_RX_Q_BASE_ADDR */ 1985 #define ETH_UPPER_RX_Q_BASE_ADDR_UPPER_RX_Q_BASE_ADDR_Pos 0UL 1986 #define ETH_UPPER_RX_Q_BASE_ADDR_UPPER_RX_Q_BASE_ADDR_Msk 0xFFFFFFFFUL 1987 /* ETH.HIDDEN_REG0 */ 1988 #define ETH_HIDDEN_REG0_HIDDEN0_FIELD_Pos 0UL 1989 #define ETH_HIDDEN_REG0_HIDDEN0_FIELD_Msk 0xFFFFFFFFUL 1990 /* ETH.HIDDEN_REG1 */ 1991 #define ETH_HIDDEN_REG1_HIDDEN1_FIELD_Pos 0UL 1992 #define ETH_HIDDEN_REG1_HIDDEN1_FIELD_Msk 0xFFFFFFFFUL 1993 /* ETH.HIDDEN_REG2 */ 1994 #define ETH_HIDDEN_REG2_HIDDEN2_FIELD_Pos 0UL 1995 #define ETH_HIDDEN_REG2_HIDDEN2_FIELD_Msk 0xFFFFFFFFUL 1996 /* ETH.HIDDEN_REG3 */ 1997 #define ETH_HIDDEN_REG3_HIDDEN3_FIELD_Pos 0UL 1998 #define ETH_HIDDEN_REG3_HIDDEN3_FIELD_Msk 0xFUL 1999 /* ETH.HIDDEN_REG4 */ 2000 #define ETH_HIDDEN_REG4_HIDDEN4_FIELD_L_Pos 0UL 2001 #define ETH_HIDDEN_REG4_HIDDEN4_FIELD_L_Msk 0x1FFUL 2002 #define ETH_HIDDEN_REG4_HIDDEN4_FIELD_H_Pos 16UL 2003 #define ETH_HIDDEN_REG4_HIDDEN4_FIELD_H_Msk 0x1FF0000UL 2004 /* ETH.HIDDEN_REG5 */ 2005 #define ETH_HIDDEN_REG5_HIDDEN5_FIELD_L_Pos 0UL 2006 #define ETH_HIDDEN_REG5_HIDDEN5_FIELD_L_Msk 0x1FFUL 2007 #define ETH_HIDDEN_REG5_HIDDEN5_FIELD_H_Pos 16UL 2008 #define ETH_HIDDEN_REG5_HIDDEN5_FIELD_H_Msk 0x1FF0000UL 2009 /* ETH.SCREENING_TYPE_1_REGISTER_0 */ 2010 #define ETH_SCREENING_TYPE_1_REGISTER_0_QUEUE_NUMBER_Pos 0UL 2011 #define ETH_SCREENING_TYPE_1_REGISTER_0_QUEUE_NUMBER_Msk 0xFUL 2012 #define ETH_SCREENING_TYPE_1_REGISTER_0_DSTC_MATCH_Pos 4UL 2013 #define ETH_SCREENING_TYPE_1_REGISTER_0_DSTC_MATCH_Msk 0xFF0UL 2014 #define ETH_SCREENING_TYPE_1_REGISTER_0_UDP_PORT_MATCH_Pos 12UL 2015 #define ETH_SCREENING_TYPE_1_REGISTER_0_UDP_PORT_MATCH_Msk 0xFFFF000UL 2016 #define ETH_SCREENING_TYPE_1_REGISTER_0_DSTC_ENABLE_Pos 28UL 2017 #define ETH_SCREENING_TYPE_1_REGISTER_0_DSTC_ENABLE_Msk 0x10000000UL 2018 #define ETH_SCREENING_TYPE_1_REGISTER_0_UDP_PORT_MATCH_ENABLE_Pos 29UL 2019 #define ETH_SCREENING_TYPE_1_REGISTER_0_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2020 /* ETH.SCREENING_TYPE_1_REGISTER_1 */ 2021 #define ETH_SCREENING_TYPE_1_REGISTER_1_QUEUE_NUMBER_Pos 0UL 2022 #define ETH_SCREENING_TYPE_1_REGISTER_1_QUEUE_NUMBER_Msk 0xFUL 2023 #define ETH_SCREENING_TYPE_1_REGISTER_1_DSTC_MATCH_Pos 4UL 2024 #define ETH_SCREENING_TYPE_1_REGISTER_1_DSTC_MATCH_Msk 0xFF0UL 2025 #define ETH_SCREENING_TYPE_1_REGISTER_1_UDP_PORT_MATCH_Pos 12UL 2026 #define ETH_SCREENING_TYPE_1_REGISTER_1_UDP_PORT_MATCH_Msk 0xFFFF000UL 2027 #define ETH_SCREENING_TYPE_1_REGISTER_1_DSTC_ENABLE_Pos 28UL 2028 #define ETH_SCREENING_TYPE_1_REGISTER_1_DSTC_ENABLE_Msk 0x10000000UL 2029 #define ETH_SCREENING_TYPE_1_REGISTER_1_UDP_PORT_MATCH_ENABLE_Pos 29UL 2030 #define ETH_SCREENING_TYPE_1_REGISTER_1_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2031 /* ETH.SCREENING_TYPE_1_REGISTER_2 */ 2032 #define ETH_SCREENING_TYPE_1_REGISTER_2_QUEUE_NUMBER_Pos 0UL 2033 #define ETH_SCREENING_TYPE_1_REGISTER_2_QUEUE_NUMBER_Msk 0xFUL 2034 #define ETH_SCREENING_TYPE_1_REGISTER_2_DSTC_MATCH_Pos 4UL 2035 #define ETH_SCREENING_TYPE_1_REGISTER_2_DSTC_MATCH_Msk 0xFF0UL 2036 #define ETH_SCREENING_TYPE_1_REGISTER_2_UDP_PORT_MATCH_Pos 12UL 2037 #define ETH_SCREENING_TYPE_1_REGISTER_2_UDP_PORT_MATCH_Msk 0xFFFF000UL 2038 #define ETH_SCREENING_TYPE_1_REGISTER_2_DSTC_ENABLE_Pos 28UL 2039 #define ETH_SCREENING_TYPE_1_REGISTER_2_DSTC_ENABLE_Msk 0x10000000UL 2040 #define ETH_SCREENING_TYPE_1_REGISTER_2_UDP_PORT_MATCH_ENABLE_Pos 29UL 2041 #define ETH_SCREENING_TYPE_1_REGISTER_2_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2042 /* ETH.SCREENING_TYPE_1_REGISTER_3 */ 2043 #define ETH_SCREENING_TYPE_1_REGISTER_3_QUEUE_NUMBER_Pos 0UL 2044 #define ETH_SCREENING_TYPE_1_REGISTER_3_QUEUE_NUMBER_Msk 0xFUL 2045 #define ETH_SCREENING_TYPE_1_REGISTER_3_DSTC_MATCH_Pos 4UL 2046 #define ETH_SCREENING_TYPE_1_REGISTER_3_DSTC_MATCH_Msk 0xFF0UL 2047 #define ETH_SCREENING_TYPE_1_REGISTER_3_UDP_PORT_MATCH_Pos 12UL 2048 #define ETH_SCREENING_TYPE_1_REGISTER_3_UDP_PORT_MATCH_Msk 0xFFFF000UL 2049 #define ETH_SCREENING_TYPE_1_REGISTER_3_DSTC_ENABLE_Pos 28UL 2050 #define ETH_SCREENING_TYPE_1_REGISTER_3_DSTC_ENABLE_Msk 0x10000000UL 2051 #define ETH_SCREENING_TYPE_1_REGISTER_3_UDP_PORT_MATCH_ENABLE_Pos 29UL 2052 #define ETH_SCREENING_TYPE_1_REGISTER_3_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2053 /* ETH.SCREENING_TYPE_1_REGISTER_4 */ 2054 #define ETH_SCREENING_TYPE_1_REGISTER_4_QUEUE_NUMBER_Pos 0UL 2055 #define ETH_SCREENING_TYPE_1_REGISTER_4_QUEUE_NUMBER_Msk 0xFUL 2056 #define ETH_SCREENING_TYPE_1_REGISTER_4_DSTC_MATCH_Pos 4UL 2057 #define ETH_SCREENING_TYPE_1_REGISTER_4_DSTC_MATCH_Msk 0xFF0UL 2058 #define ETH_SCREENING_TYPE_1_REGISTER_4_UDP_PORT_MATCH_Pos 12UL 2059 #define ETH_SCREENING_TYPE_1_REGISTER_4_UDP_PORT_MATCH_Msk 0xFFFF000UL 2060 #define ETH_SCREENING_TYPE_1_REGISTER_4_DSTC_ENABLE_Pos 28UL 2061 #define ETH_SCREENING_TYPE_1_REGISTER_4_DSTC_ENABLE_Msk 0x10000000UL 2062 #define ETH_SCREENING_TYPE_1_REGISTER_4_UDP_PORT_MATCH_ENABLE_Pos 29UL 2063 #define ETH_SCREENING_TYPE_1_REGISTER_4_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2064 /* ETH.SCREENING_TYPE_1_REGISTER_5 */ 2065 #define ETH_SCREENING_TYPE_1_REGISTER_5_QUEUE_NUMBER_Pos 0UL 2066 #define ETH_SCREENING_TYPE_1_REGISTER_5_QUEUE_NUMBER_Msk 0xFUL 2067 #define ETH_SCREENING_TYPE_1_REGISTER_5_DSTC_MATCH_Pos 4UL 2068 #define ETH_SCREENING_TYPE_1_REGISTER_5_DSTC_MATCH_Msk 0xFF0UL 2069 #define ETH_SCREENING_TYPE_1_REGISTER_5_UDP_PORT_MATCH_Pos 12UL 2070 #define ETH_SCREENING_TYPE_1_REGISTER_5_UDP_PORT_MATCH_Msk 0xFFFF000UL 2071 #define ETH_SCREENING_TYPE_1_REGISTER_5_DSTC_ENABLE_Pos 28UL 2072 #define ETH_SCREENING_TYPE_1_REGISTER_5_DSTC_ENABLE_Msk 0x10000000UL 2073 #define ETH_SCREENING_TYPE_1_REGISTER_5_UDP_PORT_MATCH_ENABLE_Pos 29UL 2074 #define ETH_SCREENING_TYPE_1_REGISTER_5_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2075 /* ETH.SCREENING_TYPE_1_REGISTER_6 */ 2076 #define ETH_SCREENING_TYPE_1_REGISTER_6_QUEUE_NUMBER_Pos 0UL 2077 #define ETH_SCREENING_TYPE_1_REGISTER_6_QUEUE_NUMBER_Msk 0xFUL 2078 #define ETH_SCREENING_TYPE_1_REGISTER_6_DSTC_MATCH_Pos 4UL 2079 #define ETH_SCREENING_TYPE_1_REGISTER_6_DSTC_MATCH_Msk 0xFF0UL 2080 #define ETH_SCREENING_TYPE_1_REGISTER_6_UDP_PORT_MATCH_Pos 12UL 2081 #define ETH_SCREENING_TYPE_1_REGISTER_6_UDP_PORT_MATCH_Msk 0xFFFF000UL 2082 #define ETH_SCREENING_TYPE_1_REGISTER_6_DSTC_ENABLE_Pos 28UL 2083 #define ETH_SCREENING_TYPE_1_REGISTER_6_DSTC_ENABLE_Msk 0x10000000UL 2084 #define ETH_SCREENING_TYPE_1_REGISTER_6_UDP_PORT_MATCH_ENABLE_Pos 29UL 2085 #define ETH_SCREENING_TYPE_1_REGISTER_6_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2086 /* ETH.SCREENING_TYPE_1_REGISTER_7 */ 2087 #define ETH_SCREENING_TYPE_1_REGISTER_7_QUEUE_NUMBER_Pos 0UL 2088 #define ETH_SCREENING_TYPE_1_REGISTER_7_QUEUE_NUMBER_Msk 0xFUL 2089 #define ETH_SCREENING_TYPE_1_REGISTER_7_DSTC_MATCH_Pos 4UL 2090 #define ETH_SCREENING_TYPE_1_REGISTER_7_DSTC_MATCH_Msk 0xFF0UL 2091 #define ETH_SCREENING_TYPE_1_REGISTER_7_UDP_PORT_MATCH_Pos 12UL 2092 #define ETH_SCREENING_TYPE_1_REGISTER_7_UDP_PORT_MATCH_Msk 0xFFFF000UL 2093 #define ETH_SCREENING_TYPE_1_REGISTER_7_DSTC_ENABLE_Pos 28UL 2094 #define ETH_SCREENING_TYPE_1_REGISTER_7_DSTC_ENABLE_Msk 0x10000000UL 2095 #define ETH_SCREENING_TYPE_1_REGISTER_7_UDP_PORT_MATCH_ENABLE_Pos 29UL 2096 #define ETH_SCREENING_TYPE_1_REGISTER_7_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2097 /* ETH.SCREENING_TYPE_1_REGISTER_8 */ 2098 #define ETH_SCREENING_TYPE_1_REGISTER_8_QUEUE_NUMBER_Pos 0UL 2099 #define ETH_SCREENING_TYPE_1_REGISTER_8_QUEUE_NUMBER_Msk 0xFUL 2100 #define ETH_SCREENING_TYPE_1_REGISTER_8_DSTC_MATCH_Pos 4UL 2101 #define ETH_SCREENING_TYPE_1_REGISTER_8_DSTC_MATCH_Msk 0xFF0UL 2102 #define ETH_SCREENING_TYPE_1_REGISTER_8_UDP_PORT_MATCH_Pos 12UL 2103 #define ETH_SCREENING_TYPE_1_REGISTER_8_UDP_PORT_MATCH_Msk 0xFFFF000UL 2104 #define ETH_SCREENING_TYPE_1_REGISTER_8_DSTC_ENABLE_Pos 28UL 2105 #define ETH_SCREENING_TYPE_1_REGISTER_8_DSTC_ENABLE_Msk 0x10000000UL 2106 #define ETH_SCREENING_TYPE_1_REGISTER_8_UDP_PORT_MATCH_ENABLE_Pos 29UL 2107 #define ETH_SCREENING_TYPE_1_REGISTER_8_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2108 /* ETH.SCREENING_TYPE_1_REGISTER_9 */ 2109 #define ETH_SCREENING_TYPE_1_REGISTER_9_QUEUE_NUMBER_Pos 0UL 2110 #define ETH_SCREENING_TYPE_1_REGISTER_9_QUEUE_NUMBER_Msk 0xFUL 2111 #define ETH_SCREENING_TYPE_1_REGISTER_9_DSTC_MATCH_Pos 4UL 2112 #define ETH_SCREENING_TYPE_1_REGISTER_9_DSTC_MATCH_Msk 0xFF0UL 2113 #define ETH_SCREENING_TYPE_1_REGISTER_9_UDP_PORT_MATCH_Pos 12UL 2114 #define ETH_SCREENING_TYPE_1_REGISTER_9_UDP_PORT_MATCH_Msk 0xFFFF000UL 2115 #define ETH_SCREENING_TYPE_1_REGISTER_9_DSTC_ENABLE_Pos 28UL 2116 #define ETH_SCREENING_TYPE_1_REGISTER_9_DSTC_ENABLE_Msk 0x10000000UL 2117 #define ETH_SCREENING_TYPE_1_REGISTER_9_UDP_PORT_MATCH_ENABLE_Pos 29UL 2118 #define ETH_SCREENING_TYPE_1_REGISTER_9_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2119 /* ETH.SCREENING_TYPE_1_REGISTER_10 */ 2120 #define ETH_SCREENING_TYPE_1_REGISTER_10_QUEUE_NUMBER_Pos 0UL 2121 #define ETH_SCREENING_TYPE_1_REGISTER_10_QUEUE_NUMBER_Msk 0xFUL 2122 #define ETH_SCREENING_TYPE_1_REGISTER_10_DSTC_MATCH_Pos 4UL 2123 #define ETH_SCREENING_TYPE_1_REGISTER_10_DSTC_MATCH_Msk 0xFF0UL 2124 #define ETH_SCREENING_TYPE_1_REGISTER_10_UDP_PORT_MATCH_Pos 12UL 2125 #define ETH_SCREENING_TYPE_1_REGISTER_10_UDP_PORT_MATCH_Msk 0xFFFF000UL 2126 #define ETH_SCREENING_TYPE_1_REGISTER_10_DSTC_ENABLE_Pos 28UL 2127 #define ETH_SCREENING_TYPE_1_REGISTER_10_DSTC_ENABLE_Msk 0x10000000UL 2128 #define ETH_SCREENING_TYPE_1_REGISTER_10_UDP_PORT_MATCH_ENABLE_Pos 29UL 2129 #define ETH_SCREENING_TYPE_1_REGISTER_10_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2130 /* ETH.SCREENING_TYPE_1_REGISTER_11 */ 2131 #define ETH_SCREENING_TYPE_1_REGISTER_11_QUEUE_NUMBER_Pos 0UL 2132 #define ETH_SCREENING_TYPE_1_REGISTER_11_QUEUE_NUMBER_Msk 0xFUL 2133 #define ETH_SCREENING_TYPE_1_REGISTER_11_DSTC_MATCH_Pos 4UL 2134 #define ETH_SCREENING_TYPE_1_REGISTER_11_DSTC_MATCH_Msk 0xFF0UL 2135 #define ETH_SCREENING_TYPE_1_REGISTER_11_UDP_PORT_MATCH_Pos 12UL 2136 #define ETH_SCREENING_TYPE_1_REGISTER_11_UDP_PORT_MATCH_Msk 0xFFFF000UL 2137 #define ETH_SCREENING_TYPE_1_REGISTER_11_DSTC_ENABLE_Pos 28UL 2138 #define ETH_SCREENING_TYPE_1_REGISTER_11_DSTC_ENABLE_Msk 0x10000000UL 2139 #define ETH_SCREENING_TYPE_1_REGISTER_11_UDP_PORT_MATCH_ENABLE_Pos 29UL 2140 #define ETH_SCREENING_TYPE_1_REGISTER_11_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2141 /* ETH.SCREENING_TYPE_1_REGISTER_12 */ 2142 #define ETH_SCREENING_TYPE_1_REGISTER_12_QUEUE_NUMBER_Pos 0UL 2143 #define ETH_SCREENING_TYPE_1_REGISTER_12_QUEUE_NUMBER_Msk 0xFUL 2144 #define ETH_SCREENING_TYPE_1_REGISTER_12_DSTC_MATCH_Pos 4UL 2145 #define ETH_SCREENING_TYPE_1_REGISTER_12_DSTC_MATCH_Msk 0xFF0UL 2146 #define ETH_SCREENING_TYPE_1_REGISTER_12_UDP_PORT_MATCH_Pos 12UL 2147 #define ETH_SCREENING_TYPE_1_REGISTER_12_UDP_PORT_MATCH_Msk 0xFFFF000UL 2148 #define ETH_SCREENING_TYPE_1_REGISTER_12_DSTC_ENABLE_Pos 28UL 2149 #define ETH_SCREENING_TYPE_1_REGISTER_12_DSTC_ENABLE_Msk 0x10000000UL 2150 #define ETH_SCREENING_TYPE_1_REGISTER_12_UDP_PORT_MATCH_ENABLE_Pos 29UL 2151 #define ETH_SCREENING_TYPE_1_REGISTER_12_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2152 /* ETH.SCREENING_TYPE_1_REGISTER_13 */ 2153 #define ETH_SCREENING_TYPE_1_REGISTER_13_QUEUE_NUMBER_Pos 0UL 2154 #define ETH_SCREENING_TYPE_1_REGISTER_13_QUEUE_NUMBER_Msk 0xFUL 2155 #define ETH_SCREENING_TYPE_1_REGISTER_13_DSTC_MATCH_Pos 4UL 2156 #define ETH_SCREENING_TYPE_1_REGISTER_13_DSTC_MATCH_Msk 0xFF0UL 2157 #define ETH_SCREENING_TYPE_1_REGISTER_13_UDP_PORT_MATCH_Pos 12UL 2158 #define ETH_SCREENING_TYPE_1_REGISTER_13_UDP_PORT_MATCH_Msk 0xFFFF000UL 2159 #define ETH_SCREENING_TYPE_1_REGISTER_13_DSTC_ENABLE_Pos 28UL 2160 #define ETH_SCREENING_TYPE_1_REGISTER_13_DSTC_ENABLE_Msk 0x10000000UL 2161 #define ETH_SCREENING_TYPE_1_REGISTER_13_UDP_PORT_MATCH_ENABLE_Pos 29UL 2162 #define ETH_SCREENING_TYPE_1_REGISTER_13_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2163 /* ETH.SCREENING_TYPE_1_REGISTER_14 */ 2164 #define ETH_SCREENING_TYPE_1_REGISTER_14_QUEUE_NUMBER_Pos 0UL 2165 #define ETH_SCREENING_TYPE_1_REGISTER_14_QUEUE_NUMBER_Msk 0xFUL 2166 #define ETH_SCREENING_TYPE_1_REGISTER_14_DSTC_MATCH_Pos 4UL 2167 #define ETH_SCREENING_TYPE_1_REGISTER_14_DSTC_MATCH_Msk 0xFF0UL 2168 #define ETH_SCREENING_TYPE_1_REGISTER_14_UDP_PORT_MATCH_Pos 12UL 2169 #define ETH_SCREENING_TYPE_1_REGISTER_14_UDP_PORT_MATCH_Msk 0xFFFF000UL 2170 #define ETH_SCREENING_TYPE_1_REGISTER_14_DSTC_ENABLE_Pos 28UL 2171 #define ETH_SCREENING_TYPE_1_REGISTER_14_DSTC_ENABLE_Msk 0x10000000UL 2172 #define ETH_SCREENING_TYPE_1_REGISTER_14_UDP_PORT_MATCH_ENABLE_Pos 29UL 2173 #define ETH_SCREENING_TYPE_1_REGISTER_14_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2174 /* ETH.SCREENING_TYPE_1_REGISTER_15 */ 2175 #define ETH_SCREENING_TYPE_1_REGISTER_15_QUEUE_NUMBER_Pos 0UL 2176 #define ETH_SCREENING_TYPE_1_REGISTER_15_QUEUE_NUMBER_Msk 0xFUL 2177 #define ETH_SCREENING_TYPE_1_REGISTER_15_DSTC_MATCH_Pos 4UL 2178 #define ETH_SCREENING_TYPE_1_REGISTER_15_DSTC_MATCH_Msk 0xFF0UL 2179 #define ETH_SCREENING_TYPE_1_REGISTER_15_UDP_PORT_MATCH_Pos 12UL 2180 #define ETH_SCREENING_TYPE_1_REGISTER_15_UDP_PORT_MATCH_Msk 0xFFFF000UL 2181 #define ETH_SCREENING_TYPE_1_REGISTER_15_DSTC_ENABLE_Pos 28UL 2182 #define ETH_SCREENING_TYPE_1_REGISTER_15_DSTC_ENABLE_Msk 0x10000000UL 2183 #define ETH_SCREENING_TYPE_1_REGISTER_15_UDP_PORT_MATCH_ENABLE_Pos 29UL 2184 #define ETH_SCREENING_TYPE_1_REGISTER_15_UDP_PORT_MATCH_ENABLE_Msk 0x20000000UL 2185 /* ETH.SCREENING_TYPE_2_REGISTER_0 */ 2186 #define ETH_SCREENING_TYPE_2_REGISTER_0_QUEUE_NUMBER_Pos 0UL 2187 #define ETH_SCREENING_TYPE_2_REGISTER_0_QUEUE_NUMBER_Msk 0xFUL 2188 #define ETH_SCREENING_TYPE_2_REGISTER_0_VLAN_PRIORITY_Pos 4UL 2189 #define ETH_SCREENING_TYPE_2_REGISTER_0_VLAN_PRIORITY_Msk 0x70UL 2190 #define ETH_SCREENING_TYPE_2_REGISTER_0_RESERVED_7_Pos 7UL 2191 #define ETH_SCREENING_TYPE_2_REGISTER_0_RESERVED_7_Msk 0x80UL 2192 #define ETH_SCREENING_TYPE_2_REGISTER_0_VLAN_ENABLE_Pos 8UL 2193 #define ETH_SCREENING_TYPE_2_REGISTER_0_VLAN_ENABLE_Msk 0x100UL 2194 #define ETH_SCREENING_TYPE_2_REGISTER_0_INDEX_Pos 9UL 2195 #define ETH_SCREENING_TYPE_2_REGISTER_0_INDEX_Msk 0xE00UL 2196 #define ETH_SCREENING_TYPE_2_REGISTER_0_ETHERTYPE_ENABLE_Pos 12UL 2197 #define ETH_SCREENING_TYPE_2_REGISTER_0_ETHERTYPE_ENABLE_Msk 0x1000UL 2198 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_A_Pos 13UL 2199 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_A_Msk 0x3E000UL 2200 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_A_ENABLE_Pos 18UL 2201 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_A_ENABLE_Msk 0x40000UL 2202 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_B_Pos 19UL 2203 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_B_Msk 0xF80000UL 2204 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_B_ENABLE_Pos 24UL 2205 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_B_ENABLE_Msk 0x1000000UL 2206 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_C_Pos 25UL 2207 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_C_Msk 0x3E000000UL 2208 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_C_ENABLE_Pos 30UL 2209 #define ETH_SCREENING_TYPE_2_REGISTER_0_COMPARE_C_ENABLE_Msk 0x40000000UL 2210 #define ETH_SCREENING_TYPE_2_REGISTER_0_RESERVED_31_Pos 31UL 2211 #define ETH_SCREENING_TYPE_2_REGISTER_0_RESERVED_31_Msk 0x80000000UL 2212 /* ETH.SCREENING_TYPE_2_REGISTER_1 */ 2213 #define ETH_SCREENING_TYPE_2_REGISTER_1_QUEUE_NUMBER_Pos 0UL 2214 #define ETH_SCREENING_TYPE_2_REGISTER_1_QUEUE_NUMBER_Msk 0xFUL 2215 #define ETH_SCREENING_TYPE_2_REGISTER_1_VLAN_PRIORITY_Pos 4UL 2216 #define ETH_SCREENING_TYPE_2_REGISTER_1_VLAN_PRIORITY_Msk 0x70UL 2217 #define ETH_SCREENING_TYPE_2_REGISTER_1_RESERVED_7_Pos 7UL 2218 #define ETH_SCREENING_TYPE_2_REGISTER_1_RESERVED_7_Msk 0x80UL 2219 #define ETH_SCREENING_TYPE_2_REGISTER_1_VLAN_ENABLE_Pos 8UL 2220 #define ETH_SCREENING_TYPE_2_REGISTER_1_VLAN_ENABLE_Msk 0x100UL 2221 #define ETH_SCREENING_TYPE_2_REGISTER_1_INDEX_Pos 9UL 2222 #define ETH_SCREENING_TYPE_2_REGISTER_1_INDEX_Msk 0xE00UL 2223 #define ETH_SCREENING_TYPE_2_REGISTER_1_ETHERTYPE_ENABLE_Pos 12UL 2224 #define ETH_SCREENING_TYPE_2_REGISTER_1_ETHERTYPE_ENABLE_Msk 0x1000UL 2225 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_A_Pos 13UL 2226 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_A_Msk 0x3E000UL 2227 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_A_ENABLE_Pos 18UL 2228 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_A_ENABLE_Msk 0x40000UL 2229 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_B_Pos 19UL 2230 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_B_Msk 0xF80000UL 2231 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_B_ENABLE_Pos 24UL 2232 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_B_ENABLE_Msk 0x1000000UL 2233 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_C_Pos 25UL 2234 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_C_Msk 0x3E000000UL 2235 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_C_ENABLE_Pos 30UL 2236 #define ETH_SCREENING_TYPE_2_REGISTER_1_COMPARE_C_ENABLE_Msk 0x40000000UL 2237 #define ETH_SCREENING_TYPE_2_REGISTER_1_RESERVED_31_Pos 31UL 2238 #define ETH_SCREENING_TYPE_2_REGISTER_1_RESERVED_31_Msk 0x80000000UL 2239 /* ETH.SCREENING_TYPE_2_REGISTER_2 */ 2240 #define ETH_SCREENING_TYPE_2_REGISTER_2_QUEUE_NUMBER_Pos 0UL 2241 #define ETH_SCREENING_TYPE_2_REGISTER_2_QUEUE_NUMBER_Msk 0xFUL 2242 #define ETH_SCREENING_TYPE_2_REGISTER_2_VLAN_PRIORITY_Pos 4UL 2243 #define ETH_SCREENING_TYPE_2_REGISTER_2_VLAN_PRIORITY_Msk 0x70UL 2244 #define ETH_SCREENING_TYPE_2_REGISTER_2_RESERVED_7_Pos 7UL 2245 #define ETH_SCREENING_TYPE_2_REGISTER_2_RESERVED_7_Msk 0x80UL 2246 #define ETH_SCREENING_TYPE_2_REGISTER_2_VLAN_ENABLE_Pos 8UL 2247 #define ETH_SCREENING_TYPE_2_REGISTER_2_VLAN_ENABLE_Msk 0x100UL 2248 #define ETH_SCREENING_TYPE_2_REGISTER_2_INDEX_Pos 9UL 2249 #define ETH_SCREENING_TYPE_2_REGISTER_2_INDEX_Msk 0xE00UL 2250 #define ETH_SCREENING_TYPE_2_REGISTER_2_ETHERTYPE_ENABLE_Pos 12UL 2251 #define ETH_SCREENING_TYPE_2_REGISTER_2_ETHERTYPE_ENABLE_Msk 0x1000UL 2252 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_A_Pos 13UL 2253 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_A_Msk 0x3E000UL 2254 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_A_ENABLE_Pos 18UL 2255 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_A_ENABLE_Msk 0x40000UL 2256 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_B_Pos 19UL 2257 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_B_Msk 0xF80000UL 2258 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_B_ENABLE_Pos 24UL 2259 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_B_ENABLE_Msk 0x1000000UL 2260 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_C_Pos 25UL 2261 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_C_Msk 0x3E000000UL 2262 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_C_ENABLE_Pos 30UL 2263 #define ETH_SCREENING_TYPE_2_REGISTER_2_COMPARE_C_ENABLE_Msk 0x40000000UL 2264 #define ETH_SCREENING_TYPE_2_REGISTER_2_RESERVED_31_Pos 31UL 2265 #define ETH_SCREENING_TYPE_2_REGISTER_2_RESERVED_31_Msk 0x80000000UL 2266 /* ETH.SCREENING_TYPE_2_REGISTER_3 */ 2267 #define ETH_SCREENING_TYPE_2_REGISTER_3_QUEUE_NUMBER_Pos 0UL 2268 #define ETH_SCREENING_TYPE_2_REGISTER_3_QUEUE_NUMBER_Msk 0xFUL 2269 #define ETH_SCREENING_TYPE_2_REGISTER_3_VLAN_PRIORITY_Pos 4UL 2270 #define ETH_SCREENING_TYPE_2_REGISTER_3_VLAN_PRIORITY_Msk 0x70UL 2271 #define ETH_SCREENING_TYPE_2_REGISTER_3_RESERVED_7_Pos 7UL 2272 #define ETH_SCREENING_TYPE_2_REGISTER_3_RESERVED_7_Msk 0x80UL 2273 #define ETH_SCREENING_TYPE_2_REGISTER_3_VLAN_ENABLE_Pos 8UL 2274 #define ETH_SCREENING_TYPE_2_REGISTER_3_VLAN_ENABLE_Msk 0x100UL 2275 #define ETH_SCREENING_TYPE_2_REGISTER_3_INDEX_Pos 9UL 2276 #define ETH_SCREENING_TYPE_2_REGISTER_3_INDEX_Msk 0xE00UL 2277 #define ETH_SCREENING_TYPE_2_REGISTER_3_ETHERTYPE_ENABLE_Pos 12UL 2278 #define ETH_SCREENING_TYPE_2_REGISTER_3_ETHERTYPE_ENABLE_Msk 0x1000UL 2279 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_A_Pos 13UL 2280 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_A_Msk 0x3E000UL 2281 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_A_ENABLE_Pos 18UL 2282 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_A_ENABLE_Msk 0x40000UL 2283 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_B_Pos 19UL 2284 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_B_Msk 0xF80000UL 2285 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_B_ENABLE_Pos 24UL 2286 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_B_ENABLE_Msk 0x1000000UL 2287 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_C_Pos 25UL 2288 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_C_Msk 0x3E000000UL 2289 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_C_ENABLE_Pos 30UL 2290 #define ETH_SCREENING_TYPE_2_REGISTER_3_COMPARE_C_ENABLE_Msk 0x40000000UL 2291 #define ETH_SCREENING_TYPE_2_REGISTER_3_RESERVED_31_Pos 31UL 2292 #define ETH_SCREENING_TYPE_2_REGISTER_3_RESERVED_31_Msk 0x80000000UL 2293 /* ETH.SCREENING_TYPE_2_REGISTER_4 */ 2294 #define ETH_SCREENING_TYPE_2_REGISTER_4_QUEUE_NUMBER_Pos 0UL 2295 #define ETH_SCREENING_TYPE_2_REGISTER_4_QUEUE_NUMBER_Msk 0xFUL 2296 #define ETH_SCREENING_TYPE_2_REGISTER_4_VLAN_PRIORITY_Pos 4UL 2297 #define ETH_SCREENING_TYPE_2_REGISTER_4_VLAN_PRIORITY_Msk 0x70UL 2298 #define ETH_SCREENING_TYPE_2_REGISTER_4_RESERVED_7_Pos 7UL 2299 #define ETH_SCREENING_TYPE_2_REGISTER_4_RESERVED_7_Msk 0x80UL 2300 #define ETH_SCREENING_TYPE_2_REGISTER_4_VLAN_ENABLE_Pos 8UL 2301 #define ETH_SCREENING_TYPE_2_REGISTER_4_VLAN_ENABLE_Msk 0x100UL 2302 #define ETH_SCREENING_TYPE_2_REGISTER_4_INDEX_Pos 9UL 2303 #define ETH_SCREENING_TYPE_2_REGISTER_4_INDEX_Msk 0xE00UL 2304 #define ETH_SCREENING_TYPE_2_REGISTER_4_ETHERTYPE_ENABLE_Pos 12UL 2305 #define ETH_SCREENING_TYPE_2_REGISTER_4_ETHERTYPE_ENABLE_Msk 0x1000UL 2306 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_A_Pos 13UL 2307 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_A_Msk 0x3E000UL 2308 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_A_ENABLE_Pos 18UL 2309 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_A_ENABLE_Msk 0x40000UL 2310 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_B_Pos 19UL 2311 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_B_Msk 0xF80000UL 2312 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_B_ENABLE_Pos 24UL 2313 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_B_ENABLE_Msk 0x1000000UL 2314 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_C_Pos 25UL 2315 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_C_Msk 0x3E000000UL 2316 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_C_ENABLE_Pos 30UL 2317 #define ETH_SCREENING_TYPE_2_REGISTER_4_COMPARE_C_ENABLE_Msk 0x40000000UL 2318 #define ETH_SCREENING_TYPE_2_REGISTER_4_RESERVED_31_Pos 31UL 2319 #define ETH_SCREENING_TYPE_2_REGISTER_4_RESERVED_31_Msk 0x80000000UL 2320 /* ETH.SCREENING_TYPE_2_REGISTER_5 */ 2321 #define ETH_SCREENING_TYPE_2_REGISTER_5_QUEUE_NUMBER_Pos 0UL 2322 #define ETH_SCREENING_TYPE_2_REGISTER_5_QUEUE_NUMBER_Msk 0xFUL 2323 #define ETH_SCREENING_TYPE_2_REGISTER_5_VLAN_PRIORITY_Pos 4UL 2324 #define ETH_SCREENING_TYPE_2_REGISTER_5_VLAN_PRIORITY_Msk 0x70UL 2325 #define ETH_SCREENING_TYPE_2_REGISTER_5_RESERVED_7_Pos 7UL 2326 #define ETH_SCREENING_TYPE_2_REGISTER_5_RESERVED_7_Msk 0x80UL 2327 #define ETH_SCREENING_TYPE_2_REGISTER_5_VLAN_ENABLE_Pos 8UL 2328 #define ETH_SCREENING_TYPE_2_REGISTER_5_VLAN_ENABLE_Msk 0x100UL 2329 #define ETH_SCREENING_TYPE_2_REGISTER_5_INDEX_Pos 9UL 2330 #define ETH_SCREENING_TYPE_2_REGISTER_5_INDEX_Msk 0xE00UL 2331 #define ETH_SCREENING_TYPE_2_REGISTER_5_ETHERTYPE_ENABLE_Pos 12UL 2332 #define ETH_SCREENING_TYPE_2_REGISTER_5_ETHERTYPE_ENABLE_Msk 0x1000UL 2333 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_A_Pos 13UL 2334 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_A_Msk 0x3E000UL 2335 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_A_ENABLE_Pos 18UL 2336 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_A_ENABLE_Msk 0x40000UL 2337 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_B_Pos 19UL 2338 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_B_Msk 0xF80000UL 2339 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_B_ENABLE_Pos 24UL 2340 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_B_ENABLE_Msk 0x1000000UL 2341 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_C_Pos 25UL 2342 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_C_Msk 0x3E000000UL 2343 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_C_ENABLE_Pos 30UL 2344 #define ETH_SCREENING_TYPE_2_REGISTER_5_COMPARE_C_ENABLE_Msk 0x40000000UL 2345 #define ETH_SCREENING_TYPE_2_REGISTER_5_RESERVED_31_Pos 31UL 2346 #define ETH_SCREENING_TYPE_2_REGISTER_5_RESERVED_31_Msk 0x80000000UL 2347 /* ETH.SCREENING_TYPE_2_REGISTER_6 */ 2348 #define ETH_SCREENING_TYPE_2_REGISTER_6_QUEUE_NUMBER_Pos 0UL 2349 #define ETH_SCREENING_TYPE_2_REGISTER_6_QUEUE_NUMBER_Msk 0xFUL 2350 #define ETH_SCREENING_TYPE_2_REGISTER_6_VLAN_PRIORITY_Pos 4UL 2351 #define ETH_SCREENING_TYPE_2_REGISTER_6_VLAN_PRIORITY_Msk 0x70UL 2352 #define ETH_SCREENING_TYPE_2_REGISTER_6_RESERVED_7_Pos 7UL 2353 #define ETH_SCREENING_TYPE_2_REGISTER_6_RESERVED_7_Msk 0x80UL 2354 #define ETH_SCREENING_TYPE_2_REGISTER_6_VLAN_ENABLE_Pos 8UL 2355 #define ETH_SCREENING_TYPE_2_REGISTER_6_VLAN_ENABLE_Msk 0x100UL 2356 #define ETH_SCREENING_TYPE_2_REGISTER_6_INDEX_Pos 9UL 2357 #define ETH_SCREENING_TYPE_2_REGISTER_6_INDEX_Msk 0xE00UL 2358 #define ETH_SCREENING_TYPE_2_REGISTER_6_ETHERTYPE_ENABLE_Pos 12UL 2359 #define ETH_SCREENING_TYPE_2_REGISTER_6_ETHERTYPE_ENABLE_Msk 0x1000UL 2360 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_A_Pos 13UL 2361 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_A_Msk 0x3E000UL 2362 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_A_ENABLE_Pos 18UL 2363 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_A_ENABLE_Msk 0x40000UL 2364 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_B_Pos 19UL 2365 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_B_Msk 0xF80000UL 2366 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_B_ENABLE_Pos 24UL 2367 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_B_ENABLE_Msk 0x1000000UL 2368 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_C_Pos 25UL 2369 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_C_Msk 0x3E000000UL 2370 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_C_ENABLE_Pos 30UL 2371 #define ETH_SCREENING_TYPE_2_REGISTER_6_COMPARE_C_ENABLE_Msk 0x40000000UL 2372 #define ETH_SCREENING_TYPE_2_REGISTER_6_RESERVED_31_Pos 31UL 2373 #define ETH_SCREENING_TYPE_2_REGISTER_6_RESERVED_31_Msk 0x80000000UL 2374 /* ETH.SCREENING_TYPE_2_REGISTER_7 */ 2375 #define ETH_SCREENING_TYPE_2_REGISTER_7_QUEUE_NUMBER_Pos 0UL 2376 #define ETH_SCREENING_TYPE_2_REGISTER_7_QUEUE_NUMBER_Msk 0xFUL 2377 #define ETH_SCREENING_TYPE_2_REGISTER_7_VLAN_PRIORITY_Pos 4UL 2378 #define ETH_SCREENING_TYPE_2_REGISTER_7_VLAN_PRIORITY_Msk 0x70UL 2379 #define ETH_SCREENING_TYPE_2_REGISTER_7_RESERVED_7_Pos 7UL 2380 #define ETH_SCREENING_TYPE_2_REGISTER_7_RESERVED_7_Msk 0x80UL 2381 #define ETH_SCREENING_TYPE_2_REGISTER_7_VLAN_ENABLE_Pos 8UL 2382 #define ETH_SCREENING_TYPE_2_REGISTER_7_VLAN_ENABLE_Msk 0x100UL 2383 #define ETH_SCREENING_TYPE_2_REGISTER_7_INDEX_Pos 9UL 2384 #define ETH_SCREENING_TYPE_2_REGISTER_7_INDEX_Msk 0xE00UL 2385 #define ETH_SCREENING_TYPE_2_REGISTER_7_ETHERTYPE_ENABLE_Pos 12UL 2386 #define ETH_SCREENING_TYPE_2_REGISTER_7_ETHERTYPE_ENABLE_Msk 0x1000UL 2387 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_A_Pos 13UL 2388 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_A_Msk 0x3E000UL 2389 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_A_ENABLE_Pos 18UL 2390 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_A_ENABLE_Msk 0x40000UL 2391 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_B_Pos 19UL 2392 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_B_Msk 0xF80000UL 2393 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_B_ENABLE_Pos 24UL 2394 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_B_ENABLE_Msk 0x1000000UL 2395 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_C_Pos 25UL 2396 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_C_Msk 0x3E000000UL 2397 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_C_ENABLE_Pos 30UL 2398 #define ETH_SCREENING_TYPE_2_REGISTER_7_COMPARE_C_ENABLE_Msk 0x40000000UL 2399 #define ETH_SCREENING_TYPE_2_REGISTER_7_RESERVED_31_Pos 31UL 2400 #define ETH_SCREENING_TYPE_2_REGISTER_7_RESERVED_31_Msk 0x80000000UL 2401 /* ETH.SCREENING_TYPE_2_REGISTER_8 */ 2402 #define ETH_SCREENING_TYPE_2_REGISTER_8_QUEUE_NUMBER_Pos 0UL 2403 #define ETH_SCREENING_TYPE_2_REGISTER_8_QUEUE_NUMBER_Msk 0xFUL 2404 #define ETH_SCREENING_TYPE_2_REGISTER_8_VLAN_PRIORITY_Pos 4UL 2405 #define ETH_SCREENING_TYPE_2_REGISTER_8_VLAN_PRIORITY_Msk 0x70UL 2406 #define ETH_SCREENING_TYPE_2_REGISTER_8_RESERVED_7_Pos 7UL 2407 #define ETH_SCREENING_TYPE_2_REGISTER_8_RESERVED_7_Msk 0x80UL 2408 #define ETH_SCREENING_TYPE_2_REGISTER_8_VLAN_ENABLE_Pos 8UL 2409 #define ETH_SCREENING_TYPE_2_REGISTER_8_VLAN_ENABLE_Msk 0x100UL 2410 #define ETH_SCREENING_TYPE_2_REGISTER_8_INDEX_Pos 9UL 2411 #define ETH_SCREENING_TYPE_2_REGISTER_8_INDEX_Msk 0xE00UL 2412 #define ETH_SCREENING_TYPE_2_REGISTER_8_ETHERTYPE_ENABLE_Pos 12UL 2413 #define ETH_SCREENING_TYPE_2_REGISTER_8_ETHERTYPE_ENABLE_Msk 0x1000UL 2414 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_A_Pos 13UL 2415 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_A_Msk 0x3E000UL 2416 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_A_ENABLE_Pos 18UL 2417 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_A_ENABLE_Msk 0x40000UL 2418 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_B_Pos 19UL 2419 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_B_Msk 0xF80000UL 2420 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_B_ENABLE_Pos 24UL 2421 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_B_ENABLE_Msk 0x1000000UL 2422 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_C_Pos 25UL 2423 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_C_Msk 0x3E000000UL 2424 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_C_ENABLE_Pos 30UL 2425 #define ETH_SCREENING_TYPE_2_REGISTER_8_COMPARE_C_ENABLE_Msk 0x40000000UL 2426 #define ETH_SCREENING_TYPE_2_REGISTER_8_RESERVED_31_Pos 31UL 2427 #define ETH_SCREENING_TYPE_2_REGISTER_8_RESERVED_31_Msk 0x80000000UL 2428 /* ETH.SCREENING_TYPE_2_REGISTER_9 */ 2429 #define ETH_SCREENING_TYPE_2_REGISTER_9_QUEUE_NUMBER_Pos 0UL 2430 #define ETH_SCREENING_TYPE_2_REGISTER_9_QUEUE_NUMBER_Msk 0xFUL 2431 #define ETH_SCREENING_TYPE_2_REGISTER_9_VLAN_PRIORITY_Pos 4UL 2432 #define ETH_SCREENING_TYPE_2_REGISTER_9_VLAN_PRIORITY_Msk 0x70UL 2433 #define ETH_SCREENING_TYPE_2_REGISTER_9_RESERVED_7_Pos 7UL 2434 #define ETH_SCREENING_TYPE_2_REGISTER_9_RESERVED_7_Msk 0x80UL 2435 #define ETH_SCREENING_TYPE_2_REGISTER_9_VLAN_ENABLE_Pos 8UL 2436 #define ETH_SCREENING_TYPE_2_REGISTER_9_VLAN_ENABLE_Msk 0x100UL 2437 #define ETH_SCREENING_TYPE_2_REGISTER_9_INDEX_Pos 9UL 2438 #define ETH_SCREENING_TYPE_2_REGISTER_9_INDEX_Msk 0xE00UL 2439 #define ETH_SCREENING_TYPE_2_REGISTER_9_ETHERTYPE_ENABLE_Pos 12UL 2440 #define ETH_SCREENING_TYPE_2_REGISTER_9_ETHERTYPE_ENABLE_Msk 0x1000UL 2441 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_A_Pos 13UL 2442 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_A_Msk 0x3E000UL 2443 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_A_ENABLE_Pos 18UL 2444 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_A_ENABLE_Msk 0x40000UL 2445 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_B_Pos 19UL 2446 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_B_Msk 0xF80000UL 2447 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_B_ENABLE_Pos 24UL 2448 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_B_ENABLE_Msk 0x1000000UL 2449 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_C_Pos 25UL 2450 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_C_Msk 0x3E000000UL 2451 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_C_ENABLE_Pos 30UL 2452 #define ETH_SCREENING_TYPE_2_REGISTER_9_COMPARE_C_ENABLE_Msk 0x40000000UL 2453 #define ETH_SCREENING_TYPE_2_REGISTER_9_RESERVED_31_Pos 31UL 2454 #define ETH_SCREENING_TYPE_2_REGISTER_9_RESERVED_31_Msk 0x80000000UL 2455 /* ETH.SCREENING_TYPE_2_REGISTER_10 */ 2456 #define ETH_SCREENING_TYPE_2_REGISTER_10_QUEUE_NUMBER_Pos 0UL 2457 #define ETH_SCREENING_TYPE_2_REGISTER_10_QUEUE_NUMBER_Msk 0xFUL 2458 #define ETH_SCREENING_TYPE_2_REGISTER_10_VLAN_PRIORITY_Pos 4UL 2459 #define ETH_SCREENING_TYPE_2_REGISTER_10_VLAN_PRIORITY_Msk 0x70UL 2460 #define ETH_SCREENING_TYPE_2_REGISTER_10_RESERVED_7_Pos 7UL 2461 #define ETH_SCREENING_TYPE_2_REGISTER_10_RESERVED_7_Msk 0x80UL 2462 #define ETH_SCREENING_TYPE_2_REGISTER_10_VLAN_ENABLE_Pos 8UL 2463 #define ETH_SCREENING_TYPE_2_REGISTER_10_VLAN_ENABLE_Msk 0x100UL 2464 #define ETH_SCREENING_TYPE_2_REGISTER_10_INDEX_Pos 9UL 2465 #define ETH_SCREENING_TYPE_2_REGISTER_10_INDEX_Msk 0xE00UL 2466 #define ETH_SCREENING_TYPE_2_REGISTER_10_ETHERTYPE_ENABLE_Pos 12UL 2467 #define ETH_SCREENING_TYPE_2_REGISTER_10_ETHERTYPE_ENABLE_Msk 0x1000UL 2468 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_A_Pos 13UL 2469 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_A_Msk 0x3E000UL 2470 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_A_ENABLE_Pos 18UL 2471 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_A_ENABLE_Msk 0x40000UL 2472 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_B_Pos 19UL 2473 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_B_Msk 0xF80000UL 2474 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_B_ENABLE_Pos 24UL 2475 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_B_ENABLE_Msk 0x1000000UL 2476 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_C_Pos 25UL 2477 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_C_Msk 0x3E000000UL 2478 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_C_ENABLE_Pos 30UL 2479 #define ETH_SCREENING_TYPE_2_REGISTER_10_COMPARE_C_ENABLE_Msk 0x40000000UL 2480 #define ETH_SCREENING_TYPE_2_REGISTER_10_RESERVED_31_Pos 31UL 2481 #define ETH_SCREENING_TYPE_2_REGISTER_10_RESERVED_31_Msk 0x80000000UL 2482 /* ETH.SCREENING_TYPE_2_REGISTER_11 */ 2483 #define ETH_SCREENING_TYPE_2_REGISTER_11_QUEUE_NUMBER_Pos 0UL 2484 #define ETH_SCREENING_TYPE_2_REGISTER_11_QUEUE_NUMBER_Msk 0xFUL 2485 #define ETH_SCREENING_TYPE_2_REGISTER_11_VLAN_PRIORITY_Pos 4UL 2486 #define ETH_SCREENING_TYPE_2_REGISTER_11_VLAN_PRIORITY_Msk 0x70UL 2487 #define ETH_SCREENING_TYPE_2_REGISTER_11_RESERVED_7_Pos 7UL 2488 #define ETH_SCREENING_TYPE_2_REGISTER_11_RESERVED_7_Msk 0x80UL 2489 #define ETH_SCREENING_TYPE_2_REGISTER_11_VLAN_ENABLE_Pos 8UL 2490 #define ETH_SCREENING_TYPE_2_REGISTER_11_VLAN_ENABLE_Msk 0x100UL 2491 #define ETH_SCREENING_TYPE_2_REGISTER_11_INDEX_Pos 9UL 2492 #define ETH_SCREENING_TYPE_2_REGISTER_11_INDEX_Msk 0xE00UL 2493 #define ETH_SCREENING_TYPE_2_REGISTER_11_ETHERTYPE_ENABLE_Pos 12UL 2494 #define ETH_SCREENING_TYPE_2_REGISTER_11_ETHERTYPE_ENABLE_Msk 0x1000UL 2495 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_A_Pos 13UL 2496 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_A_Msk 0x3E000UL 2497 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_A_ENABLE_Pos 18UL 2498 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_A_ENABLE_Msk 0x40000UL 2499 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_B_Pos 19UL 2500 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_B_Msk 0xF80000UL 2501 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_B_ENABLE_Pos 24UL 2502 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_B_ENABLE_Msk 0x1000000UL 2503 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_C_Pos 25UL 2504 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_C_Msk 0x3E000000UL 2505 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_C_ENABLE_Pos 30UL 2506 #define ETH_SCREENING_TYPE_2_REGISTER_11_COMPARE_C_ENABLE_Msk 0x40000000UL 2507 #define ETH_SCREENING_TYPE_2_REGISTER_11_RESERVED_31_Pos 31UL 2508 #define ETH_SCREENING_TYPE_2_REGISTER_11_RESERVED_31_Msk 0x80000000UL 2509 /* ETH.SCREENING_TYPE_2_REGISTER_12 */ 2510 #define ETH_SCREENING_TYPE_2_REGISTER_12_QUEUE_NUMBER_Pos 0UL 2511 #define ETH_SCREENING_TYPE_2_REGISTER_12_QUEUE_NUMBER_Msk 0xFUL 2512 #define ETH_SCREENING_TYPE_2_REGISTER_12_VLAN_PRIORITY_Pos 4UL 2513 #define ETH_SCREENING_TYPE_2_REGISTER_12_VLAN_PRIORITY_Msk 0x70UL 2514 #define ETH_SCREENING_TYPE_2_REGISTER_12_RESERVED_7_Pos 7UL 2515 #define ETH_SCREENING_TYPE_2_REGISTER_12_RESERVED_7_Msk 0x80UL 2516 #define ETH_SCREENING_TYPE_2_REGISTER_12_VLAN_ENABLE_Pos 8UL 2517 #define ETH_SCREENING_TYPE_2_REGISTER_12_VLAN_ENABLE_Msk 0x100UL 2518 #define ETH_SCREENING_TYPE_2_REGISTER_12_INDEX_Pos 9UL 2519 #define ETH_SCREENING_TYPE_2_REGISTER_12_INDEX_Msk 0xE00UL 2520 #define ETH_SCREENING_TYPE_2_REGISTER_12_ETHERTYPE_ENABLE_Pos 12UL 2521 #define ETH_SCREENING_TYPE_2_REGISTER_12_ETHERTYPE_ENABLE_Msk 0x1000UL 2522 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_A_Pos 13UL 2523 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_A_Msk 0x3E000UL 2524 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_A_ENABLE_Pos 18UL 2525 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_A_ENABLE_Msk 0x40000UL 2526 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_B_Pos 19UL 2527 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_B_Msk 0xF80000UL 2528 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_B_ENABLE_Pos 24UL 2529 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_B_ENABLE_Msk 0x1000000UL 2530 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_C_Pos 25UL 2531 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_C_Msk 0x3E000000UL 2532 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_C_ENABLE_Pos 30UL 2533 #define ETH_SCREENING_TYPE_2_REGISTER_12_COMPARE_C_ENABLE_Msk 0x40000000UL 2534 #define ETH_SCREENING_TYPE_2_REGISTER_12_RESERVED_31_Pos 31UL 2535 #define ETH_SCREENING_TYPE_2_REGISTER_12_RESERVED_31_Msk 0x80000000UL 2536 /* ETH.SCREENING_TYPE_2_REGISTER_13 */ 2537 #define ETH_SCREENING_TYPE_2_REGISTER_13_QUEUE_NUMBER_Pos 0UL 2538 #define ETH_SCREENING_TYPE_2_REGISTER_13_QUEUE_NUMBER_Msk 0xFUL 2539 #define ETH_SCREENING_TYPE_2_REGISTER_13_VLAN_PRIORITY_Pos 4UL 2540 #define ETH_SCREENING_TYPE_2_REGISTER_13_VLAN_PRIORITY_Msk 0x70UL 2541 #define ETH_SCREENING_TYPE_2_REGISTER_13_RESERVED_7_Pos 7UL 2542 #define ETH_SCREENING_TYPE_2_REGISTER_13_RESERVED_7_Msk 0x80UL 2543 #define ETH_SCREENING_TYPE_2_REGISTER_13_VLAN_ENABLE_Pos 8UL 2544 #define ETH_SCREENING_TYPE_2_REGISTER_13_VLAN_ENABLE_Msk 0x100UL 2545 #define ETH_SCREENING_TYPE_2_REGISTER_13_INDEX_Pos 9UL 2546 #define ETH_SCREENING_TYPE_2_REGISTER_13_INDEX_Msk 0xE00UL 2547 #define ETH_SCREENING_TYPE_2_REGISTER_13_ETHERTYPE_ENABLE_Pos 12UL 2548 #define ETH_SCREENING_TYPE_2_REGISTER_13_ETHERTYPE_ENABLE_Msk 0x1000UL 2549 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_A_Pos 13UL 2550 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_A_Msk 0x3E000UL 2551 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_A_ENABLE_Pos 18UL 2552 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_A_ENABLE_Msk 0x40000UL 2553 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_B_Pos 19UL 2554 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_B_Msk 0xF80000UL 2555 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_B_ENABLE_Pos 24UL 2556 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_B_ENABLE_Msk 0x1000000UL 2557 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_C_Pos 25UL 2558 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_C_Msk 0x3E000000UL 2559 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_C_ENABLE_Pos 30UL 2560 #define ETH_SCREENING_TYPE_2_REGISTER_13_COMPARE_C_ENABLE_Msk 0x40000000UL 2561 #define ETH_SCREENING_TYPE_2_REGISTER_13_RESERVED_31_Pos 31UL 2562 #define ETH_SCREENING_TYPE_2_REGISTER_13_RESERVED_31_Msk 0x80000000UL 2563 /* ETH.SCREENING_TYPE_2_REGISTER_14 */ 2564 #define ETH_SCREENING_TYPE_2_REGISTER_14_QUEUE_NUMBER_Pos 0UL 2565 #define ETH_SCREENING_TYPE_2_REGISTER_14_QUEUE_NUMBER_Msk 0xFUL 2566 #define ETH_SCREENING_TYPE_2_REGISTER_14_VLAN_PRIORITY_Pos 4UL 2567 #define ETH_SCREENING_TYPE_2_REGISTER_14_VLAN_PRIORITY_Msk 0x70UL 2568 #define ETH_SCREENING_TYPE_2_REGISTER_14_RESERVED_7_Pos 7UL 2569 #define ETH_SCREENING_TYPE_2_REGISTER_14_RESERVED_7_Msk 0x80UL 2570 #define ETH_SCREENING_TYPE_2_REGISTER_14_VLAN_ENABLE_Pos 8UL 2571 #define ETH_SCREENING_TYPE_2_REGISTER_14_VLAN_ENABLE_Msk 0x100UL 2572 #define ETH_SCREENING_TYPE_2_REGISTER_14_INDEX_Pos 9UL 2573 #define ETH_SCREENING_TYPE_2_REGISTER_14_INDEX_Msk 0xE00UL 2574 #define ETH_SCREENING_TYPE_2_REGISTER_14_ETHERTYPE_ENABLE_Pos 12UL 2575 #define ETH_SCREENING_TYPE_2_REGISTER_14_ETHERTYPE_ENABLE_Msk 0x1000UL 2576 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_A_Pos 13UL 2577 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_A_Msk 0x3E000UL 2578 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_A_ENABLE_Pos 18UL 2579 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_A_ENABLE_Msk 0x40000UL 2580 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_B_Pos 19UL 2581 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_B_Msk 0xF80000UL 2582 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_B_ENABLE_Pos 24UL 2583 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_B_ENABLE_Msk 0x1000000UL 2584 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_C_Pos 25UL 2585 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_C_Msk 0x3E000000UL 2586 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_C_ENABLE_Pos 30UL 2587 #define ETH_SCREENING_TYPE_2_REGISTER_14_COMPARE_C_ENABLE_Msk 0x40000000UL 2588 #define ETH_SCREENING_TYPE_2_REGISTER_14_RESERVED_31_Pos 31UL 2589 #define ETH_SCREENING_TYPE_2_REGISTER_14_RESERVED_31_Msk 0x80000000UL 2590 /* ETH.SCREENING_TYPE_2_REGISTER_15 */ 2591 #define ETH_SCREENING_TYPE_2_REGISTER_15_QUEUE_NUMBER_Pos 0UL 2592 #define ETH_SCREENING_TYPE_2_REGISTER_15_QUEUE_NUMBER_Msk 0xFUL 2593 #define ETH_SCREENING_TYPE_2_REGISTER_15_VLAN_PRIORITY_Pos 4UL 2594 #define ETH_SCREENING_TYPE_2_REGISTER_15_VLAN_PRIORITY_Msk 0x70UL 2595 #define ETH_SCREENING_TYPE_2_REGISTER_15_RESERVED_7_Pos 7UL 2596 #define ETH_SCREENING_TYPE_2_REGISTER_15_RESERVED_7_Msk 0x80UL 2597 #define ETH_SCREENING_TYPE_2_REGISTER_15_VLAN_ENABLE_Pos 8UL 2598 #define ETH_SCREENING_TYPE_2_REGISTER_15_VLAN_ENABLE_Msk 0x100UL 2599 #define ETH_SCREENING_TYPE_2_REGISTER_15_INDEX_Pos 9UL 2600 #define ETH_SCREENING_TYPE_2_REGISTER_15_INDEX_Msk 0xE00UL 2601 #define ETH_SCREENING_TYPE_2_REGISTER_15_ETHERTYPE_ENABLE_Pos 12UL 2602 #define ETH_SCREENING_TYPE_2_REGISTER_15_ETHERTYPE_ENABLE_Msk 0x1000UL 2603 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_A_Pos 13UL 2604 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_A_Msk 0x3E000UL 2605 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_A_ENABLE_Pos 18UL 2606 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_A_ENABLE_Msk 0x40000UL 2607 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_B_Pos 19UL 2608 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_B_Msk 0xF80000UL 2609 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_B_ENABLE_Pos 24UL 2610 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_B_ENABLE_Msk 0x1000000UL 2611 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_C_Pos 25UL 2612 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_C_Msk 0x3E000000UL 2613 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_C_ENABLE_Pos 30UL 2614 #define ETH_SCREENING_TYPE_2_REGISTER_15_COMPARE_C_ENABLE_Msk 0x40000000UL 2615 #define ETH_SCREENING_TYPE_2_REGISTER_15_RESERVED_31_Pos 31UL 2616 #define ETH_SCREENING_TYPE_2_REGISTER_15_RESERVED_31_Msk 0x80000000UL 2617 /* ETH.TX_SCHED_CTRL */ 2618 #define ETH_TX_SCHED_CTRL_TX_SCHED_Q0_Pos 0UL 2619 #define ETH_TX_SCHED_CTRL_TX_SCHED_Q0_Msk 0x3UL 2620 #define ETH_TX_SCHED_CTRL_TX_SCHED_Q1_Pos 2UL 2621 #define ETH_TX_SCHED_CTRL_TX_SCHED_Q1_Msk 0xCUL 2622 #define ETH_TX_SCHED_CTRL_TX_SCHED_Q2_Pos 4UL 2623 #define ETH_TX_SCHED_CTRL_TX_SCHED_Q2_Msk 0x30UL 2624 #define ETH_TX_SCHED_CTRL_TX_SCHED_Q3_Pos 6UL 2625 #define ETH_TX_SCHED_CTRL_TX_SCHED_Q3_Msk 0xC0UL 2626 #define ETH_TX_SCHED_CTRL_REMOVED_31_8_Pos 8UL 2627 #define ETH_TX_SCHED_CTRL_REMOVED_31_8_Msk 0xFFFFFF00UL 2628 /* ETH.BW_RATE_LIMIT_Q0TO3 */ 2629 #define ETH_BW_RATE_LIMIT_Q0TO3_DWRR_ETS_WEIGHT_Q0_Pos 0UL 2630 #define ETH_BW_RATE_LIMIT_Q0TO3_DWRR_ETS_WEIGHT_Q0_Msk 0xFFUL 2631 #define ETH_BW_RATE_LIMIT_Q0TO3_DWRR_ETS_WEIGHT_Q1_Pos 8UL 2632 #define ETH_BW_RATE_LIMIT_Q0TO3_DWRR_ETS_WEIGHT_Q1_Msk 0xFF00UL 2633 #define ETH_BW_RATE_LIMIT_Q0TO3_DWRR_ETS_WEIGHT_Q2_Pos 16UL 2634 #define ETH_BW_RATE_LIMIT_Q0TO3_DWRR_ETS_WEIGHT_Q2_Msk 0xFF0000UL 2635 #define ETH_BW_RATE_LIMIT_Q0TO3_DWRR_ETS_WEIGHT_Q3_Pos 24UL 2636 #define ETH_BW_RATE_LIMIT_Q0TO3_DWRR_ETS_WEIGHT_Q3_Msk 0xFF000000UL 2637 /* ETH.BW_RATE_LIMIT_Q4TO7 */ 2638 #define ETH_BW_RATE_LIMIT_Q4TO7_REMOVED_31_0_Pos 0UL 2639 #define ETH_BW_RATE_LIMIT_Q4TO7_REMOVED_31_0_Msk 0xFFFFFFFFUL 2640 /* ETH.BW_RATE_LIMIT_Q8TO11 */ 2641 #define ETH_BW_RATE_LIMIT_Q8TO11_REMOVED_31_0_Pos 0UL 2642 #define ETH_BW_RATE_LIMIT_Q8TO11_REMOVED_31_0_Msk 0xFFFFFFFFUL 2643 /* ETH.BW_RATE_LIMIT_Q12TO15 */ 2644 #define ETH_BW_RATE_LIMIT_Q12TO15_REMOVED_31_0_Pos 0UL 2645 #define ETH_BW_RATE_LIMIT_Q12TO15_REMOVED_31_0_Msk 0xFFFFFFFFUL 2646 /* ETH.TX_Q_SEG_ALLOC_Q0TO7 */ 2647 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_SEGMENT_ALLOC_Q0_Pos 0UL 2648 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_SEGMENT_ALLOC_Q0_Msk 0x7UL 2649 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_3_3_Pos 3UL 2650 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_3_3_Msk 0x8UL 2651 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_SEGMENT_ALLOC_Q1_Pos 4UL 2652 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_SEGMENT_ALLOC_Q1_Msk 0x70UL 2653 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_7_7_Pos 7UL 2654 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_7_7_Msk 0x80UL 2655 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_SEGMENT_ALLOC_Q2_Pos 8UL 2656 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_SEGMENT_ALLOC_Q2_Msk 0x700UL 2657 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_11_11_Pos 11UL 2658 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_11_11_Msk 0x800UL 2659 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_14_12_Pos 12UL 2660 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_14_12_Msk 0x7000UL 2661 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_15_15_Pos 15UL 2662 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_15_15_Msk 0x8000UL 2663 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_18_16_Pos 16UL 2664 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_18_16_Msk 0x70000UL 2665 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_19_19_Pos 19UL 2666 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_19_19_Msk 0x80000UL 2667 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_22_20_Pos 20UL 2668 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_22_20_Msk 0x700000UL 2669 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_23_Pos 23UL 2670 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_23_Msk 0x800000UL 2671 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_26_24_Pos 24UL 2672 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_26_24_Msk 0x7000000UL 2673 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_27_27_Pos 27UL 2674 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_27_27_Msk 0x8000000UL 2675 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_30_28_Pos 28UL 2676 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_REMOVED_30_28_Msk 0x70000000UL 2677 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_31_31_Pos 31UL 2678 #define ETH_TX_Q_SEG_ALLOC_Q0TO7_RESERVED_31_31_Msk 0x80000000UL 2679 /* ETH.TX_Q_SEG_ALLOC_Q8TO15 */ 2680 #define ETH_TX_Q_SEG_ALLOC_Q8TO15_REMOVED_31_0_Pos 0UL 2681 #define ETH_TX_Q_SEG_ALLOC_Q8TO15_REMOVED_31_0_Msk 0xFFFFFFFFUL 2682 /* ETH.RECEIVE_Q8_PTR */ 2683 #define ETH_RECEIVE_Q8_PTR_REMOVED_31_0_Pos 0UL 2684 #define ETH_RECEIVE_Q8_PTR_REMOVED_31_0_Msk 0xFFFFFFFFUL 2685 /* ETH.RECEIVE_Q15_PTR */ 2686 #define ETH_RECEIVE_Q15_PTR_REMOVED_31_0_Pos 0UL 2687 #define ETH_RECEIVE_Q15_PTR_REMOVED_31_0_Msk 0xFFFFFFFFUL 2688 /* ETH.DMA_RXBUF_SIZE_Q8 */ 2689 #define ETH_DMA_RXBUF_SIZE_Q8_REMOVED_31_0_Pos 0UL 2690 #define ETH_DMA_RXBUF_SIZE_Q8_REMOVED_31_0_Msk 0xFFFFFFFFUL 2691 /* ETH.DMA_RXBUF_SIZE_Q15 */ 2692 #define ETH_DMA_RXBUF_SIZE_Q15_REMOVED_31_0_Pos 0UL 2693 #define ETH_DMA_RXBUF_SIZE_Q15_REMOVED_31_0_Msk 0xFFFFFFFFUL 2694 /* ETH.INT_Q1_ENABLE */ 2695 #define ETH_INT_Q1_ENABLE_ENABLE_RECEIVE_COMPLETE_INTERRUPT_Pos 1UL 2696 #define ETH_INT_Q1_ENABLE_ENABLE_RECEIVE_COMPLETE_INTERRUPT_Msk 0x2UL 2697 #define ETH_INT_Q1_ENABLE_ENABLE_RX_USED_BIT_READ_INTERRUPT_Pos 2UL 2698 #define ETH_INT_Q1_ENABLE_ENABLE_RX_USED_BIT_READ_INTERRUPT_Msk 0x4UL 2699 #define ETH_INT_Q1_ENABLE_ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Pos 5UL 2700 #define ETH_INT_Q1_ENABLE_ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Msk 0x20UL 2701 #define ETH_INT_Q1_ENABLE_ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Pos 6UL 2702 #define ETH_INT_Q1_ENABLE_ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Msk 0x40UL 2703 #define ETH_INT_Q1_ENABLE_ENABLE_TRANSMIT_COMPLETE_INTERRUPT_Pos 7UL 2704 #define ETH_INT_Q1_ENABLE_ENABLE_TRANSMIT_COMPLETE_INTERRUPT_Msk 0x80UL 2705 #define ETH_INT_Q1_ENABLE_ENABLE_RESP_NOT_OK_INTERRUPT_Pos 11UL 2706 #define ETH_INT_Q1_ENABLE_ENABLE_RESP_NOT_OK_INTERRUPT_Msk 0x800UL 2707 /* ETH.INT_Q2_ENABLE */ 2708 #define ETH_INT_Q2_ENABLE_ENABLE_RECEIVE_COMPLETE_INTERRUPT_Pos 1UL 2709 #define ETH_INT_Q2_ENABLE_ENABLE_RECEIVE_COMPLETE_INTERRUPT_Msk 0x2UL 2710 #define ETH_INT_Q2_ENABLE_ENABLE_RX_USED_BIT_READ_INTERRUPT_Pos 2UL 2711 #define ETH_INT_Q2_ENABLE_ENABLE_RX_USED_BIT_READ_INTERRUPT_Msk 0x4UL 2712 #define ETH_INT_Q2_ENABLE_ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Pos 5UL 2713 #define ETH_INT_Q2_ENABLE_ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Msk 0x20UL 2714 #define ETH_INT_Q2_ENABLE_ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Pos 6UL 2715 #define ETH_INT_Q2_ENABLE_ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Msk 0x40UL 2716 #define ETH_INT_Q2_ENABLE_ENABLE_TRANSMIT_COMPLETE_INTERRUPT_Pos 7UL 2717 #define ETH_INT_Q2_ENABLE_ENABLE_TRANSMIT_COMPLETE_INTERRUPT_Msk 0x80UL 2718 #define ETH_INT_Q2_ENABLE_ENABLE_RESP_NOT_OK_INTERRUPT_Pos 11UL 2719 #define ETH_INT_Q2_ENABLE_ENABLE_RESP_NOT_OK_INTERRUPT_Msk 0x800UL 2720 /* ETH.INT_Q3_ENABLE */ 2721 #define ETH_INT_Q3_ENABLE_REMOVED_31_0_Pos 0UL 2722 #define ETH_INT_Q3_ENABLE_REMOVED_31_0_Msk 0xFFFFFFFFUL 2723 /* ETH.INT_Q7_ENABLE */ 2724 #define ETH_INT_Q7_ENABLE_REMOVED_31_0_Pos 0UL 2725 #define ETH_INT_Q7_ENABLE_REMOVED_31_0_Msk 0xFFFFFFFFUL 2726 /* ETH.INT_Q1_DISABLE */ 2727 #define ETH_INT_Q1_DISABLE_DISABLE_RECEIVE_COMPLETE_INTERRUPT_Pos 1UL 2728 #define ETH_INT_Q1_DISABLE_DISABLE_RECEIVE_COMPLETE_INTERRUPT_Msk 0x2UL 2729 #define ETH_INT_Q1_DISABLE_DISABLE_RX_USED_BIT_READ_INTERRUPT_Pos 2UL 2730 #define ETH_INT_Q1_DISABLE_DISABLE_RX_USED_BIT_READ_INTERRUPT_Msk 0x4UL 2731 #define ETH_INT_Q1_DISABLE_DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Pos 5UL 2732 #define ETH_INT_Q1_DISABLE_DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Msk 0x20UL 2733 #define ETH_INT_Q1_DISABLE_DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Pos 6UL 2734 #define ETH_INT_Q1_DISABLE_DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Msk 0x40UL 2735 #define ETH_INT_Q1_DISABLE_DISABLE_TRANSMIT_COMPLETE_INTERRUPT_Pos 7UL 2736 #define ETH_INT_Q1_DISABLE_DISABLE_TRANSMIT_COMPLETE_INTERRUPT_Msk 0x80UL 2737 #define ETH_INT_Q1_DISABLE_DISABLE_RESP_NOT_OK_INTERRUPT_Pos 11UL 2738 #define ETH_INT_Q1_DISABLE_DISABLE_RESP_NOT_OK_INTERRUPT_Msk 0x800UL 2739 /* ETH.INT_Q2_DISABLE */ 2740 #define ETH_INT_Q2_DISABLE_DISABLE_RECEIVE_COMPLETE_INTERRUPT_Pos 1UL 2741 #define ETH_INT_Q2_DISABLE_DISABLE_RECEIVE_COMPLETE_INTERRUPT_Msk 0x2UL 2742 #define ETH_INT_Q2_DISABLE_DISABLE_RX_USED_BIT_READ_INTERRUPT_Pos 2UL 2743 #define ETH_INT_Q2_DISABLE_DISABLE_RX_USED_BIT_READ_INTERRUPT_Msk 0x4UL 2744 #define ETH_INT_Q2_DISABLE_DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Pos 5UL 2745 #define ETH_INT_Q2_DISABLE_DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_Msk 0x20UL 2746 #define ETH_INT_Q2_DISABLE_DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Pos 6UL 2747 #define ETH_INT_Q2_DISABLE_DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_Msk 0x40UL 2748 #define ETH_INT_Q2_DISABLE_DISABLE_TRANSMIT_COMPLETE_INTERRUPT_Pos 7UL 2749 #define ETH_INT_Q2_DISABLE_DISABLE_TRANSMIT_COMPLETE_INTERRUPT_Msk 0x80UL 2750 #define ETH_INT_Q2_DISABLE_DISABLE_RESP_NOT_OK_INTERRUPT_Pos 11UL 2751 #define ETH_INT_Q2_DISABLE_DISABLE_RESP_NOT_OK_INTERRUPT_Msk 0x800UL 2752 /* ETH.INT_Q3_DISABLE */ 2753 #define ETH_INT_Q3_DISABLE_REMOVED_31_0_Pos 0UL 2754 #define ETH_INT_Q3_DISABLE_REMOVED_31_0_Msk 0xFFFFFFFFUL 2755 /* ETH.INT_Q7_DISABLE */ 2756 #define ETH_INT_Q7_DISABLE_REMOVED_31_0_Pos 0UL 2757 #define ETH_INT_Q7_DISABLE_REMOVED_31_0_Msk 0xFFFFFFFFUL 2758 /* ETH.INT_Q1_MASK */ 2759 #define ETH_INT_Q1_MASK_RECEIVE_COMPLETE_INTERRUPT_MASK_Pos 1UL 2760 #define ETH_INT_Q1_MASK_RECEIVE_COMPLETE_INTERRUPT_MASK_Msk 0x2UL 2761 #define ETH_INT_Q1_MASK_RX_USED_INTERRUPT_MASK_Pos 2UL 2762 #define ETH_INT_Q1_MASK_RX_USED_INTERRUPT_MASK_Msk 0x4UL 2763 #define ETH_INT_Q1_MASK_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK_Pos 5UL 2764 #define ETH_INT_Q1_MASK_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK_Msk 0x20UL 2765 #define ETH_INT_Q1_MASK_AMBA_ERROR_INTERRUPT_MASK_Pos 6UL 2766 #define ETH_INT_Q1_MASK_AMBA_ERROR_INTERRUPT_MASK_Msk 0x40UL 2767 #define ETH_INT_Q1_MASK_TRANSMIT_COMPLETE_INTERRUPT_MASK_Pos 7UL 2768 #define ETH_INT_Q1_MASK_TRANSMIT_COMPLETE_INTERRUPT_MASK_Msk 0x80UL 2769 #define ETH_INT_Q1_MASK_RESP_NOT_OK_INTERRUPT_MASK_Pos 11UL 2770 #define ETH_INT_Q1_MASK_RESP_NOT_OK_INTERRUPT_MASK_Msk 0x800UL 2771 /* ETH.INT_Q2_MASK */ 2772 #define ETH_INT_Q2_MASK_RECEIVE_COMPLETE_INTERRUPT_MASK_Pos 1UL 2773 #define ETH_INT_Q2_MASK_RECEIVE_COMPLETE_INTERRUPT_MASK_Msk 0x2UL 2774 #define ETH_INT_Q2_MASK_RX_USED_INTERRUPT_MASK_Pos 2UL 2775 #define ETH_INT_Q2_MASK_RX_USED_INTERRUPT_MASK_Msk 0x4UL 2776 #define ETH_INT_Q2_MASK_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK_Pos 5UL 2777 #define ETH_INT_Q2_MASK_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK_Msk 0x20UL 2778 #define ETH_INT_Q2_MASK_AMBA_ERROR_INTERRUPT_MASK_Pos 6UL 2779 #define ETH_INT_Q2_MASK_AMBA_ERROR_INTERRUPT_MASK_Msk 0x40UL 2780 #define ETH_INT_Q2_MASK_TRANSMIT_COMPLETE_INTERRUPT_MASK_Pos 7UL 2781 #define ETH_INT_Q2_MASK_TRANSMIT_COMPLETE_INTERRUPT_MASK_Msk 0x80UL 2782 #define ETH_INT_Q2_MASK_RESP_NOT_OK_INTERRUPT_MASK_Pos 11UL 2783 #define ETH_INT_Q2_MASK_RESP_NOT_OK_INTERRUPT_MASK_Msk 0x800UL 2784 /* ETH.INT_Q3_MASK */ 2785 #define ETH_INT_Q3_MASK_REMOVED_31_0_Pos 0UL 2786 #define ETH_INT_Q3_MASK_REMOVED_31_0_Msk 0xFFFFFFFFUL 2787 /* ETH.INT_Q7_MASK */ 2788 #define ETH_INT_Q7_MASK_REMOVED_31_0_Pos 0UL 2789 #define ETH_INT_Q7_MASK_REMOVED_31_0_Msk 0xFFFFFFFFUL 2790 /* ETH.INT_Q8_ENABLE */ 2791 #define ETH_INT_Q8_ENABLE_REMOVED_31_0_Pos 0UL 2792 #define ETH_INT_Q8_ENABLE_REMOVED_31_0_Msk 0xFFFFFFFFUL 2793 /* ETH.INT_Q15_ENABLE */ 2794 #define ETH_INT_Q15_ENABLE_REMOVED_31_0_Pos 0UL 2795 #define ETH_INT_Q15_ENABLE_REMOVED_31_0_Msk 0xFFFFFFFFUL 2796 /* ETH.INT_Q8_DISABLE */ 2797 #define ETH_INT_Q8_DISABLE_REMOVED_31_0_Pos 0UL 2798 #define ETH_INT_Q8_DISABLE_REMOVED_31_0_Msk 0xFFFFFFFFUL 2799 /* ETH.INT_Q15_DISABLE */ 2800 #define ETH_INT_Q15_DISABLE_REMOVED_31_0_Pos 0UL 2801 #define ETH_INT_Q15_DISABLE_REMOVED_31_0_Msk 0xFFFFFFFFUL 2802 /* ETH.INT_Q8_MASK */ 2803 #define ETH_INT_Q8_MASK_REMOVED_31_0_Pos 0UL 2804 #define ETH_INT_Q8_MASK_REMOVED_31_0_Msk 0xFFFFFFFFUL 2805 /* ETH.INT_Q15_MASK */ 2806 #define ETH_INT_Q15_MASK_REMOVED_31_0_Pos 0UL 2807 #define ETH_INT_Q15_MASK_REMOVED_31_0_Msk 0xFFFFFFFFUL 2808 /* ETH.SCREENING_TYPE_2_ETHERTYPE_REG_0 */ 2809 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_0_COMPARE_VALUE_Pos 0UL 2810 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_0_COMPARE_VALUE_Msk 0xFFFFUL 2811 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_0_RESERVED_31_16_Pos 16UL 2812 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_0_RESERVED_31_16_Msk 0xFFFF0000UL 2813 /* ETH.SCREENING_TYPE_2_ETHERTYPE_REG_1 */ 2814 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_1_COMPARE_VALUE_Pos 0UL 2815 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_1_COMPARE_VALUE_Msk 0xFFFFUL 2816 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_1_RESERVED_31_16_Pos 16UL 2817 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_1_RESERVED_31_16_Msk 0xFFFF0000UL 2818 /* ETH.SCREENING_TYPE_2_ETHERTYPE_REG_2 */ 2819 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_2_COMPARE_VALUE_Pos 0UL 2820 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_2_COMPARE_VALUE_Msk 0xFFFFUL 2821 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_2_RESERVED_31_16_Pos 16UL 2822 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_2_RESERVED_31_16_Msk 0xFFFF0000UL 2823 /* ETH.SCREENING_TYPE_2_ETHERTYPE_REG_3 */ 2824 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_3_COMPARE_VALUE_Pos 0UL 2825 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_3_COMPARE_VALUE_Msk 0xFFFFUL 2826 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_3_RESERVED_31_16_Pos 16UL 2827 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_3_RESERVED_31_16_Msk 0xFFFF0000UL 2828 /* ETH.SCREENING_TYPE_2_ETHERTYPE_REG_4 */ 2829 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_4_COMPARE_VALUE_Pos 0UL 2830 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_4_COMPARE_VALUE_Msk 0xFFFFUL 2831 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_4_RESERVED_31_16_Pos 16UL 2832 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_4_RESERVED_31_16_Msk 0xFFFF0000UL 2833 /* ETH.SCREENING_TYPE_2_ETHERTYPE_REG_5 */ 2834 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_5_COMPARE_VALUE_Pos 0UL 2835 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_5_COMPARE_VALUE_Msk 0xFFFFUL 2836 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_5_RESERVED_31_16_Pos 16UL 2837 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_5_RESERVED_31_16_Msk 0xFFFF0000UL 2838 /* ETH.SCREENING_TYPE_2_ETHERTYPE_REG_6 */ 2839 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_6_COMPARE_VALUE_Pos 0UL 2840 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_6_COMPARE_VALUE_Msk 0xFFFFUL 2841 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_6_RESERVED_31_16_Pos 16UL 2842 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_6_RESERVED_31_16_Msk 0xFFFF0000UL 2843 /* ETH.SCREENING_TYPE_2_ETHERTYPE_REG_7 */ 2844 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_7_COMPARE_VALUE_Pos 0UL 2845 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_7_COMPARE_VALUE_Msk 0xFFFFUL 2846 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_7_RESERVED_31_16_Pos 16UL 2847 #define ETH_SCREENING_TYPE_2_ETHERTYPE_REG_7_RESERVED_31_16_Msk 0xFFFF0000UL 2848 /* ETH.TYPE2_COMPARE_0_WORD_0 */ 2849 #define ETH_TYPE2_COMPARE_0_WORD_0_MASK_VALUE_Pos 0UL 2850 #define ETH_TYPE2_COMPARE_0_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2851 #define ETH_TYPE2_COMPARE_0_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2852 #define ETH_TYPE2_COMPARE_0_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2853 /* ETH.TYPE2_COMPARE_0_WORD_1 */ 2854 #define ETH_TYPE2_COMPARE_0_WORD_1_OFFSET_VALUE_Pos 0UL 2855 #define ETH_TYPE2_COMPARE_0_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2856 #define ETH_TYPE2_COMPARE_0_WORD_1_COMPARE_OFFSET_Pos 7UL 2857 #define ETH_TYPE2_COMPARE_0_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2858 #define ETH_TYPE2_COMPARE_0_WORD_1_DISABLE_MASK_Pos 9UL 2859 #define ETH_TYPE2_COMPARE_0_WORD_1_DISABLE_MASK_Msk 0x200UL 2860 #define ETH_TYPE2_COMPARE_0_WORD_1_RESERVED_31_10_Pos 10UL 2861 #define ETH_TYPE2_COMPARE_0_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2862 /* ETH.TYPE2_COMPARE_1_WORD_0 */ 2863 #define ETH_TYPE2_COMPARE_1_WORD_0_MASK_VALUE_Pos 0UL 2864 #define ETH_TYPE2_COMPARE_1_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2865 #define ETH_TYPE2_COMPARE_1_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2866 #define ETH_TYPE2_COMPARE_1_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2867 /* ETH.TYPE2_COMPARE_1_WORD_1 */ 2868 #define ETH_TYPE2_COMPARE_1_WORD_1_OFFSET_VALUE_Pos 0UL 2869 #define ETH_TYPE2_COMPARE_1_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2870 #define ETH_TYPE2_COMPARE_1_WORD_1_COMPARE_OFFSET_Pos 7UL 2871 #define ETH_TYPE2_COMPARE_1_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2872 #define ETH_TYPE2_COMPARE_1_WORD_1_DISABLE_MASK_Pos 9UL 2873 #define ETH_TYPE2_COMPARE_1_WORD_1_DISABLE_MASK_Msk 0x200UL 2874 #define ETH_TYPE2_COMPARE_1_WORD_1_RESERVED_31_10_Pos 10UL 2875 #define ETH_TYPE2_COMPARE_1_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2876 /* ETH.TYPE2_COMPARE_2_WORD_0 */ 2877 #define ETH_TYPE2_COMPARE_2_WORD_0_MASK_VALUE_Pos 0UL 2878 #define ETH_TYPE2_COMPARE_2_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2879 #define ETH_TYPE2_COMPARE_2_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2880 #define ETH_TYPE2_COMPARE_2_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2881 /* ETH.TYPE2_COMPARE_2_WORD_1 */ 2882 #define ETH_TYPE2_COMPARE_2_WORD_1_OFFSET_VALUE_Pos 0UL 2883 #define ETH_TYPE2_COMPARE_2_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2884 #define ETH_TYPE2_COMPARE_2_WORD_1_COMPARE_OFFSET_Pos 7UL 2885 #define ETH_TYPE2_COMPARE_2_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2886 #define ETH_TYPE2_COMPARE_2_WORD_1_DISABLE_MASK_Pos 9UL 2887 #define ETH_TYPE2_COMPARE_2_WORD_1_DISABLE_MASK_Msk 0x200UL 2888 #define ETH_TYPE2_COMPARE_2_WORD_1_RESERVED_31_10_Pos 10UL 2889 #define ETH_TYPE2_COMPARE_2_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2890 /* ETH.TYPE2_COMPARE_3_WORD_0 */ 2891 #define ETH_TYPE2_COMPARE_3_WORD_0_MASK_VALUE_Pos 0UL 2892 #define ETH_TYPE2_COMPARE_3_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2893 #define ETH_TYPE2_COMPARE_3_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2894 #define ETH_TYPE2_COMPARE_3_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2895 /* ETH.TYPE2_COMPARE_3_WORD_1 */ 2896 #define ETH_TYPE2_COMPARE_3_WORD_1_OFFSET_VALUE_Pos 0UL 2897 #define ETH_TYPE2_COMPARE_3_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2898 #define ETH_TYPE2_COMPARE_3_WORD_1_COMPARE_OFFSET_Pos 7UL 2899 #define ETH_TYPE2_COMPARE_3_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2900 #define ETH_TYPE2_COMPARE_3_WORD_1_DISABLE_MASK_Pos 9UL 2901 #define ETH_TYPE2_COMPARE_3_WORD_1_DISABLE_MASK_Msk 0x200UL 2902 #define ETH_TYPE2_COMPARE_3_WORD_1_RESERVED_31_10_Pos 10UL 2903 #define ETH_TYPE2_COMPARE_3_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2904 /* ETH.TYPE2_COMPARE_4_WORD_0 */ 2905 #define ETH_TYPE2_COMPARE_4_WORD_0_MASK_VALUE_Pos 0UL 2906 #define ETH_TYPE2_COMPARE_4_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2907 #define ETH_TYPE2_COMPARE_4_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2908 #define ETH_TYPE2_COMPARE_4_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2909 /* ETH.TYPE2_COMPARE_4_WORD_1 */ 2910 #define ETH_TYPE2_COMPARE_4_WORD_1_OFFSET_VALUE_Pos 0UL 2911 #define ETH_TYPE2_COMPARE_4_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2912 #define ETH_TYPE2_COMPARE_4_WORD_1_COMPARE_OFFSET_Pos 7UL 2913 #define ETH_TYPE2_COMPARE_4_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2914 #define ETH_TYPE2_COMPARE_4_WORD_1_DISABLE_MASK_Pos 9UL 2915 #define ETH_TYPE2_COMPARE_4_WORD_1_DISABLE_MASK_Msk 0x200UL 2916 #define ETH_TYPE2_COMPARE_4_WORD_1_RESERVED_31_10_Pos 10UL 2917 #define ETH_TYPE2_COMPARE_4_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2918 /* ETH.TYPE2_COMPARE_5_WORD_0 */ 2919 #define ETH_TYPE2_COMPARE_5_WORD_0_MASK_VALUE_Pos 0UL 2920 #define ETH_TYPE2_COMPARE_5_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2921 #define ETH_TYPE2_COMPARE_5_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2922 #define ETH_TYPE2_COMPARE_5_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2923 /* ETH.TYPE2_COMPARE_5_WORD_1 */ 2924 #define ETH_TYPE2_COMPARE_5_WORD_1_OFFSET_VALUE_Pos 0UL 2925 #define ETH_TYPE2_COMPARE_5_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2926 #define ETH_TYPE2_COMPARE_5_WORD_1_COMPARE_OFFSET_Pos 7UL 2927 #define ETH_TYPE2_COMPARE_5_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2928 #define ETH_TYPE2_COMPARE_5_WORD_1_DISABLE_MASK_Pos 9UL 2929 #define ETH_TYPE2_COMPARE_5_WORD_1_DISABLE_MASK_Msk 0x200UL 2930 #define ETH_TYPE2_COMPARE_5_WORD_1_RESERVED_31_10_Pos 10UL 2931 #define ETH_TYPE2_COMPARE_5_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2932 /* ETH.TYPE2_COMPARE_6_WORD_0 */ 2933 #define ETH_TYPE2_COMPARE_6_WORD_0_MASK_VALUE_Pos 0UL 2934 #define ETH_TYPE2_COMPARE_6_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2935 #define ETH_TYPE2_COMPARE_6_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2936 #define ETH_TYPE2_COMPARE_6_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2937 /* ETH.TYPE2_COMPARE_6_WORD_1 */ 2938 #define ETH_TYPE2_COMPARE_6_WORD_1_OFFSET_VALUE_Pos 0UL 2939 #define ETH_TYPE2_COMPARE_6_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2940 #define ETH_TYPE2_COMPARE_6_WORD_1_COMPARE_OFFSET_Pos 7UL 2941 #define ETH_TYPE2_COMPARE_6_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2942 #define ETH_TYPE2_COMPARE_6_WORD_1_DISABLE_MASK_Pos 9UL 2943 #define ETH_TYPE2_COMPARE_6_WORD_1_DISABLE_MASK_Msk 0x200UL 2944 #define ETH_TYPE2_COMPARE_6_WORD_1_RESERVED_31_10_Pos 10UL 2945 #define ETH_TYPE2_COMPARE_6_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2946 /* ETH.TYPE2_COMPARE_7_WORD_0 */ 2947 #define ETH_TYPE2_COMPARE_7_WORD_0_MASK_VALUE_Pos 0UL 2948 #define ETH_TYPE2_COMPARE_7_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2949 #define ETH_TYPE2_COMPARE_7_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2950 #define ETH_TYPE2_COMPARE_7_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2951 /* ETH.TYPE2_COMPARE_7_WORD_1 */ 2952 #define ETH_TYPE2_COMPARE_7_WORD_1_OFFSET_VALUE_Pos 0UL 2953 #define ETH_TYPE2_COMPARE_7_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2954 #define ETH_TYPE2_COMPARE_7_WORD_1_COMPARE_OFFSET_Pos 7UL 2955 #define ETH_TYPE2_COMPARE_7_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2956 #define ETH_TYPE2_COMPARE_7_WORD_1_DISABLE_MASK_Pos 9UL 2957 #define ETH_TYPE2_COMPARE_7_WORD_1_DISABLE_MASK_Msk 0x200UL 2958 #define ETH_TYPE2_COMPARE_7_WORD_1_RESERVED_31_10_Pos 10UL 2959 #define ETH_TYPE2_COMPARE_7_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2960 /* ETH.TYPE2_COMPARE_8_WORD_0 */ 2961 #define ETH_TYPE2_COMPARE_8_WORD_0_MASK_VALUE_Pos 0UL 2962 #define ETH_TYPE2_COMPARE_8_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2963 #define ETH_TYPE2_COMPARE_8_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2964 #define ETH_TYPE2_COMPARE_8_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2965 /* ETH.TYPE2_COMPARE_8_WORD_1 */ 2966 #define ETH_TYPE2_COMPARE_8_WORD_1_OFFSET_VALUE_Pos 0UL 2967 #define ETH_TYPE2_COMPARE_8_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2968 #define ETH_TYPE2_COMPARE_8_WORD_1_COMPARE_OFFSET_Pos 7UL 2969 #define ETH_TYPE2_COMPARE_8_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2970 #define ETH_TYPE2_COMPARE_8_WORD_1_DISABLE_MASK_Pos 9UL 2971 #define ETH_TYPE2_COMPARE_8_WORD_1_DISABLE_MASK_Msk 0x200UL 2972 #define ETH_TYPE2_COMPARE_8_WORD_1_RESERVED_31_10_Pos 10UL 2973 #define ETH_TYPE2_COMPARE_8_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2974 /* ETH.TYPE2_COMPARE_9_WORD_0 */ 2975 #define ETH_TYPE2_COMPARE_9_WORD_0_MASK_VALUE_Pos 0UL 2976 #define ETH_TYPE2_COMPARE_9_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2977 #define ETH_TYPE2_COMPARE_9_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2978 #define ETH_TYPE2_COMPARE_9_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2979 /* ETH.TYPE2_COMPARE_9_WORD_1 */ 2980 #define ETH_TYPE2_COMPARE_9_WORD_1_OFFSET_VALUE_Pos 0UL 2981 #define ETH_TYPE2_COMPARE_9_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2982 #define ETH_TYPE2_COMPARE_9_WORD_1_COMPARE_OFFSET_Pos 7UL 2983 #define ETH_TYPE2_COMPARE_9_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2984 #define ETH_TYPE2_COMPARE_9_WORD_1_DISABLE_MASK_Pos 9UL 2985 #define ETH_TYPE2_COMPARE_9_WORD_1_DISABLE_MASK_Msk 0x200UL 2986 #define ETH_TYPE2_COMPARE_9_WORD_1_RESERVED_31_10_Pos 10UL 2987 #define ETH_TYPE2_COMPARE_9_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 2988 /* ETH.TYPE2_COMPARE_10_WORD_0 */ 2989 #define ETH_TYPE2_COMPARE_10_WORD_0_MASK_VALUE_Pos 0UL 2990 #define ETH_TYPE2_COMPARE_10_WORD_0_MASK_VALUE_Msk 0xFFFFUL 2991 #define ETH_TYPE2_COMPARE_10_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 2992 #define ETH_TYPE2_COMPARE_10_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 2993 /* ETH.TYPE2_COMPARE_10_WORD_1 */ 2994 #define ETH_TYPE2_COMPARE_10_WORD_1_OFFSET_VALUE_Pos 0UL 2995 #define ETH_TYPE2_COMPARE_10_WORD_1_OFFSET_VALUE_Msk 0x7FUL 2996 #define ETH_TYPE2_COMPARE_10_WORD_1_COMPARE_OFFSET_Pos 7UL 2997 #define ETH_TYPE2_COMPARE_10_WORD_1_COMPARE_OFFSET_Msk 0x180UL 2998 #define ETH_TYPE2_COMPARE_10_WORD_1_DISABLE_MASK_Pos 9UL 2999 #define ETH_TYPE2_COMPARE_10_WORD_1_DISABLE_MASK_Msk 0x200UL 3000 #define ETH_TYPE2_COMPARE_10_WORD_1_RESERVED_31_10_Pos 10UL 3001 #define ETH_TYPE2_COMPARE_10_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3002 /* ETH.TYPE2_COMPARE_11_WORD_0 */ 3003 #define ETH_TYPE2_COMPARE_11_WORD_0_MASK_VALUE_Pos 0UL 3004 #define ETH_TYPE2_COMPARE_11_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3005 #define ETH_TYPE2_COMPARE_11_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3006 #define ETH_TYPE2_COMPARE_11_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3007 /* ETH.TYPE2_COMPARE_11_WORD_1 */ 3008 #define ETH_TYPE2_COMPARE_11_WORD_1_OFFSET_VALUE_Pos 0UL 3009 #define ETH_TYPE2_COMPARE_11_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3010 #define ETH_TYPE2_COMPARE_11_WORD_1_COMPARE_OFFSET_Pos 7UL 3011 #define ETH_TYPE2_COMPARE_11_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3012 #define ETH_TYPE2_COMPARE_11_WORD_1_DISABLE_MASK_Pos 9UL 3013 #define ETH_TYPE2_COMPARE_11_WORD_1_DISABLE_MASK_Msk 0x200UL 3014 #define ETH_TYPE2_COMPARE_11_WORD_1_RESERVED_31_10_Pos 10UL 3015 #define ETH_TYPE2_COMPARE_11_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3016 /* ETH.TYPE2_COMPARE_12_WORD_0 */ 3017 #define ETH_TYPE2_COMPARE_12_WORD_0_MASK_VALUE_Pos 0UL 3018 #define ETH_TYPE2_COMPARE_12_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3019 #define ETH_TYPE2_COMPARE_12_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3020 #define ETH_TYPE2_COMPARE_12_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3021 /* ETH.TYPE2_COMPARE_12_WORD_1 */ 3022 #define ETH_TYPE2_COMPARE_12_WORD_1_OFFSET_VALUE_Pos 0UL 3023 #define ETH_TYPE2_COMPARE_12_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3024 #define ETH_TYPE2_COMPARE_12_WORD_1_COMPARE_OFFSET_Pos 7UL 3025 #define ETH_TYPE2_COMPARE_12_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3026 #define ETH_TYPE2_COMPARE_12_WORD_1_DISABLE_MASK_Pos 9UL 3027 #define ETH_TYPE2_COMPARE_12_WORD_1_DISABLE_MASK_Msk 0x200UL 3028 #define ETH_TYPE2_COMPARE_12_WORD_1_RESERVED_31_10_Pos 10UL 3029 #define ETH_TYPE2_COMPARE_12_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3030 /* ETH.TYPE2_COMPARE_13_WORD_0 */ 3031 #define ETH_TYPE2_COMPARE_13_WORD_0_MASK_VALUE_Pos 0UL 3032 #define ETH_TYPE2_COMPARE_13_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3033 #define ETH_TYPE2_COMPARE_13_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3034 #define ETH_TYPE2_COMPARE_13_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3035 /* ETH.TYPE2_COMPARE_13_WORD_1 */ 3036 #define ETH_TYPE2_COMPARE_13_WORD_1_OFFSET_VALUE_Pos 0UL 3037 #define ETH_TYPE2_COMPARE_13_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3038 #define ETH_TYPE2_COMPARE_13_WORD_1_COMPARE_OFFSET_Pos 7UL 3039 #define ETH_TYPE2_COMPARE_13_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3040 #define ETH_TYPE2_COMPARE_13_WORD_1_DISABLE_MASK_Pos 9UL 3041 #define ETH_TYPE2_COMPARE_13_WORD_1_DISABLE_MASK_Msk 0x200UL 3042 #define ETH_TYPE2_COMPARE_13_WORD_1_RESERVED_31_10_Pos 10UL 3043 #define ETH_TYPE2_COMPARE_13_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3044 /* ETH.TYPE2_COMPARE_14_WORD_0 */ 3045 #define ETH_TYPE2_COMPARE_14_WORD_0_MASK_VALUE_Pos 0UL 3046 #define ETH_TYPE2_COMPARE_14_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3047 #define ETH_TYPE2_COMPARE_14_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3048 #define ETH_TYPE2_COMPARE_14_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3049 /* ETH.TYPE2_COMPARE_14_WORD_1 */ 3050 #define ETH_TYPE2_COMPARE_14_WORD_1_OFFSET_VALUE_Pos 0UL 3051 #define ETH_TYPE2_COMPARE_14_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3052 #define ETH_TYPE2_COMPARE_14_WORD_1_COMPARE_OFFSET_Pos 7UL 3053 #define ETH_TYPE2_COMPARE_14_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3054 #define ETH_TYPE2_COMPARE_14_WORD_1_DISABLE_MASK_Pos 9UL 3055 #define ETH_TYPE2_COMPARE_14_WORD_1_DISABLE_MASK_Msk 0x200UL 3056 #define ETH_TYPE2_COMPARE_14_WORD_1_RESERVED_31_10_Pos 10UL 3057 #define ETH_TYPE2_COMPARE_14_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3058 /* ETH.TYPE2_COMPARE_15_WORD_0 */ 3059 #define ETH_TYPE2_COMPARE_15_WORD_0_MASK_VALUE_Pos 0UL 3060 #define ETH_TYPE2_COMPARE_15_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3061 #define ETH_TYPE2_COMPARE_15_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3062 #define ETH_TYPE2_COMPARE_15_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3063 /* ETH.TYPE2_COMPARE_15_WORD_1 */ 3064 #define ETH_TYPE2_COMPARE_15_WORD_1_OFFSET_VALUE_Pos 0UL 3065 #define ETH_TYPE2_COMPARE_15_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3066 #define ETH_TYPE2_COMPARE_15_WORD_1_COMPARE_OFFSET_Pos 7UL 3067 #define ETH_TYPE2_COMPARE_15_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3068 #define ETH_TYPE2_COMPARE_15_WORD_1_DISABLE_MASK_Pos 9UL 3069 #define ETH_TYPE2_COMPARE_15_WORD_1_DISABLE_MASK_Msk 0x200UL 3070 #define ETH_TYPE2_COMPARE_15_WORD_1_RESERVED_31_10_Pos 10UL 3071 #define ETH_TYPE2_COMPARE_15_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3072 /* ETH.TYPE2_COMPARE_16_WORD_0 */ 3073 #define ETH_TYPE2_COMPARE_16_WORD_0_MASK_VALUE_Pos 0UL 3074 #define ETH_TYPE2_COMPARE_16_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3075 #define ETH_TYPE2_COMPARE_16_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3076 #define ETH_TYPE2_COMPARE_16_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3077 /* ETH.TYPE2_COMPARE_16_WORD_1 */ 3078 #define ETH_TYPE2_COMPARE_16_WORD_1_OFFSET_VALUE_Pos 0UL 3079 #define ETH_TYPE2_COMPARE_16_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3080 #define ETH_TYPE2_COMPARE_16_WORD_1_COMPARE_OFFSET_Pos 7UL 3081 #define ETH_TYPE2_COMPARE_16_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3082 #define ETH_TYPE2_COMPARE_16_WORD_1_DISABLE_MASK_Pos 9UL 3083 #define ETH_TYPE2_COMPARE_16_WORD_1_DISABLE_MASK_Msk 0x200UL 3084 #define ETH_TYPE2_COMPARE_16_WORD_1_RESERVED_31_10_Pos 10UL 3085 #define ETH_TYPE2_COMPARE_16_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3086 /* ETH.TYPE2_COMPARE_17_WORD_0 */ 3087 #define ETH_TYPE2_COMPARE_17_WORD_0_MASK_VALUE_Pos 0UL 3088 #define ETH_TYPE2_COMPARE_17_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3089 #define ETH_TYPE2_COMPARE_17_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3090 #define ETH_TYPE2_COMPARE_17_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3091 /* ETH.TYPE2_COMPARE_17_WORD_1 */ 3092 #define ETH_TYPE2_COMPARE_17_WORD_1_OFFSET_VALUE_Pos 0UL 3093 #define ETH_TYPE2_COMPARE_17_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3094 #define ETH_TYPE2_COMPARE_17_WORD_1_COMPARE_OFFSET_Pos 7UL 3095 #define ETH_TYPE2_COMPARE_17_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3096 #define ETH_TYPE2_COMPARE_17_WORD_1_DISABLE_MASK_Pos 9UL 3097 #define ETH_TYPE2_COMPARE_17_WORD_1_DISABLE_MASK_Msk 0x200UL 3098 #define ETH_TYPE2_COMPARE_17_WORD_1_RESERVED_31_10_Pos 10UL 3099 #define ETH_TYPE2_COMPARE_17_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3100 /* ETH.TYPE2_COMPARE_18_WORD_0 */ 3101 #define ETH_TYPE2_COMPARE_18_WORD_0_MASK_VALUE_Pos 0UL 3102 #define ETH_TYPE2_COMPARE_18_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3103 #define ETH_TYPE2_COMPARE_18_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3104 #define ETH_TYPE2_COMPARE_18_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3105 /* ETH.TYPE2_COMPARE_18_WORD_1 */ 3106 #define ETH_TYPE2_COMPARE_18_WORD_1_OFFSET_VALUE_Pos 0UL 3107 #define ETH_TYPE2_COMPARE_18_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3108 #define ETH_TYPE2_COMPARE_18_WORD_1_COMPARE_OFFSET_Pos 7UL 3109 #define ETH_TYPE2_COMPARE_18_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3110 #define ETH_TYPE2_COMPARE_18_WORD_1_DISABLE_MASK_Pos 9UL 3111 #define ETH_TYPE2_COMPARE_18_WORD_1_DISABLE_MASK_Msk 0x200UL 3112 #define ETH_TYPE2_COMPARE_18_WORD_1_RESERVED_31_10_Pos 10UL 3113 #define ETH_TYPE2_COMPARE_18_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3114 /* ETH.TYPE2_COMPARE_19_WORD_0 */ 3115 #define ETH_TYPE2_COMPARE_19_WORD_0_MASK_VALUE_Pos 0UL 3116 #define ETH_TYPE2_COMPARE_19_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3117 #define ETH_TYPE2_COMPARE_19_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3118 #define ETH_TYPE2_COMPARE_19_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3119 /* ETH.TYPE2_COMPARE_19_WORD_1 */ 3120 #define ETH_TYPE2_COMPARE_19_WORD_1_OFFSET_VALUE_Pos 0UL 3121 #define ETH_TYPE2_COMPARE_19_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3122 #define ETH_TYPE2_COMPARE_19_WORD_1_COMPARE_OFFSET_Pos 7UL 3123 #define ETH_TYPE2_COMPARE_19_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3124 #define ETH_TYPE2_COMPARE_19_WORD_1_DISABLE_MASK_Pos 9UL 3125 #define ETH_TYPE2_COMPARE_19_WORD_1_DISABLE_MASK_Msk 0x200UL 3126 #define ETH_TYPE2_COMPARE_19_WORD_1_RESERVED_31_10_Pos 10UL 3127 #define ETH_TYPE2_COMPARE_19_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3128 /* ETH.TYPE2_COMPARE_20_WORD_0 */ 3129 #define ETH_TYPE2_COMPARE_20_WORD_0_MASK_VALUE_Pos 0UL 3130 #define ETH_TYPE2_COMPARE_20_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3131 #define ETH_TYPE2_COMPARE_20_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3132 #define ETH_TYPE2_COMPARE_20_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3133 /* ETH.TYPE2_COMPARE_20_WORD_1 */ 3134 #define ETH_TYPE2_COMPARE_20_WORD_1_OFFSET_VALUE_Pos 0UL 3135 #define ETH_TYPE2_COMPARE_20_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3136 #define ETH_TYPE2_COMPARE_20_WORD_1_COMPARE_OFFSET_Pos 7UL 3137 #define ETH_TYPE2_COMPARE_20_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3138 #define ETH_TYPE2_COMPARE_20_WORD_1_DISABLE_MASK_Pos 9UL 3139 #define ETH_TYPE2_COMPARE_20_WORD_1_DISABLE_MASK_Msk 0x200UL 3140 #define ETH_TYPE2_COMPARE_20_WORD_1_RESERVED_31_10_Pos 10UL 3141 #define ETH_TYPE2_COMPARE_20_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3142 /* ETH.TYPE2_COMPARE_21_WORD_0 */ 3143 #define ETH_TYPE2_COMPARE_21_WORD_0_MASK_VALUE_Pos 0UL 3144 #define ETH_TYPE2_COMPARE_21_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3145 #define ETH_TYPE2_COMPARE_21_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3146 #define ETH_TYPE2_COMPARE_21_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3147 /* ETH.TYPE2_COMPARE_21_WORD_1 */ 3148 #define ETH_TYPE2_COMPARE_21_WORD_1_OFFSET_VALUE_Pos 0UL 3149 #define ETH_TYPE2_COMPARE_21_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3150 #define ETH_TYPE2_COMPARE_21_WORD_1_COMPARE_OFFSET_Pos 7UL 3151 #define ETH_TYPE2_COMPARE_21_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3152 #define ETH_TYPE2_COMPARE_21_WORD_1_DISABLE_MASK_Pos 9UL 3153 #define ETH_TYPE2_COMPARE_21_WORD_1_DISABLE_MASK_Msk 0x200UL 3154 #define ETH_TYPE2_COMPARE_21_WORD_1_RESERVED_31_10_Pos 10UL 3155 #define ETH_TYPE2_COMPARE_21_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3156 /* ETH.TYPE2_COMPARE_22_WORD_0 */ 3157 #define ETH_TYPE2_COMPARE_22_WORD_0_MASK_VALUE_Pos 0UL 3158 #define ETH_TYPE2_COMPARE_22_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3159 #define ETH_TYPE2_COMPARE_22_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3160 #define ETH_TYPE2_COMPARE_22_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3161 /* ETH.TYPE2_COMPARE_22_WORD_1 */ 3162 #define ETH_TYPE2_COMPARE_22_WORD_1_OFFSET_VALUE_Pos 0UL 3163 #define ETH_TYPE2_COMPARE_22_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3164 #define ETH_TYPE2_COMPARE_22_WORD_1_COMPARE_OFFSET_Pos 7UL 3165 #define ETH_TYPE2_COMPARE_22_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3166 #define ETH_TYPE2_COMPARE_22_WORD_1_DISABLE_MASK_Pos 9UL 3167 #define ETH_TYPE2_COMPARE_22_WORD_1_DISABLE_MASK_Msk 0x200UL 3168 #define ETH_TYPE2_COMPARE_22_WORD_1_RESERVED_31_10_Pos 10UL 3169 #define ETH_TYPE2_COMPARE_22_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3170 /* ETH.TYPE2_COMPARE_23_WORD_0 */ 3171 #define ETH_TYPE2_COMPARE_23_WORD_0_MASK_VALUE_Pos 0UL 3172 #define ETH_TYPE2_COMPARE_23_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3173 #define ETH_TYPE2_COMPARE_23_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3174 #define ETH_TYPE2_COMPARE_23_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3175 /* ETH.TYPE2_COMPARE_23_WORD_1 */ 3176 #define ETH_TYPE2_COMPARE_23_WORD_1_OFFSET_VALUE_Pos 0UL 3177 #define ETH_TYPE2_COMPARE_23_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3178 #define ETH_TYPE2_COMPARE_23_WORD_1_COMPARE_OFFSET_Pos 7UL 3179 #define ETH_TYPE2_COMPARE_23_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3180 #define ETH_TYPE2_COMPARE_23_WORD_1_DISABLE_MASK_Pos 9UL 3181 #define ETH_TYPE2_COMPARE_23_WORD_1_DISABLE_MASK_Msk 0x200UL 3182 #define ETH_TYPE2_COMPARE_23_WORD_1_RESERVED_31_10_Pos 10UL 3183 #define ETH_TYPE2_COMPARE_23_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3184 /* ETH.TYPE2_COMPARE_24_WORD_0 */ 3185 #define ETH_TYPE2_COMPARE_24_WORD_0_MASK_VALUE_Pos 0UL 3186 #define ETH_TYPE2_COMPARE_24_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3187 #define ETH_TYPE2_COMPARE_24_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3188 #define ETH_TYPE2_COMPARE_24_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3189 /* ETH.TYPE2_COMPARE_24_WORD_1 */ 3190 #define ETH_TYPE2_COMPARE_24_WORD_1_OFFSET_VALUE_Pos 0UL 3191 #define ETH_TYPE2_COMPARE_24_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3192 #define ETH_TYPE2_COMPARE_24_WORD_1_COMPARE_OFFSET_Pos 7UL 3193 #define ETH_TYPE2_COMPARE_24_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3194 #define ETH_TYPE2_COMPARE_24_WORD_1_DISABLE_MASK_Pos 9UL 3195 #define ETH_TYPE2_COMPARE_24_WORD_1_DISABLE_MASK_Msk 0x200UL 3196 #define ETH_TYPE2_COMPARE_24_WORD_1_RESERVED_31_10_Pos 10UL 3197 #define ETH_TYPE2_COMPARE_24_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3198 /* ETH.TYPE2_COMPARE_25_WORD_0 */ 3199 #define ETH_TYPE2_COMPARE_25_WORD_0_MASK_VALUE_Pos 0UL 3200 #define ETH_TYPE2_COMPARE_25_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3201 #define ETH_TYPE2_COMPARE_25_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3202 #define ETH_TYPE2_COMPARE_25_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3203 /* ETH.TYPE2_COMPARE_25_WORD_1 */ 3204 #define ETH_TYPE2_COMPARE_25_WORD_1_OFFSET_VALUE_Pos 0UL 3205 #define ETH_TYPE2_COMPARE_25_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3206 #define ETH_TYPE2_COMPARE_25_WORD_1_COMPARE_OFFSET_Pos 7UL 3207 #define ETH_TYPE2_COMPARE_25_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3208 #define ETH_TYPE2_COMPARE_25_WORD_1_DISABLE_MASK_Pos 9UL 3209 #define ETH_TYPE2_COMPARE_25_WORD_1_DISABLE_MASK_Msk 0x200UL 3210 #define ETH_TYPE2_COMPARE_25_WORD_1_RESERVED_31_10_Pos 10UL 3211 #define ETH_TYPE2_COMPARE_25_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3212 /* ETH.TYPE2_COMPARE_26_WORD_0 */ 3213 #define ETH_TYPE2_COMPARE_26_WORD_0_MASK_VALUE_Pos 0UL 3214 #define ETH_TYPE2_COMPARE_26_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3215 #define ETH_TYPE2_COMPARE_26_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3216 #define ETH_TYPE2_COMPARE_26_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3217 /* ETH.TYPE2_COMPARE_26_WORD_1 */ 3218 #define ETH_TYPE2_COMPARE_26_WORD_1_OFFSET_VALUE_Pos 0UL 3219 #define ETH_TYPE2_COMPARE_26_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3220 #define ETH_TYPE2_COMPARE_26_WORD_1_COMPARE_OFFSET_Pos 7UL 3221 #define ETH_TYPE2_COMPARE_26_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3222 #define ETH_TYPE2_COMPARE_26_WORD_1_DISABLE_MASK_Pos 9UL 3223 #define ETH_TYPE2_COMPARE_26_WORD_1_DISABLE_MASK_Msk 0x200UL 3224 #define ETH_TYPE2_COMPARE_26_WORD_1_RESERVED_31_10_Pos 10UL 3225 #define ETH_TYPE2_COMPARE_26_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3226 /* ETH.TYPE2_COMPARE_27_WORD_0 */ 3227 #define ETH_TYPE2_COMPARE_27_WORD_0_MASK_VALUE_Pos 0UL 3228 #define ETH_TYPE2_COMPARE_27_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3229 #define ETH_TYPE2_COMPARE_27_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3230 #define ETH_TYPE2_COMPARE_27_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3231 /* ETH.TYPE2_COMPARE_27_WORD_1 */ 3232 #define ETH_TYPE2_COMPARE_27_WORD_1_OFFSET_VALUE_Pos 0UL 3233 #define ETH_TYPE2_COMPARE_27_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3234 #define ETH_TYPE2_COMPARE_27_WORD_1_COMPARE_OFFSET_Pos 7UL 3235 #define ETH_TYPE2_COMPARE_27_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3236 #define ETH_TYPE2_COMPARE_27_WORD_1_DISABLE_MASK_Pos 9UL 3237 #define ETH_TYPE2_COMPARE_27_WORD_1_DISABLE_MASK_Msk 0x200UL 3238 #define ETH_TYPE2_COMPARE_27_WORD_1_RESERVED_31_10_Pos 10UL 3239 #define ETH_TYPE2_COMPARE_27_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3240 /* ETH.TYPE2_COMPARE_28_WORD_0 */ 3241 #define ETH_TYPE2_COMPARE_28_WORD_0_MASK_VALUE_Pos 0UL 3242 #define ETH_TYPE2_COMPARE_28_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3243 #define ETH_TYPE2_COMPARE_28_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3244 #define ETH_TYPE2_COMPARE_28_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3245 /* ETH.TYPE2_COMPARE_28_WORD_1 */ 3246 #define ETH_TYPE2_COMPARE_28_WORD_1_OFFSET_VALUE_Pos 0UL 3247 #define ETH_TYPE2_COMPARE_28_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3248 #define ETH_TYPE2_COMPARE_28_WORD_1_COMPARE_OFFSET_Pos 7UL 3249 #define ETH_TYPE2_COMPARE_28_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3250 #define ETH_TYPE2_COMPARE_28_WORD_1_DISABLE_MASK_Pos 9UL 3251 #define ETH_TYPE2_COMPARE_28_WORD_1_DISABLE_MASK_Msk 0x200UL 3252 #define ETH_TYPE2_COMPARE_28_WORD_1_RESERVED_31_10_Pos 10UL 3253 #define ETH_TYPE2_COMPARE_28_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3254 /* ETH.TYPE2_COMPARE_29_WORD_0 */ 3255 #define ETH_TYPE2_COMPARE_29_WORD_0_MASK_VALUE_Pos 0UL 3256 #define ETH_TYPE2_COMPARE_29_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3257 #define ETH_TYPE2_COMPARE_29_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3258 #define ETH_TYPE2_COMPARE_29_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3259 /* ETH.TYPE2_COMPARE_29_WORD_1 */ 3260 #define ETH_TYPE2_COMPARE_29_WORD_1_OFFSET_VALUE_Pos 0UL 3261 #define ETH_TYPE2_COMPARE_29_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3262 #define ETH_TYPE2_COMPARE_29_WORD_1_COMPARE_OFFSET_Pos 7UL 3263 #define ETH_TYPE2_COMPARE_29_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3264 #define ETH_TYPE2_COMPARE_29_WORD_1_DISABLE_MASK_Pos 9UL 3265 #define ETH_TYPE2_COMPARE_29_WORD_1_DISABLE_MASK_Msk 0x200UL 3266 #define ETH_TYPE2_COMPARE_29_WORD_1_RESERVED_31_10_Pos 10UL 3267 #define ETH_TYPE2_COMPARE_29_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3268 /* ETH.TYPE2_COMPARE_30_WORD_0 */ 3269 #define ETH_TYPE2_COMPARE_30_WORD_0_MASK_VALUE_Pos 0UL 3270 #define ETH_TYPE2_COMPARE_30_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3271 #define ETH_TYPE2_COMPARE_30_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3272 #define ETH_TYPE2_COMPARE_30_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3273 /* ETH.TYPE2_COMPARE_30_WORD_1 */ 3274 #define ETH_TYPE2_COMPARE_30_WORD_1_OFFSET_VALUE_Pos 0UL 3275 #define ETH_TYPE2_COMPARE_30_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3276 #define ETH_TYPE2_COMPARE_30_WORD_1_COMPARE_OFFSET_Pos 7UL 3277 #define ETH_TYPE2_COMPARE_30_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3278 #define ETH_TYPE2_COMPARE_30_WORD_1_DISABLE_MASK_Pos 9UL 3279 #define ETH_TYPE2_COMPARE_30_WORD_1_DISABLE_MASK_Msk 0x200UL 3280 #define ETH_TYPE2_COMPARE_30_WORD_1_RESERVED_31_10_Pos 10UL 3281 #define ETH_TYPE2_COMPARE_30_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3282 /* ETH.TYPE2_COMPARE_31_WORD_0 */ 3283 #define ETH_TYPE2_COMPARE_31_WORD_0_MASK_VALUE_Pos 0UL 3284 #define ETH_TYPE2_COMPARE_31_WORD_0_MASK_VALUE_Msk 0xFFFFUL 3285 #define ETH_TYPE2_COMPARE_31_WORD_0_COMPARE_VALUE_TYPE2_Pos 16UL 3286 #define ETH_TYPE2_COMPARE_31_WORD_0_COMPARE_VALUE_TYPE2_Msk 0xFFFF0000UL 3287 /* ETH.TYPE2_COMPARE_31_WORD_1 */ 3288 #define ETH_TYPE2_COMPARE_31_WORD_1_OFFSET_VALUE_Pos 0UL 3289 #define ETH_TYPE2_COMPARE_31_WORD_1_OFFSET_VALUE_Msk 0x7FUL 3290 #define ETH_TYPE2_COMPARE_31_WORD_1_COMPARE_OFFSET_Pos 7UL 3291 #define ETH_TYPE2_COMPARE_31_WORD_1_COMPARE_OFFSET_Msk 0x180UL 3292 #define ETH_TYPE2_COMPARE_31_WORD_1_DISABLE_MASK_Pos 9UL 3293 #define ETH_TYPE2_COMPARE_31_WORD_1_DISABLE_MASK_Msk 0x200UL 3294 #define ETH_TYPE2_COMPARE_31_WORD_1_RESERVED_31_10_Pos 10UL 3295 #define ETH_TYPE2_COMPARE_31_WORD_1_RESERVED_31_10_Msk 0xFFFFFC00UL 3296 3297 3298 #endif /* _CYIP_ETH_H_ */ 3299 3300 3301 /* [] END OF FILE */ 3302
