1 /***************************************************************************//** 2 * \file cyip_epass.h 3 * 4 * \brief 5 * PASS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_EPASS_H_ 28 #define _CYIP_EPASS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PASS 34 *******************************************************************************/ 35 36 #define PASS_SAR_CH_SECTION_SIZE 0x00000040UL 37 #define PASS_SAR_SECTION_SIZE 0x00001000UL 38 #define PASS_EPASS_MMIO_SECTION_SIZE 0x00001000UL 39 #define PASS_SECTION_SIZE 0x00100000UL 40 41 /** 42 * \brief Channel structure (PASS_SAR_CH) 43 */ 44 typedef struct { 45 __IOM uint32_t TR_CTL; /*!< 0x00000000 Trigger control. */ 46 __IOM uint32_t SAMPLE_CTL; /*!< 0x00000004 Sample control. */ 47 __IOM uint32_t POST_CTL; /*!< 0x00000008 Post processing control */ 48 __IOM uint32_t RANGE_CTL; /*!< 0x0000000C Range thresholds */ 49 __IOM uint32_t INTR; /*!< 0x00000010 Interrupt request register. */ 50 __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set request register */ 51 __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask register. */ 52 __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked request register */ 53 __IM uint32_t WORK; /*!< 0x00000020 Working data register */ 54 __IM uint32_t RESULT; /*!< 0x00000024 Result data register */ 55 __IM uint32_t GRP_STAT; /*!< 0x00000028 Group status register */ 56 __IM uint32_t RESERVED[3]; 57 __IOM uint32_t ENABLE; /*!< 0x00000038 Enable register */ 58 __IOM uint32_t TR_CMD; /*!< 0x0000003C Software triggers */ 59 } PASS_SAR_CH_V1_Type; /*!< Size = 64 (0x40) */ 60 61 /** 62 * \brief SAR ADC with Sequencer for S40E (PASS_SAR) 63 */ 64 typedef struct { 65 __IOM uint32_t CTL; /*!< 0x00000000 Analog control register. */ 66 __IOM uint32_t DIAG_CTL; /*!< 0x00000004 Diagnostic Reference control register. */ 67 __IM uint32_t RESERVED[2]; 68 __IOM uint32_t PRECOND_CTL; /*!< 0x00000010 Preconditioning control register. */ 69 __IM uint32_t RESERVED1[27]; 70 __IOM uint32_t ANA_CAL; /*!< 0x00000080 Current analog calibration values */ 71 __IOM uint32_t DIG_CAL; /*!< 0x00000084 Current digital calibration values */ 72 __IM uint32_t RESERVED2[2]; 73 __IOM uint32_t ANA_CAL_ALT; /*!< 0x00000090 Alternate analog calibration values */ 74 __IOM uint32_t DIG_CAL_ALT; /*!< 0x00000094 Alternate digital calibration values */ 75 __IOM uint32_t CAL_UPD_CMD; /*!< 0x00000098 Calibration update command */ 76 __IM uint32_t RESERVED3[25]; 77 __IM uint32_t TR_PEND; /*!< 0x00000100 Trigger pending status */ 78 __IM uint32_t RESERVED4[31]; 79 __IM uint32_t WORK_VALID; /*!< 0x00000180 Channel working data register 'valid' bits */ 80 __IM uint32_t WORK_RANGE; /*!< 0x00000184 Range detected */ 81 __IM uint32_t WORK_RANGE_HI; /*!< 0x00000188 Range detect above Hi flag */ 82 __IM uint32_t WORK_PULSE; /*!< 0x0000018C Pulse detected */ 83 __IM uint32_t RESERVED5[4]; 84 __IM uint32_t RESULT_VALID; /*!< 0x000001A0 Channel result data register 'valid' bits */ 85 __IM uint32_t RESULT_RANGE_HI; /*!< 0x000001A4 Channel Range above Hi flags */ 86 __IM uint32_t RESERVED6[22]; 87 __IM uint32_t STATUS; /*!< 0x00000200 Current status of internal SAR registers (mostly for debug) */ 88 __IM uint32_t AVG_STAT; /*!< 0x00000204 Current averaging status (for debug) */ 89 __IM uint32_t RESERVED7[382]; 90 PASS_SAR_CH_V1_Type CH[32]; /*!< 0x00000800 Channel structure */ 91 } PASS_SAR_V1_Type; /*!< Size = 4096 (0x1000) */ 92 93 /** 94 * \brief PASS top-level MMIO (Generic Triggers) (PASS_EPASS_MMIO) 95 */ 96 typedef struct { 97 __IOM uint32_t PASS_CTL; /*!< 0x00000000 PASS control register */ 98 __IM uint32_t RESERVED[7]; 99 __IOM uint32_t SAR_TR_IN_SEL[4]; /*!< 0x00000020 per SAR generic input trigger select */ 100 __IM uint32_t RESERVED1[4]; 101 __IOM uint32_t SAR_TR_OUT_SEL[4]; /*!< 0x00000040 per SAR generic output trigger select */ 102 __IM uint32_t RESERVED2[12]; 103 __IOM uint32_t TEST_CTL; /*!< 0x00000080 Test control bits */ 104 __IM uint32_t RESERVED3[991]; 105 } PASS_EPASS_MMIO_V1_Type; /*!< Size = 4096 (0x1000) */ 106 107 /** 108 * \brief Programmable Analog Subsystem for S40E (PASS) 109 */ 110 typedef struct { 111 PASS_SAR_V1_Type SAR[4]; /*!< 0x00000000 SAR ADC with Sequencer for S40E */ 112 __IM uint32_t RESERVED[241664]; 113 PASS_EPASS_MMIO_V1_Type EPASS_MMIO; /*!< 0x000F0000 PASS top-level MMIO (Generic Triggers) */ 114 } PASS_V1_Type; /*!< Size = 987136 (0xF1000) */ 115 116 117 /* PASS_SAR_CH.TR_CTL */ 118 #define PASS_SAR_CH_TR_CTL_SEL_Pos 0UL 119 #define PASS_SAR_CH_TR_CTL_SEL_Msk 0x7UL 120 #define PASS_SAR_CH_TR_CTL_PRIO_Pos 4UL 121 #define PASS_SAR_CH_TR_CTL_PRIO_Msk 0x70UL 122 #define PASS_SAR_CH_TR_CTL_PREEMPT_TYPE_Pos 8UL 123 #define PASS_SAR_CH_TR_CTL_PREEMPT_TYPE_Msk 0x300UL 124 #define PASS_SAR_CH_TR_CTL_GROUP_END_Pos 11UL 125 #define PASS_SAR_CH_TR_CTL_GROUP_END_Msk 0x800UL 126 #define PASS_SAR_CH_TR_CTL_DONE_LEVEL_Pos 31UL 127 #define PASS_SAR_CH_TR_CTL_DONE_LEVEL_Msk 0x80000000UL 128 /* PASS_SAR_CH.SAMPLE_CTL */ 129 #define PASS_SAR_CH_SAMPLE_CTL_PIN_ADDR_Pos 0UL 130 #define PASS_SAR_CH_SAMPLE_CTL_PIN_ADDR_Msk 0x3FUL 131 #define PASS_SAR_CH_SAMPLE_CTL_PORT_ADDR_Pos 6UL 132 #define PASS_SAR_CH_SAMPLE_CTL_PORT_ADDR_Msk 0xC0UL 133 #define PASS_SAR_CH_SAMPLE_CTL_EXT_MUX_SEL_Pos 8UL 134 #define PASS_SAR_CH_SAMPLE_CTL_EXT_MUX_SEL_Msk 0x700UL 135 #define PASS_SAR_CH_SAMPLE_CTL_EXT_MUX_EN_Pos 11UL 136 #define PASS_SAR_CH_SAMPLE_CTL_EXT_MUX_EN_Msk 0x800UL 137 #define PASS_SAR_CH_SAMPLE_CTL_PRECOND_MODE_Pos 12UL 138 #define PASS_SAR_CH_SAMPLE_CTL_PRECOND_MODE_Msk 0x3000UL 139 #define PASS_SAR_CH_SAMPLE_CTL_OVERLAP_DIAG_Pos 14UL 140 #define PASS_SAR_CH_SAMPLE_CTL_OVERLAP_DIAG_Msk 0xC000UL 141 #define PASS_SAR_CH_SAMPLE_CTL_SAMPLE_TIME_Pos 16UL 142 #define PASS_SAR_CH_SAMPLE_CTL_SAMPLE_TIME_Msk 0xFFF0000UL 143 #define PASS_SAR_CH_SAMPLE_CTL_ALT_CAL_Pos 31UL 144 #define PASS_SAR_CH_SAMPLE_CTL_ALT_CAL_Msk 0x80000000UL 145 /* PASS_SAR_CH.POST_CTL */ 146 #define PASS_SAR_CH_POST_CTL_POST_PROC_Pos 0UL 147 #define PASS_SAR_CH_POST_CTL_POST_PROC_Msk 0x7UL 148 #define PASS_SAR_CH_POST_CTL_LEFT_ALIGN_Pos 6UL 149 #define PASS_SAR_CH_POST_CTL_LEFT_ALIGN_Msk 0x40UL 150 #define PASS_SAR_CH_POST_CTL_SIGN_EXT_Pos 7UL 151 #define PASS_SAR_CH_POST_CTL_SIGN_EXT_Msk 0x80UL 152 #define PASS_SAR_CH_POST_CTL_AVG_CNT_Pos 8UL 153 #define PASS_SAR_CH_POST_CTL_AVG_CNT_Msk 0xFF00UL 154 #define PASS_SAR_CH_POST_CTL_SHIFT_R_Pos 16UL 155 #define PASS_SAR_CH_POST_CTL_SHIFT_R_Msk 0x1F0000UL 156 #define PASS_SAR_CH_POST_CTL_RANGE_MODE_Pos 22UL 157 #define PASS_SAR_CH_POST_CTL_RANGE_MODE_Msk 0xC00000UL 158 #define PASS_SAR_CH_POST_CTL_TR_DONE_GRP_VIO_Pos 25UL 159 #define PASS_SAR_CH_POST_CTL_TR_DONE_GRP_VIO_Msk 0x2000000UL 160 /* PASS_SAR_CH.RANGE_CTL */ 161 #define PASS_SAR_CH_RANGE_CTL_RANGE_LO_Pos 0UL 162 #define PASS_SAR_CH_RANGE_CTL_RANGE_LO_Msk 0xFFFFUL 163 #define PASS_SAR_CH_RANGE_CTL_RANGE_HI_Pos 16UL 164 #define PASS_SAR_CH_RANGE_CTL_RANGE_HI_Msk 0xFFFF0000UL 165 /* PASS_SAR_CH.INTR */ 166 #define PASS_SAR_CH_INTR_GRP_DONE_Pos 0UL 167 #define PASS_SAR_CH_INTR_GRP_DONE_Msk 0x1UL 168 #define PASS_SAR_CH_INTR_GRP_CANCELLED_Pos 1UL 169 #define PASS_SAR_CH_INTR_GRP_CANCELLED_Msk 0x2UL 170 #define PASS_SAR_CH_INTR_GRP_OVERFLOW_Pos 2UL 171 #define PASS_SAR_CH_INTR_GRP_OVERFLOW_Msk 0x4UL 172 #define PASS_SAR_CH_INTR_CH_RANGE_Pos 8UL 173 #define PASS_SAR_CH_INTR_CH_RANGE_Msk 0x100UL 174 #define PASS_SAR_CH_INTR_CH_PULSE_Pos 9UL 175 #define PASS_SAR_CH_INTR_CH_PULSE_Msk 0x200UL 176 #define PASS_SAR_CH_INTR_CH_OVERFLOW_Pos 10UL 177 #define PASS_SAR_CH_INTR_CH_OVERFLOW_Msk 0x400UL 178 /* PASS_SAR_CH.INTR_SET */ 179 #define PASS_SAR_CH_INTR_SET_GRP_DONE_SET_Pos 0UL 180 #define PASS_SAR_CH_INTR_SET_GRP_DONE_SET_Msk 0x1UL 181 #define PASS_SAR_CH_INTR_SET_GRP_CANCELLED_SET_Pos 1UL 182 #define PASS_SAR_CH_INTR_SET_GRP_CANCELLED_SET_Msk 0x2UL 183 #define PASS_SAR_CH_INTR_SET_GRP_OVERFLOW_SET_Pos 2UL 184 #define PASS_SAR_CH_INTR_SET_GRP_OVERFLOW_SET_Msk 0x4UL 185 #define PASS_SAR_CH_INTR_SET_CH_RANGE_SET_Pos 8UL 186 #define PASS_SAR_CH_INTR_SET_CH_RANGE_SET_Msk 0x100UL 187 #define PASS_SAR_CH_INTR_SET_CH_PULSE_SET_Pos 9UL 188 #define PASS_SAR_CH_INTR_SET_CH_PULSE_SET_Msk 0x200UL 189 #define PASS_SAR_CH_INTR_SET_CH_OVERFLOW_SET_Pos 10UL 190 #define PASS_SAR_CH_INTR_SET_CH_OVERFLOW_SET_Msk 0x400UL 191 /* PASS_SAR_CH.INTR_MASK */ 192 #define PASS_SAR_CH_INTR_MASK_GRP_DONE_MASK_Pos 0UL 193 #define PASS_SAR_CH_INTR_MASK_GRP_DONE_MASK_Msk 0x1UL 194 #define PASS_SAR_CH_INTR_MASK_GRP_CANCELLED_MASK_Pos 1UL 195 #define PASS_SAR_CH_INTR_MASK_GRP_CANCELLED_MASK_Msk 0x2UL 196 #define PASS_SAR_CH_INTR_MASK_GRP_OVERFLOW_MASK_Pos 2UL 197 #define PASS_SAR_CH_INTR_MASK_GRP_OVERFLOW_MASK_Msk 0x4UL 198 #define PASS_SAR_CH_INTR_MASK_CH_RANGE_MASK_Pos 8UL 199 #define PASS_SAR_CH_INTR_MASK_CH_RANGE_MASK_Msk 0x100UL 200 #define PASS_SAR_CH_INTR_MASK_CH_PULSE_MASK_Pos 9UL 201 #define PASS_SAR_CH_INTR_MASK_CH_PULSE_MASK_Msk 0x200UL 202 #define PASS_SAR_CH_INTR_MASK_CH_OVERFLOW_MASK_Pos 10UL 203 #define PASS_SAR_CH_INTR_MASK_CH_OVERFLOW_MASK_Msk 0x400UL 204 /* PASS_SAR_CH.INTR_MASKED */ 205 #define PASS_SAR_CH_INTR_MASKED_GRP_DONE_MASKED_Pos 0UL 206 #define PASS_SAR_CH_INTR_MASKED_GRP_DONE_MASKED_Msk 0x1UL 207 #define PASS_SAR_CH_INTR_MASKED_GRP_CANCELLED_MASKED_Pos 1UL 208 #define PASS_SAR_CH_INTR_MASKED_GRP_CANCELLED_MASKED_Msk 0x2UL 209 #define PASS_SAR_CH_INTR_MASKED_GRP_OVERFLOW_MASKED_Pos 2UL 210 #define PASS_SAR_CH_INTR_MASKED_GRP_OVERFLOW_MASKED_Msk 0x4UL 211 #define PASS_SAR_CH_INTR_MASKED_CH_RANGE_MASKED_Pos 8UL 212 #define PASS_SAR_CH_INTR_MASKED_CH_RANGE_MASKED_Msk 0x100UL 213 #define PASS_SAR_CH_INTR_MASKED_CH_PULSE_MASKED_Pos 9UL 214 #define PASS_SAR_CH_INTR_MASKED_CH_PULSE_MASKED_Msk 0x200UL 215 #define PASS_SAR_CH_INTR_MASKED_CH_OVERFLOW_MASKED_Pos 10UL 216 #define PASS_SAR_CH_INTR_MASKED_CH_OVERFLOW_MASKED_Msk 0x400UL 217 /* PASS_SAR_CH.WORK */ 218 #define PASS_SAR_CH_WORK_WORK_Pos 0UL 219 #define PASS_SAR_CH_WORK_WORK_Msk 0xFFFFUL 220 #define PASS_SAR_CH_WORK_ABOVE_HI_MIR_Pos 28UL 221 #define PASS_SAR_CH_WORK_ABOVE_HI_MIR_Msk 0x10000000UL 222 #define PASS_SAR_CH_WORK_RANGE_MIR_Pos 29UL 223 #define PASS_SAR_CH_WORK_RANGE_MIR_Msk 0x20000000UL 224 #define PASS_SAR_CH_WORK_PULSE_MIR_Pos 30UL 225 #define PASS_SAR_CH_WORK_PULSE_MIR_Msk 0x40000000UL 226 #define PASS_SAR_CH_WORK_VALID_MIR_Pos 31UL 227 #define PASS_SAR_CH_WORK_VALID_MIR_Msk 0x80000000UL 228 /* PASS_SAR_CH.RESULT */ 229 #define PASS_SAR_CH_RESULT_RESULT_Pos 0UL 230 #define PASS_SAR_CH_RESULT_RESULT_Msk 0xFFFFUL 231 #define PASS_SAR_CH_RESULT_ABOVE_HI_MIR_Pos 28UL 232 #define PASS_SAR_CH_RESULT_ABOVE_HI_MIR_Msk 0x10000000UL 233 #define PASS_SAR_CH_RESULT_RANGE_INTR_MIR_Pos 29UL 234 #define PASS_SAR_CH_RESULT_RANGE_INTR_MIR_Msk 0x20000000UL 235 #define PASS_SAR_CH_RESULT_PULSE_INTR_MIR_Pos 30UL 236 #define PASS_SAR_CH_RESULT_PULSE_INTR_MIR_Msk 0x40000000UL 237 #define PASS_SAR_CH_RESULT_VALID_MIR_Pos 31UL 238 #define PASS_SAR_CH_RESULT_VALID_MIR_Msk 0x80000000UL 239 /* PASS_SAR_CH.GRP_STAT */ 240 #define PASS_SAR_CH_GRP_STAT_GRP_COMPLETE_Pos 0UL 241 #define PASS_SAR_CH_GRP_STAT_GRP_COMPLETE_Msk 0x1UL 242 #define PASS_SAR_CH_GRP_STAT_GRP_CANCELLED_Pos 1UL 243 #define PASS_SAR_CH_GRP_STAT_GRP_CANCELLED_Msk 0x2UL 244 #define PASS_SAR_CH_GRP_STAT_GRP_OVERFLOW_Pos 2UL 245 #define PASS_SAR_CH_GRP_STAT_GRP_OVERFLOW_Msk 0x4UL 246 #define PASS_SAR_CH_GRP_STAT_CH_RANGE_COMPLETE_Pos 8UL 247 #define PASS_SAR_CH_GRP_STAT_CH_RANGE_COMPLETE_Msk 0x100UL 248 #define PASS_SAR_CH_GRP_STAT_CH_PULSE_COMPLETE_Pos 9UL 249 #define PASS_SAR_CH_GRP_STAT_CH_PULSE_COMPLETE_Msk 0x200UL 250 #define PASS_SAR_CH_GRP_STAT_CH_OVERFLOW_Pos 10UL 251 #define PASS_SAR_CH_GRP_STAT_CH_OVERFLOW_Msk 0x400UL 252 #define PASS_SAR_CH_GRP_STAT_GRP_BUSY_Pos 16UL 253 #define PASS_SAR_CH_GRP_STAT_GRP_BUSY_Msk 0x10000UL 254 /* PASS_SAR_CH.ENABLE */ 255 #define PASS_SAR_CH_ENABLE_CHAN_EN_Pos 0UL 256 #define PASS_SAR_CH_ENABLE_CHAN_EN_Msk 0x1UL 257 /* PASS_SAR_CH.TR_CMD */ 258 #define PASS_SAR_CH_TR_CMD_START_Pos 0UL 259 #define PASS_SAR_CH_TR_CMD_START_Msk 0x1UL 260 261 262 /* PASS_SAR.CTL */ 263 #define PASS_SAR_CTL_PWRUP_TIME_Pos 0UL 264 #define PASS_SAR_CTL_PWRUP_TIME_Msk 0xFFUL 265 #define PASS_SAR_CTL_IDLE_PWRDWN_Pos 8UL 266 #define PASS_SAR_CTL_IDLE_PWRDWN_Msk 0x100UL 267 #define PASS_SAR_CTL_MSB_STRETCH_Pos 9UL 268 #define PASS_SAR_CTL_MSB_STRETCH_Msk 0x200UL 269 #define PASS_SAR_CTL_HALF_LSB_Pos 10UL 270 #define PASS_SAR_CTL_HALF_LSB_Msk 0x400UL 271 #define PASS_SAR_CTL_SARMUX_EN_Pos 29UL 272 #define PASS_SAR_CTL_SARMUX_EN_Msk 0x20000000UL 273 #define PASS_SAR_CTL_ADC_EN_Pos 30UL 274 #define PASS_SAR_CTL_ADC_EN_Msk 0x40000000UL 275 #define PASS_SAR_CTL_ENABLED_Pos 31UL 276 #define PASS_SAR_CTL_ENABLED_Msk 0x80000000UL 277 /* PASS_SAR.DIAG_CTL */ 278 #define PASS_SAR_DIAG_CTL_DIAG_SEL_Pos 0UL 279 #define PASS_SAR_DIAG_CTL_DIAG_SEL_Msk 0xFUL 280 #define PASS_SAR_DIAG_CTL_DIAG_EN_Pos 31UL 281 #define PASS_SAR_DIAG_CTL_DIAG_EN_Msk 0x80000000UL 282 /* PASS_SAR.PRECOND_CTL */ 283 #define PASS_SAR_PRECOND_CTL_PRECOND_TIME_Pos 0UL 284 #define PASS_SAR_PRECOND_CTL_PRECOND_TIME_Msk 0xFUL 285 /* PASS_SAR.ANA_CAL */ 286 #define PASS_SAR_ANA_CAL_AOFFSET_Pos 0UL 287 #define PASS_SAR_ANA_CAL_AOFFSET_Msk 0xFFUL 288 #define PASS_SAR_ANA_CAL_AGAIN_Pos 16UL 289 #define PASS_SAR_ANA_CAL_AGAIN_Msk 0x1F0000UL 290 /* PASS_SAR.DIG_CAL */ 291 #define PASS_SAR_DIG_CAL_DOFFSET_Pos 0UL 292 #define PASS_SAR_DIG_CAL_DOFFSET_Msk 0xFFFUL 293 #define PASS_SAR_DIG_CAL_DGAIN_Pos 16UL 294 #define PASS_SAR_DIG_CAL_DGAIN_Msk 0x3F0000UL 295 /* PASS_SAR.ANA_CAL_ALT */ 296 #define PASS_SAR_ANA_CAL_ALT_AOFFSET_Pos 0UL 297 #define PASS_SAR_ANA_CAL_ALT_AOFFSET_Msk 0xFFUL 298 #define PASS_SAR_ANA_CAL_ALT_AGAIN_Pos 16UL 299 #define PASS_SAR_ANA_CAL_ALT_AGAIN_Msk 0x1F0000UL 300 /* PASS_SAR.DIG_CAL_ALT */ 301 #define PASS_SAR_DIG_CAL_ALT_DOFFSET_Pos 0UL 302 #define PASS_SAR_DIG_CAL_ALT_DOFFSET_Msk 0xFFFUL 303 #define PASS_SAR_DIG_CAL_ALT_DGAIN_Pos 16UL 304 #define PASS_SAR_DIG_CAL_ALT_DGAIN_Msk 0x3F0000UL 305 /* PASS_SAR.CAL_UPD_CMD */ 306 #define PASS_SAR_CAL_UPD_CMD_UPDATE_Pos 0UL 307 #define PASS_SAR_CAL_UPD_CMD_UPDATE_Msk 0x1UL 308 /* PASS_SAR.TR_PEND */ 309 #define PASS_SAR_TR_PEND_TR_PEND_Pos 0UL 310 #define PASS_SAR_TR_PEND_TR_PEND_Msk 0xFFFFFFFFUL 311 /* PASS_SAR.WORK_VALID */ 312 #define PASS_SAR_WORK_VALID_WORK_VALID_Pos 0UL 313 #define PASS_SAR_WORK_VALID_WORK_VALID_Msk 0xFFFFFFFFUL 314 /* PASS_SAR.WORK_RANGE */ 315 #define PASS_SAR_WORK_RANGE_RANGE_Pos 0UL 316 #define PASS_SAR_WORK_RANGE_RANGE_Msk 0xFFFFFFFFUL 317 /* PASS_SAR.WORK_RANGE_HI */ 318 #define PASS_SAR_WORK_RANGE_HI_ABOVE_HI_Pos 0UL 319 #define PASS_SAR_WORK_RANGE_HI_ABOVE_HI_Msk 0xFFFFFFFFUL 320 /* PASS_SAR.WORK_PULSE */ 321 #define PASS_SAR_WORK_PULSE_PULSE_Pos 0UL 322 #define PASS_SAR_WORK_PULSE_PULSE_Msk 0xFFFFFFFFUL 323 /* PASS_SAR.RESULT_VALID */ 324 #define PASS_SAR_RESULT_VALID_RESULT_VALID_Pos 0UL 325 #define PASS_SAR_RESULT_VALID_RESULT_VALID_Msk 0xFFFFFFFFUL 326 /* PASS_SAR.RESULT_RANGE_HI */ 327 #define PASS_SAR_RESULT_RANGE_HI_ABOVE_HI_Pos 0UL 328 #define PASS_SAR_RESULT_RANGE_HI_ABOVE_HI_Msk 0xFFFFFFFFUL 329 /* PASS_SAR.STATUS */ 330 #define PASS_SAR_STATUS_CUR_CHAN_Pos 0UL 331 #define PASS_SAR_STATUS_CUR_CHAN_Msk 0x1FUL 332 #define PASS_SAR_STATUS_CUR_PRIO_Pos 8UL 333 #define PASS_SAR_STATUS_CUR_PRIO_Msk 0x700UL 334 #define PASS_SAR_STATUS_CUR_PREEMPT_TYPE_Pos 12UL 335 #define PASS_SAR_STATUS_CUR_PREEMPT_TYPE_Msk 0x3000UL 336 #define PASS_SAR_STATUS_DBG_FREEZE_Pos 29UL 337 #define PASS_SAR_STATUS_DBG_FREEZE_Msk 0x20000000UL 338 #define PASS_SAR_STATUS_PWRUP_BUSY_Pos 30UL 339 #define PASS_SAR_STATUS_PWRUP_BUSY_Msk 0x40000000UL 340 #define PASS_SAR_STATUS_BUSY_Pos 31UL 341 #define PASS_SAR_STATUS_BUSY_Msk 0x80000000UL 342 /* PASS_SAR.AVG_STAT */ 343 #define PASS_SAR_AVG_STAT_CUR_AVG_ACCU_Pos 0UL 344 #define PASS_SAR_AVG_STAT_CUR_AVG_ACCU_Msk 0xFFFFFUL 345 #define PASS_SAR_AVG_STAT_CUR_AVG_CNT_Pos 24UL 346 #define PASS_SAR_AVG_STAT_CUR_AVG_CNT_Msk 0xFF000000UL 347 348 349 /* PASS_EPASS_MMIO.PASS_CTL */ 350 #define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_EN_A_Pos 0UL 351 #define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_EN_A_Msk 0x1UL 352 #define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_LVL_A_Pos 1UL 353 #define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_LVL_A_Msk 0x2UL 354 #define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_EN_B_Pos 4UL 355 #define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_EN_B_Msk 0x10UL 356 #define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_LVL_B_Pos 5UL 357 #define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_LVL_B_Msk 0x20UL 358 #define PASS_EPASS_MMIO_PASS_CTL_REFBUF_MODE_Pos 21UL 359 #define PASS_EPASS_MMIO_PASS_CTL_REFBUF_MODE_Msk 0x600000UL 360 #define PASS_EPASS_MMIO_PASS_CTL_DBG_FREEZE_EN_Pos 28UL 361 #define PASS_EPASS_MMIO_PASS_CTL_DBG_FREEZE_EN_Msk 0xF0000000UL 362 /* PASS_EPASS_MMIO.SAR_TR_IN_SEL */ 363 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN0_SEL_Pos 0UL 364 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN0_SEL_Msk 0xFUL 365 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN1_SEL_Pos 4UL 366 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN1_SEL_Msk 0xF0UL 367 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN2_SEL_Pos 8UL 368 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN2_SEL_Msk 0xF00UL 369 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN3_SEL_Pos 12UL 370 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN3_SEL_Msk 0xF000UL 371 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN4_SEL_Pos 16UL 372 #define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN4_SEL_Msk 0xF0000UL 373 /* PASS_EPASS_MMIO.SAR_TR_OUT_SEL */ 374 #define PASS_EPASS_MMIO_SAR_TR_OUT_SEL_OUT0_SEL_Pos 0UL 375 #define PASS_EPASS_MMIO_SAR_TR_OUT_SEL_OUT0_SEL_Msk 0x3FUL 376 #define PASS_EPASS_MMIO_SAR_TR_OUT_SEL_OUT1_SEL_Pos 8UL 377 #define PASS_EPASS_MMIO_SAR_TR_OUT_SEL_OUT1_SEL_Msk 0x3F00UL 378 /* PASS_EPASS_MMIO.TEST_CTL */ 379 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_CUR_IN_Pos 0UL 380 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_CUR_IN_Msk 0x1UL 381 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_VB_OUT_Pos 2UL 382 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_VB_OUT_Msk 0x4UL 383 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_VE_OUT_Pos 3UL 384 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_VE_OUT_Msk 0x8UL 385 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_DIODE_EN_Pos 4UL 386 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_DIODE_EN_Msk 0x10UL 387 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_DIODE_PNP_EN_Pos 5UL 388 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_DIODE_PNP_EN_Msk 0x20UL 389 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_VI_SEL_Pos 6UL 390 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_VI_SEL_Msk 0x40UL 391 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_CUR_SEL_Pos 8UL 392 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_CUR_SEL_Msk 0x300UL 393 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_SPARE_Pos 12UL 394 #define PASS_EPASS_MMIO_TEST_CTL_TS_CAL_SPARE_Msk 0x1000UL 395 396 397 #endif /* _CYIP_EPASS_H_ */ 398 399 400 /* [] END OF FILE */ 401
