1 /***************************************************************************//** 2 * \file cyip_dmac_v2.h 3 * 4 * \brief 5 * DMAC IP definitions 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CYIP_DMAC_V2_H_ 29 #define _CYIP_DMAC_V2_H_ 30 31 #include "cyip_headers.h" 32 33 /******************************************************************************* 34 * DMAC 35 *******************************************************************************/ 36 37 #define DMAC_CH_V2_SECTION_SIZE 0x00000100UL 38 #define DMAC_V2_SECTION_SIZE 0x00010000UL 39 40 /** 41 * \brief DMA controller channel (DMAC_CH) 42 */ 43 typedef struct { 44 __IOM uint32_t CTL; /*!< 0x00000000 Channel control */ 45 __IM uint32_t RESERVED[3]; 46 __IM uint32_t IDX; /*!< 0x00000010 Channel current indices */ 47 __IM uint32_t SRC; /*!< 0x00000014 Channel current source address */ 48 __IM uint32_t DST; /*!< 0x00000018 Channel current destination address */ 49 __IM uint32_t RESERVED1; 50 __IOM uint32_t CURR; /*!< 0x00000020 Channel current descriptor pointer */ 51 __IM uint32_t RESERVED2; 52 __IOM uint32_t TR_CMD; /*!< 0x00000028 Channle software trigger */ 53 __IM uint32_t RESERVED3[5]; 54 __IM uint32_t DESCR_STATUS; /*!< 0x00000040 Channel descriptor status */ 55 __IM uint32_t RESERVED4[7]; 56 __IM uint32_t DESCR_CTL; /*!< 0x00000060 Channel descriptor control */ 57 __IM uint32_t DESCR_SRC; /*!< 0x00000064 Channel descriptor source */ 58 __IM uint32_t DESCR_DST; /*!< 0x00000068 Channel descriptor destination */ 59 __IM uint32_t DESCR_X_SIZE; /*!< 0x0000006C Channel descriptor X size */ 60 __IM uint32_t DESCR_X_INCR; /*!< 0x00000070 Channel descriptor X increment */ 61 __IM uint32_t DESCR_Y_SIZE; /*!< 0x00000074 Channel descriptor Y size */ 62 __IM uint32_t DESCR_Y_INCR; /*!< 0x00000078 Channel descriptor Y increment */ 63 __IM uint32_t DESCR_NEXT; /*!< 0x0000007C Channel descriptor next pointer */ 64 __IOM uint32_t INTR; /*!< 0x00000080 Interrupt */ 65 __IOM uint32_t INTR_SET; /*!< 0x00000084 Interrupt set */ 66 __IOM uint32_t INTR_MASK; /*!< 0x00000088 Interrupt mask */ 67 __IM uint32_t INTR_MASKED; /*!< 0x0000008C Interrupt masked */ 68 __IM uint32_t RESERVED5[28]; 69 } DMAC_CH_V2_Type; /*!< Size = 256 (0x100) */ 70 71 /** 72 * \brief DMAC (DMAC) 73 */ 74 typedef struct { 75 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 76 __IM uint32_t RESERVED; 77 __IM uint32_t ACTIVE; /*!< 0x00000008 Active channels */ 78 __IM uint32_t RESERVED1[1021]; 79 DMAC_CH_V2_Type CH[8]; /*!< 0x00001000 DMA controller channel */ 80 } DMAC_V2_Type; /*!< Size = 6144 (0x1800) */ 81 82 83 /* DMAC_CH.CTL */ 84 #define DMAC_CH_V2_CTL_P_Pos 0UL 85 #define DMAC_CH_V2_CTL_P_Msk 0x1UL 86 #define DMAC_CH_V2_CTL_NS_Pos 1UL 87 #define DMAC_CH_V2_CTL_NS_Msk 0x2UL 88 #define DMAC_CH_V2_CTL_B_Pos 2UL 89 #define DMAC_CH_V2_CTL_B_Msk 0x4UL 90 #define DMAC_CH_V2_CTL_PC_Pos 4UL 91 #define DMAC_CH_V2_CTL_PC_Msk 0xF0UL 92 #define DMAC_CH_V2_CTL_PRIO_Pos 8UL 93 #define DMAC_CH_V2_CTL_PRIO_Msk 0x300UL 94 #define DMAC_CH_V2_CTL_ENABLED_Pos 31UL 95 #define DMAC_CH_V2_CTL_ENABLED_Msk 0x80000000UL 96 /* DMAC_CH.IDX */ 97 #define DMAC_CH_V2_IDX_X_Pos 0UL 98 #define DMAC_CH_V2_IDX_X_Msk 0xFFFFUL 99 #define DMAC_CH_V2_IDX_Y_Pos 16UL 100 #define DMAC_CH_V2_IDX_Y_Msk 0xFFFF0000UL 101 /* DMAC_CH.SRC */ 102 #define DMAC_CH_V2_SRC_ADDR_Pos 0UL 103 #define DMAC_CH_V2_SRC_ADDR_Msk 0xFFFFFFFFUL 104 /* DMAC_CH.DST */ 105 #define DMAC_CH_V2_DST_ADDR_Pos 0UL 106 #define DMAC_CH_V2_DST_ADDR_Msk 0xFFFFFFFFUL 107 /* DMAC_CH.CURR */ 108 #define DMAC_CH_V2_CURR_PTR_Pos 2UL 109 #define DMAC_CH_V2_CURR_PTR_Msk 0xFFFFFFFCUL 110 /* DMAC_CH.TR_CMD */ 111 #define DMAC_CH_V2_TR_CMD_ACTIVATE_Pos 0UL 112 #define DMAC_CH_V2_TR_CMD_ACTIVATE_Msk 0x1UL 113 /* DMAC_CH.DESCR_STATUS */ 114 #define DMAC_CH_V2_DESCR_STATUS_VALID_Pos 31UL 115 #define DMAC_CH_V2_DESCR_STATUS_VALID_Msk 0x80000000UL 116 /* DMAC_CH.DESCR_CTL */ 117 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL 118 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL 119 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Pos 2UL 120 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Msk 0xCUL 121 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Pos 4UL 122 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL 123 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Pos 6UL 124 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL 125 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Pos 8UL 126 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Msk 0x100UL 127 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Pos 16UL 128 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Msk 0x30000UL 129 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Pos 24UL 130 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL 131 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL 132 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL 133 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL 134 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL 135 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Pos 28UL 136 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Msk 0x70000000UL 137 /* DMAC_CH.DESCR_SRC */ 138 #define DMAC_CH_V2_DESCR_SRC_ADDR_Pos 0UL 139 #define DMAC_CH_V2_DESCR_SRC_ADDR_Msk 0xFFFFFFFFUL 140 /* DMAC_CH.DESCR_DST */ 141 #define DMAC_CH_V2_DESCR_DST_ADDR_Pos 0UL 142 #define DMAC_CH_V2_DESCR_DST_ADDR_Msk 0xFFFFFFFFUL 143 /* DMAC_CH.DESCR_X_SIZE */ 144 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Pos 0UL 145 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Msk 0xFFFFUL 146 /* DMAC_CH.DESCR_X_INCR */ 147 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Pos 0UL 148 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Msk 0xFFFFUL 149 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Pos 16UL 150 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Msk 0xFFFF0000UL 151 /* DMAC_CH.DESCR_Y_SIZE */ 152 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Pos 0UL 153 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Msk 0xFFFFUL 154 /* DMAC_CH.DESCR_Y_INCR */ 155 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Pos 0UL 156 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Msk 0xFFFFUL 157 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Pos 16UL 158 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Msk 0xFFFF0000UL 159 /* DMAC_CH.DESCR_NEXT */ 160 #define DMAC_CH_V2_DESCR_NEXT_PTR_Pos 2UL 161 #define DMAC_CH_V2_DESCR_NEXT_PTR_Msk 0xFFFFFFFCUL 162 /* DMAC_CH.INTR */ 163 #define DMAC_CH_V2_INTR_COMPLETION_Pos 0UL 164 #define DMAC_CH_V2_INTR_COMPLETION_Msk 0x1UL 165 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Pos 1UL 166 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk 0x2UL 167 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Pos 2UL 168 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk 0x4UL 169 #define DMAC_CH_V2_INTR_SRC_MISAL_Pos 3UL 170 #define DMAC_CH_V2_INTR_SRC_MISAL_Msk 0x8UL 171 #define DMAC_CH_V2_INTR_DST_MISAL_Pos 4UL 172 #define DMAC_CH_V2_INTR_DST_MISAL_Msk 0x10UL 173 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Pos 5UL 174 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk 0x20UL 175 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Pos 6UL 176 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk 0x40UL 177 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Pos 7UL 178 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk 0x80UL 179 /* DMAC_CH.INTR_SET */ 180 #define DMAC_CH_V2_INTR_SET_COMPLETION_Pos 0UL 181 #define DMAC_CH_V2_INTR_SET_COMPLETION_Msk 0x1UL 182 #define DMAC_CH_V2_INTR_SET_SRC_BUS_ERROR_Pos 1UL 183 #define DMAC_CH_V2_INTR_SET_SRC_BUS_ERROR_Msk 0x2UL 184 #define DMAC_CH_V2_INTR_SET_DST_BUS_ERROR_Pos 2UL 185 #define DMAC_CH_V2_INTR_SET_DST_BUS_ERROR_Msk 0x4UL 186 #define DMAC_CH_V2_INTR_SET_SRC_MISAL_Pos 3UL 187 #define DMAC_CH_V2_INTR_SET_SRC_MISAL_Msk 0x8UL 188 #define DMAC_CH_V2_INTR_SET_DST_MISAL_Pos 4UL 189 #define DMAC_CH_V2_INTR_SET_DST_MISAL_Msk 0x10UL 190 #define DMAC_CH_V2_INTR_SET_CURR_PTR_NULL_Pos 5UL 191 #define DMAC_CH_V2_INTR_SET_CURR_PTR_NULL_Msk 0x20UL 192 #define DMAC_CH_V2_INTR_SET_ACTIVE_CH_DISABLED_Pos 6UL 193 #define DMAC_CH_V2_INTR_SET_ACTIVE_CH_DISABLED_Msk 0x40UL 194 #define DMAC_CH_V2_INTR_SET_DESCR_BUS_ERROR_Pos 7UL 195 #define DMAC_CH_V2_INTR_SET_DESCR_BUS_ERROR_Msk 0x80UL 196 /* DMAC_CH.INTR_MASK */ 197 #define DMAC_CH_V2_INTR_MASK_COMPLETION_Pos 0UL 198 #define DMAC_CH_V2_INTR_MASK_COMPLETION_Msk 0x1UL 199 #define DMAC_CH_V2_INTR_MASK_SRC_BUS_ERROR_Pos 1UL 200 #define DMAC_CH_V2_INTR_MASK_SRC_BUS_ERROR_Msk 0x2UL 201 #define DMAC_CH_V2_INTR_MASK_DST_BUS_ERROR_Pos 2UL 202 #define DMAC_CH_V2_INTR_MASK_DST_BUS_ERROR_Msk 0x4UL 203 #define DMAC_CH_V2_INTR_MASK_SRC_MISAL_Pos 3UL 204 #define DMAC_CH_V2_INTR_MASK_SRC_MISAL_Msk 0x8UL 205 #define DMAC_CH_V2_INTR_MASK_DST_MISAL_Pos 4UL 206 #define DMAC_CH_V2_INTR_MASK_DST_MISAL_Msk 0x10UL 207 #define DMAC_CH_V2_INTR_MASK_CURR_PTR_NULL_Pos 5UL 208 #define DMAC_CH_V2_INTR_MASK_CURR_PTR_NULL_Msk 0x20UL 209 #define DMAC_CH_V2_INTR_MASK_ACTIVE_CH_DISABLED_Pos 6UL 210 #define DMAC_CH_V2_INTR_MASK_ACTIVE_CH_DISABLED_Msk 0x40UL 211 #define DMAC_CH_V2_INTR_MASK_DESCR_BUS_ERROR_Pos 7UL 212 #define DMAC_CH_V2_INTR_MASK_DESCR_BUS_ERROR_Msk 0x80UL 213 /* DMAC_CH.INTR_MASKED */ 214 #define DMAC_CH_V2_INTR_MASKED_COMPLETION_Pos 0UL 215 #define DMAC_CH_V2_INTR_MASKED_COMPLETION_Msk 0x1UL 216 #define DMAC_CH_V2_INTR_MASKED_SRC_BUS_ERROR_Pos 1UL 217 #define DMAC_CH_V2_INTR_MASKED_SRC_BUS_ERROR_Msk 0x2UL 218 #define DMAC_CH_V2_INTR_MASKED_DST_BUS_ERROR_Pos 2UL 219 #define DMAC_CH_V2_INTR_MASKED_DST_BUS_ERROR_Msk 0x4UL 220 #define DMAC_CH_V2_INTR_MASKED_SRC_MISAL_Pos 3UL 221 #define DMAC_CH_V2_INTR_MASKED_SRC_MISAL_Msk 0x8UL 222 #define DMAC_CH_V2_INTR_MASKED_DST_MISAL_Pos 4UL 223 #define DMAC_CH_V2_INTR_MASKED_DST_MISAL_Msk 0x10UL 224 #define DMAC_CH_V2_INTR_MASKED_CURR_PTR_NULL_Pos 5UL 225 #define DMAC_CH_V2_INTR_MASKED_CURR_PTR_NULL_Msk 0x20UL 226 #define DMAC_CH_V2_INTR_MASKED_ACTIVE_CH_DISABLED_Pos 6UL 227 #define DMAC_CH_V2_INTR_MASKED_ACTIVE_CH_DISABLED_Msk 0x40UL 228 #define DMAC_CH_V2_INTR_MASKED_DESCR_BUS_ERROR_Pos 7UL 229 #define DMAC_CH_V2_INTR_MASKED_DESCR_BUS_ERROR_Msk 0x80UL 230 231 232 /* DMAC.CTL */ 233 #define DMAC_V2_CTL_ENABLED_Pos 31UL 234 #define DMAC_V2_CTL_ENABLED_Msk 0x80000000UL 235 /* DMAC.ACTIVE */ 236 #define DMAC_V2_ACTIVE_ACTIVE_Pos 0UL 237 #define DMAC_V2_ACTIVE_ACTIVE_Msk 0xFFUL 238 239 240 #endif /* _CYIP_DMAC_V2_H_ */ 241 242 243 /* [] END OF FILE */ 244
