1 /***************************************************************************//** 2 * \file cyip_cpuss_sl_ctl.h 3 * 4 * \brief 5 * CPUSS_SL_CTL IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CPUSS_SL_CTL_H_ 28 #define _CYIP_CPUSS_SL_CTL_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CPUSS_SL_CTL 34 *******************************************************************************/ 35 36 #define CPUSS_SL_CTL_SECTION_SIZE 0x00000010UL 37 38 /** 39 * \brief SYSCPUSS Internal slave control registers (CPUSS_SL_CTL) 40 */ 41 typedef struct { 42 __IOM uint32_t SL_CTL; /*!< 0x00000000 Slave control (Clock enables) */ 43 __IOM uint32_t SL_CTL2; /*!< 0x00000004 Slave control2 (Reset enables) */ 44 } CPUSS_SL_CTL_Type; /*!< Size = 8 (0x8) */ 45 46 47 /* CPUSS_SL_CTL.SL_CTL */ 48 #define CPUSS_SL_CTL_SL_CTL_PROMC_ENABLED_Pos 0UL 49 #define CPUSS_SL_CTL_SL_CTL_PROMC_ENABLED_Msk 0x1UL 50 #define CPUSS_SL_CTL_SL_CTL_FLASHC_ENABLED_Pos 1UL 51 #define CPUSS_SL_CTL_SL_CTL_FLASHC_ENABLED_Msk 0x2UL 52 #define CPUSS_SL_CTL_SL_CTL_RAMC0_ENABLED_Pos 3UL 53 #define CPUSS_SL_CTL_SL_CTL_RAMC0_ENABLED_Msk 0x8UL 54 #define CPUSS_SL_CTL_SL_CTL_RAMC1_ENABLED_Pos 4UL 55 #define CPUSS_SL_CTL_SL_CTL_RAMC1_ENABLED_Msk 0x10UL 56 #define CPUSS_SL_CTL_SL_CTL_RAMC2_ENABLED_Pos 5UL 57 #define CPUSS_SL_CTL_SL_CTL_RAMC2_ENABLED_Msk 0x20UL 58 #define CPUSS_SL_CTL_SL_CTL_DW0_ENABLED_Pos 6UL 59 #define CPUSS_SL_CTL_SL_CTL_DW0_ENABLED_Msk 0x40UL 60 #define CPUSS_SL_CTL_SL_CTL_DW1_ENABLED_Pos 7UL 61 #define CPUSS_SL_CTL_SL_CTL_DW1_ENABLED_Msk 0x80UL 62 #define CPUSS_SL_CTL_SL_CTL_DMAC0_ENABLED_Pos 8UL 63 #define CPUSS_SL_CTL_SL_CTL_DMAC0_ENABLED_Msk 0x100UL 64 #define CPUSS_SL_CTL_SL_CTL_DMAC1_ENABLED_Pos 9UL 65 #define CPUSS_SL_CTL_SL_CTL_DMAC1_ENABLED_Msk 0x200UL 66 #define CPUSS_SL_CTL_SL_CTL_IPC_ENABLED_Pos 10UL 67 #define CPUSS_SL_CTL_SL_CTL_IPC_ENABLED_Msk 0x400UL 68 /* CPUSS_SL_CTL.SL_CTL2 */ 69 #define CPUSS_SL_CTL_SL_CTL2_PROMC_RST_Pos 0UL 70 #define CPUSS_SL_CTL_SL_CTL2_PROMC_RST_Msk 0x1UL 71 #define CPUSS_SL_CTL_SL_CTL2_FLASHC_RST_Pos 1UL 72 #define CPUSS_SL_CTL_SL_CTL2_FLASHC_RST_Msk 0x2UL 73 #define CPUSS_SL_CTL_SL_CTL2_RAMC0_RST_Pos 3UL 74 #define CPUSS_SL_CTL_SL_CTL2_RAMC0_RST_Msk 0x8UL 75 #define CPUSS_SL_CTL_SL_CTL2_RAMC1_RST_Pos 4UL 76 #define CPUSS_SL_CTL_SL_CTL2_RAMC1_RST_Msk 0x10UL 77 #define CPUSS_SL_CTL_SL_CTL2_RAMC2_RST_Pos 5UL 78 #define CPUSS_SL_CTL_SL_CTL2_RAMC2_RST_Msk 0x20UL 79 #define CPUSS_SL_CTL_SL_CTL2_DW0_RST_Pos 6UL 80 #define CPUSS_SL_CTL_SL_CTL2_DW0_RST_Msk 0x40UL 81 #define CPUSS_SL_CTL_SL_CTL2_DW1_RST_Pos 7UL 82 #define CPUSS_SL_CTL_SL_CTL2_DW1_RST_Msk 0x80UL 83 #define CPUSS_SL_CTL_SL_CTL2_DMAC0_RST_Pos 8UL 84 #define CPUSS_SL_CTL_SL_CTL2_DMAC0_RST_Msk 0x100UL 85 #define CPUSS_SL_CTL_SL_CTL2_DMAC1_RST_Pos 9UL 86 #define CPUSS_SL_CTL_SL_CTL2_DMAC1_RST_Msk 0x200UL 87 #define CPUSS_SL_CTL_SL_CTL2_IPC_RST_Pos 10UL 88 #define CPUSS_SL_CTL_SL_CTL2_IPC_RST_Msk 0x400UL 89 90 91 #endif /* _CYIP_CPUSS_SL_CTL_H_ */ 92 93 94 /* [] END OF FILE */ 95
