1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <stdint.h>
15 #include <stddef.h>
16 #include <assert.h>
17 #include "riscv/interrupt.h"
18 #include "soc/interrupt_reg.h"
19 #include "riscv/csr.h"
20 #include "esp_attr.h"
21
22 #define RV_INT_COUNT 32
23
assert_valid_rv_int_num(int rv_int_num)24 static inline void assert_valid_rv_int_num(int rv_int_num)
25 {
26 assert(rv_int_num != 0 && rv_int_num < RV_INT_COUNT && "Invalid CPU interrupt number");
27 }
28
29 /*************************** Software interrupt dispatcher ***************************/
30
31
32 typedef struct {
33 intr_handler_t handler;
34 void *arg;
35 } intr_handler_item_t;
36
37 static intr_handler_item_t s_intr_handlers[32];
38
intr_handler_set(int int_no,intr_handler_t fn,void * arg)39 void intr_handler_set(int int_no, intr_handler_t fn, void *arg)
40 {
41 assert_valid_rv_int_num(int_no);
42
43 s_intr_handlers[int_no] = (intr_handler_item_t) {
44 .handler = fn,
45 .arg = arg
46 };
47 }
48
intr_handler_get(int rv_int_num)49 intr_handler_t intr_handler_get(int rv_int_num)
50 {
51 return s_intr_handlers[rv_int_num].handler;
52 }
53
intr_handler_get_arg(int rv_int_num)54 void *intr_handler_get_arg(int rv_int_num)
55 {
56 return s_intr_handlers[rv_int_num].arg;
57 }
58
59 /* called from vectors.S */
_global_interrupt_handler(intptr_t sp,int mcause)60 void _global_interrupt_handler(intptr_t sp, int mcause)
61 {
62 intr_handler_item_t it = s_intr_handlers[mcause];
63 if (it.handler) {
64 (*it.handler)(it.arg);
65 }
66 }
67
68 /*************************** RISC-V interrupt enable/disable ***************************/
69
intr_matrix_route(int intr_src,int intr_num)70 void intr_matrix_route(int intr_src, int intr_num)
71 {
72 assert(intr_num != 0);
73
74 REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_src, intr_num);
75 }
76
riscv_global_interrupts_enable(void)77 void riscv_global_interrupts_enable(void)
78 {
79 RV_SET_CSR(mstatus, MSTATUS_MIE);
80 }
81
riscv_global_interrupts_disable(void)82 void riscv_global_interrupts_disable(void)
83 {
84 RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
85 }
86
esprv_intc_get_interrupt_unmask(void)87 uint32_t esprv_intc_get_interrupt_unmask(void)
88 {
89 return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
90 }
91
92 /*************************** Exception names. Used in .gdbinit file. ***************************/
93
94 const char *riscv_excp_names[16] __attribute__((used)) = {
95 "misaligned_fetch",
96 "fault_fetch",
97 "illegal_instruction",
98 "breakpoint",
99 "misaligned_load",
100 "fault_load",
101 "misaligned_store",
102 "fault_store",
103 "user_ecall",
104 "supervisor_ecall",
105 "hypervisor_ecall",
106 "machine_ecall",
107 "exec_page_fault",
108 "load_page_fault",
109 "reserved",
110 "store_page_fault"
111 };
112
