1/*
2 * Copyright (c) 2023 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8#include <dt-bindings/interrupt-controller/intel-ioapic.h>
9#include <dt-bindings/i2c/i2c.h>
10#include <mem.h>
11
12/ {
13	power-states {
14		d0i0: d0i0 {
15			compatible = "zephyr,power-state";
16			power-state-name = "runtime-idle";
17			min-residency-us = <500>;
18			substate-id = <1>;
19		};
20
21		d0i2: d0i2 {
22			compatible = "zephyr,power-state";
23			power-state-name = "suspend-to-ram";
24			min-residency-us = <10000>;
25			substate-id = <3>;
26		};
27
28		d0i3: d0i3 {
29			compatible = "zephyr,power-state";
30			power-state-name = "suspend-to-disk";
31			min-residency-us = <3000000>;
32			substate-id = <4>;
33		};
34	};
35
36	cpus {
37		#address-cells = <1>;
38		#size-cells = <0>;
39
40		cpu0: cpu0@0 {
41			device_type = "cpu";
42			compatible = "intel,ish", "intel,x86";
43			reg = <0>;
44			cpu-power-states = <&d0i0 &d0i2 &d0i3>;
45		};
46	};
47
48	intc: ioapic@fec00000  {
49		compatible = "intel,ioapic";
50		#address-cells = <1>;
51		#interrupt-cells = <3>;
52		reg = <0xfec00000 0x1000>;
53		interrupt-controller;
54	};
55
56	intc_loapic: loapic@fee00000  {
57		compatible = "intel,loapic";
58		reg = <0xfee00000 0x1000>;
59		interrupt-controller;
60		#interrupt-cells = <3>;
61		#address-cells = <1>;
62	};
63
64	sram: memory@ff200000 {
65		device_type = "memory";
66		compatible = "mmio-sram";
67		reg = <0xff200000 DT_SIZE_K(640)>;
68	};
69
70	aon: memory@ff800000 {
71		device_type = "memory";
72		compatible = "zephyr,memory-region", "mmio-sram";
73		reg = <0xff800000 DT_SIZE_K(8)>;
74		zephyr,memory-region = "AON";
75	};
76
77	soc {
78		#address-cells = <1>;
79		#size-cells = <1>;
80		compatible = "simple-bus";
81		ranges;
82
83		hpet: hpet@4700000{
84			compatible = "intel,hpet";
85			reg = <0x04700000 0x400>;
86			interrupt-parent = <&intc>;
87			interrupts = <14 IRQ_TYPE_FIXED_LEVEL_HIGH 2>;
88			status = "okay";
89		};
90
91		ipmhost: ipm@4100000 {
92			compatible = "intel,sedi-ipm";
93			reg = <0x4100000 0x1000>;
94			peripheral-id = <0>;
95			interrupt-parent = <&intc>;
96			interrupts = <0 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
97
98			status = "okay";
99		};
100
101		uart0: uart@8100000 {
102			compatible = "intel,sedi-uart";
103			reg = <0x08100000 0x1000>;
104			interrupt-parent = <&intc>;
105			interrupts = <23 IRQ_TYPE_LOWEST_EDGE_RISING 6>;
106			peripheral-id = <0>;
107			current-speed = <115200>;
108			status = "okay";
109		};
110
111		i2c0: i2c@0 {
112			compatible = "intel,sedi-i2c";
113			#address-cells = <1>;
114			#size-cells = <0>;
115			reg = <0x0 0x1000>;
116			peripheral-id = <0>;
117			interrupt-parent = <&intc>;
118			interrupts = <15 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
119			clock-frequency = <I2C_BITRATE_FAST>;
120			status = "okay";
121		};
122
123		i2c1: i2c@2000 {
124			compatible = "intel,sedi-i2c";
125			#address-cells = <1>;
126			#size-cells = <0>;
127			reg = <0x00002000 0x1000>;
128			peripheral-id = <1>;
129			interrupt-parent = <&intc>;
130			interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
131			clock-frequency = <I2C_BITRATE_FAST>;
132			status = "okay";
133		};
134
135		i2c2: i2c@4000 {
136			compatible = "intel,sedi-i2c";
137			#address-cells = <1>;
138			#size-cells = <0>;
139			reg = <0x00004000 0x1000>;
140			peripheral-id = <2>;
141			interrupt-parent = <&intc>;
142			interrupts = <17 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
143			clock-frequency = <I2C_BITRATE_FAST>;
144			status = "disabled";
145		};
146
147		gpio0: gpio@100000 {
148			compatible = "intel,sedi-gpio";
149			gpio-controller;
150			#gpio-cells = <2>;
151			peripheral-id = <0>;
152			reg = <0x00100000 0x1000>;
153			interrupt-parent = <&intc>;
154			ngpios = <32>;
155			interrupts = <13 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
156
157			status = "okay";
158		};
159
160		spi0: spi@8000000 {
161			compatible = "intel,sedi-spi";
162			#address-cells = <1>;
163			#size-cells = <0>;
164			reg = <0x8000000 0x1000>;
165			peripheral-id = <0>;
166			interrupt-parent = <&intc>;
167			interrupts = <19 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
168
169			status = "okay";
170		};
171
172		spi1: spi@8002000 {
173			compatible = "intel,sedi-spi";
174			#address-cells = <1>;
175			#size-cells = <0>;
176			reg = <0x8002000 0x1000>;
177			peripheral-id = <1>;
178			interrupt-parent = <&intc>;
179			interrupts = <20 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
180
181			status = "disabled";
182		};
183
184		dma0: dma@10100000 {
185			compatible = "intel,sedi-dma";
186			#dma-cells = <2>;
187			dma-channels = <8>;
188			peripheral-id = <0>;
189			reg = <0x10100000 0x1000>;
190			interrupts = <11 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
191			interrupt-parent = <&intc>;
192			dma-buf-size-alignment = <4>;
193			dma-copy-alignment = <4>;
194			status = "okay";
195		};
196	};
197};
198