1/*
2 * Copyright (c) 2017 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu: cpu@0 {
16			device_type = "cpu";
17			d-cache-line-size = <64>;
18			reg = <0>;
19		};
20
21	};
22
23	intc: ioapic@fec00000  {
24		compatible = "intel,ioapic";
25		#address-cells = <1>;
26		#interrupt-cells = <3>;
27		reg = <0xfec00000 0x1000>;
28		interrupt-controller;
29	};
30
31	intc_loapic: loapic@fee00000  {
32		compatible = "intel,loapic";
33		reg = <0xfee00000 0x1000>;
34		interrupt-controller;
35		#interrupt-cells = <3>;
36		#address-cells = <1>;
37	};
38
39	dram0: memory@DT_DRAM_BASE {
40		device_type = "memory";
41		reg = <DT_ADDR(DT_DRAM_BASE) DT_DRAM_SIZE>;
42	};
43
44	soc {
45		#address-cells = <1>;
46		#size-cells = <1>;
47		compatible = "simple-bus";
48		ranges;
49
50		uart0: uart@3f8 {
51			compatible = "ns16550";
52			reg = <0x000003f8 0x100>;
53			io-mapped;
54			clock-frequency = <1843200>;
55			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
56			interrupt-parent = <&intc>;
57			reg-shift = <0>;
58			status = "disabled";
59		};
60
61		uart1: uart@2f8 {
62			compatible = "ns16550";
63			reg = <0x000002f8 0x100>;
64			io-mapped;
65			clock-frequency = <1843200>;
66			interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
67			interrupt-parent = <&intc>;
68			reg-shift = <0>;
69			status = "disabled";
70		};
71
72		hpet: hpet@fed00000 {
73			compatible = "intel,hpet";
74			reg = <0xfed00000 0x400>;
75			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
76			interrupt-parent = <&intc>;
77
78			status = "disabled";
79		};
80
81		rtc: counter: rtc@70 {
82			compatible = "motorola,mc146818";
83			reg = <0x70 0x0D 0x71 0x0D>;
84			interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
85			interrupt-parent = <&intc>;
86			alarms-count = <1>;
87
88			status = "okay";
89		};
90
91	};
92};
93