1 /*
2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
3 * Contributors: 2018 Antmicro <www.antmicro.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT sifive_plic_1_0_0
9
10 /**
11 * @brief Platform Level Interrupt Controller (PLIC) driver
12 * for RISC-V processors
13 */
14
15 #include <zephyr/kernel.h>
16 #include <zephyr/arch/cpu.h>
17 #include <zephyr/init.h>
18 #include <soc.h>
19
20 #include <zephyr/sw_isr_table.h>
21 #include <zephyr/drivers/interrupt_controller/riscv_plic.h>
22 #include <zephyr/irq.h>
23
24 #define PLIC_MAX_PRIO DT_INST_PROP(0, riscv_max_priority)
25 #define PLIC_PRIO DT_INST_REG_ADDR_BY_NAME(0, prio)
26 #define PLIC_IRQ_EN DT_INST_REG_ADDR_BY_NAME(0, irq_en)
27 #define PLIC_REG DT_INST_REG_ADDR_BY_NAME(0, reg)
28
29 #define PLIC_IRQS (CONFIG_NUM_IRQS - CONFIG_2ND_LVL_ISR_TBL_OFFSET)
30 #define PLIC_EN_SIZE ((PLIC_IRQS >> 5) + 1)
31
32 struct plic_regs_t {
33 uint32_t threshold_prio;
34 uint32_t claim_complete;
35 };
36
37 static int save_irq;
38
39 /**
40 * @brief Enable a riscv PLIC-specific interrupt line
41 *
42 * This routine enables a RISCV PLIC-specific interrupt line.
43 * riscv_plic_irq_enable is called by SOC_FAMILY_RISCV_PRIVILEGED
44 * arch_irq_enable function to enable external interrupts for
45 * IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
46 *
47 * @param irq IRQ number to enable
48 */
riscv_plic_irq_enable(uint32_t irq)49 void riscv_plic_irq_enable(uint32_t irq)
50 {
51 uint32_t key;
52 volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
53
54 key = irq_lock();
55 en += (irq >> 5);
56 *en |= (1 << (irq & 31));
57 irq_unlock(key);
58 }
59
60 /**
61 * @brief Disable a riscv PLIC-specific interrupt line
62 *
63 * This routine disables a RISCV PLIC-specific interrupt line.
64 * riscv_plic_irq_disable is called by SOC_FAMILY_RISCV_PRIVILEGED
65 * arch_irq_disable function to disable external interrupts, for
66 * IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
67 *
68 * @param irq IRQ number to disable
69 */
riscv_plic_irq_disable(uint32_t irq)70 void riscv_plic_irq_disable(uint32_t irq)
71 {
72 uint32_t key;
73 volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
74
75 key = irq_lock();
76 en += (irq >> 5);
77 *en &= ~(1 << (irq & 31));
78 irq_unlock(key);
79 }
80
81 /**
82 * @brief Check if a riscv PLIC-specific interrupt line is enabled
83 *
84 * This routine checks if a RISCV PLIC-specific interrupt line is enabled.
85 * @param irq IRQ number to check
86 *
87 * @return 1 or 0
88 */
riscv_plic_irq_is_enabled(uint32_t irq)89 int riscv_plic_irq_is_enabled(uint32_t irq)
90 {
91 volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
92
93 en += (irq >> 5);
94 return !!(*en & (1 << (irq & 31)));
95 }
96
97 /**
98 * @brief Set priority of a riscv PLIC-specific interrupt line
99 *
100 * This routine set the priority of a RISCV PLIC-specific interrupt line.
101 * riscv_plic_irq_set_prio is called by riscv arch_irq_priority_set to set
102 * the priority of an interrupt whenever CONFIG_RISCV_HAS_PLIC variable is set.
103 *
104 * @param irq IRQ number for which to set priority
105 * @param priority Priority of IRQ to set to
106 */
riscv_plic_set_priority(uint32_t irq,uint32_t priority)107 void riscv_plic_set_priority(uint32_t irq, uint32_t priority)
108 {
109 volatile uint32_t *prio = (volatile uint32_t *)PLIC_PRIO;
110
111 if (priority > PLIC_MAX_PRIO)
112 priority = PLIC_MAX_PRIO;
113
114 prio += irq;
115 *prio = priority;
116 }
117
118 /**
119 * @brief Get riscv PLIC-specific interrupt line causing an interrupt
120 *
121 * This routine returns the RISCV PLIC-specific interrupt line causing an
122 * interrupt.
123 *
124 * @return PLIC-specific interrupt line causing an interrupt.
125 */
riscv_plic_get_irq(void)126 int riscv_plic_get_irq(void)
127 {
128 return save_irq;
129 }
130
plic_irq_handler(const void * arg)131 static void plic_irq_handler(const void *arg)
132 {
133 volatile struct plic_regs_t *regs =
134 (volatile struct plic_regs_t *) PLIC_REG;
135
136 uint32_t irq;
137 struct _isr_table_entry *ite;
138
139 /* Get the IRQ number generating the interrupt */
140 irq = regs->claim_complete;
141
142 /*
143 * Save IRQ in save_irq. To be used, if need be, by
144 * subsequent handlers registered in the _sw_isr_table table,
145 * as IRQ number held by the claim_complete register is
146 * cleared upon read.
147 */
148 save_irq = irq;
149
150 /*
151 * If the IRQ is out of range, call z_irq_spurious.
152 * A call to z_irq_spurious will not return.
153 */
154 if (irq == 0U || irq >= PLIC_IRQS)
155 z_irq_spurious(NULL);
156
157 irq += CONFIG_2ND_LVL_ISR_TBL_OFFSET;
158
159 /* Call the corresponding IRQ handler in _sw_isr_table */
160 ite = (struct _isr_table_entry *)&_sw_isr_table[irq];
161 ite->isr(ite->arg);
162
163 /*
164 * Write to claim_complete register to indicate to
165 * PLIC controller that the IRQ has been handled.
166 */
167 regs->claim_complete = save_irq;
168 }
169
170 /**
171 * @brief Initialize the Platform Level Interrupt Controller
172 *
173 * @retval 0 on success.
174 */
plic_init(void)175 static int plic_init(void)
176 {
177
178 volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
179 volatile uint32_t *prio = (volatile uint32_t *)PLIC_PRIO;
180 volatile struct plic_regs_t *regs =
181 (volatile struct plic_regs_t *)PLIC_REG;
182 int i;
183
184 /* Ensure that all interrupts are disabled initially */
185 for (i = 0; i < PLIC_EN_SIZE; i++) {
186 *en = 0U;
187 en++;
188 }
189
190 /* Set priority of each interrupt line to 0 initially */
191 for (i = 0; i < PLIC_IRQS; i++) {
192 *prio = 0U;
193 prio++;
194 }
195
196 /* Set threshold priority to 0 */
197 regs->threshold_prio = 0U;
198
199 /* Setup IRQ handler for PLIC driver */
200 IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
201 0,
202 plic_irq_handler,
203 NULL,
204 0);
205
206 /* Enable IRQ for PLIC driver */
207 irq_enable(RISCV_MACHINE_EXT_IRQ);
208
209 return 0;
210 }
211
212 SYS_INIT(plic_init, PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY);
213
