1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_UOTGHS_INSTANCE_ 31 #define _SAM3XA_UOTGHS_INSTANCE_ 32 33 /* ========== Register definition for UOTGHS peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_UOTGHS_DEVCTRL (0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */ 36 #define REG_UOTGHS_DEVISR (0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */ 37 #define REG_UOTGHS_DEVICR (0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */ 38 #define REG_UOTGHS_DEVIFR (0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */ 39 #define REG_UOTGHS_DEVIMR (0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */ 40 #define REG_UOTGHS_DEVIDR (0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */ 41 #define REG_UOTGHS_DEVIER (0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */ 42 #define REG_UOTGHS_DEVEPT (0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */ 43 #define REG_UOTGHS_DEVFNUM (0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */ 44 #define REG_UOTGHS_DEVEPTCFG (0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */ 45 #define REG_UOTGHS_DEVEPTISR (0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */ 46 #define REG_UOTGHS_DEVEPTICR (0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */ 47 #define REG_UOTGHS_DEVEPTIFR (0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */ 48 #define REG_UOTGHS_DEVEPTIMR (0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */ 49 #define REG_UOTGHS_DEVEPTIER (0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */ 50 #define REG_UOTGHS_DEVEPTIDR (0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */ 51 #define REG_UOTGHS_DEVDMANXTDSC1 (0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ 52 #define REG_UOTGHS_DEVDMAADDRESS1 (0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */ 53 #define REG_UOTGHS_DEVDMACONTROL1 (0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */ 54 #define REG_UOTGHS_DEVDMASTATUS1 (0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */ 55 #define REG_UOTGHS_DEVDMANXTDSC2 (0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ 56 #define REG_UOTGHS_DEVDMAADDRESS2 (0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */ 57 #define REG_UOTGHS_DEVDMACONTROL2 (0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */ 58 #define REG_UOTGHS_DEVDMASTATUS2 (0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */ 59 #define REG_UOTGHS_DEVDMANXTDSC3 (0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ 60 #define REG_UOTGHS_DEVDMAADDRESS3 (0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */ 61 #define REG_UOTGHS_DEVDMACONTROL3 (0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */ 62 #define REG_UOTGHS_DEVDMASTATUS3 (0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */ 63 #define REG_UOTGHS_DEVDMANXTDSC4 (0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ 64 #define REG_UOTGHS_DEVDMAADDRESS4 (0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */ 65 #define REG_UOTGHS_DEVDMACONTROL4 (0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */ 66 #define REG_UOTGHS_DEVDMASTATUS4 (0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */ 67 #define REG_UOTGHS_DEVDMANXTDSC5 (0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ 68 #define REG_UOTGHS_DEVDMAADDRESS5 (0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */ 69 #define REG_UOTGHS_DEVDMACONTROL5 (0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */ 70 #define REG_UOTGHS_DEVDMASTATUS5 (0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */ 71 #define REG_UOTGHS_DEVDMANXTDSC6 (0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ 72 #define REG_UOTGHS_DEVDMAADDRESS6 (0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */ 73 #define REG_UOTGHS_DEVDMACONTROL6 (0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */ 74 #define REG_UOTGHS_DEVDMASTATUS6 (0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */ 75 #define REG_UOTGHS_DEVDMANXTDSC7 (0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ 76 #define REG_UOTGHS_DEVDMAADDRESS7 (0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */ 77 #define REG_UOTGHS_DEVDMACONTROL7 (0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */ 78 #define REG_UOTGHS_DEVDMASTATUS7 (0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */ 79 #define REG_UOTGHS_HSTCTRL (0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */ 80 #define REG_UOTGHS_HSTISR (0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */ 81 #define REG_UOTGHS_HSTICR (0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */ 82 #define REG_UOTGHS_HSTIFR (0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */ 83 #define REG_UOTGHS_HSTIMR (0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */ 84 #define REG_UOTGHS_HSTIDR (0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */ 85 #define REG_UOTGHS_HSTIER (0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */ 86 #define REG_UOTGHS_HSTPIP (0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */ 87 #define REG_UOTGHS_HSTFNUM (0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */ 88 #define REG_UOTGHS_HSTADDR1 (0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */ 89 #define REG_UOTGHS_HSTADDR2 (0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */ 90 #define REG_UOTGHS_HSTADDR3 (0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */ 91 #define REG_UOTGHS_HSTPIPCFG (0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */ 92 #define REG_UOTGHS_HSTPIPISR (0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */ 93 #define REG_UOTGHS_HSTPIPICR (0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */ 94 #define REG_UOTGHS_HSTPIPIFR (0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */ 95 #define REG_UOTGHS_HSTPIPIMR (0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */ 96 #define REG_UOTGHS_HSTPIPIER (0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */ 97 #define REG_UOTGHS_HSTPIPIDR (0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */ 98 #define REG_UOTGHS_HSTPIPINRQ (0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */ 99 #define REG_UOTGHS_HSTPIPERR (0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */ 100 #define REG_UOTGHS_HSTDMANXTDSC1 (0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ 101 #define REG_UOTGHS_HSTDMAADDRESS1 (0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */ 102 #define REG_UOTGHS_HSTDMACONTROL1 (0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */ 103 #define REG_UOTGHS_HSTDMASTATUS1 (0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */ 104 #define REG_UOTGHS_HSTDMANXTDSC2 (0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ 105 #define REG_UOTGHS_HSTDMAADDRESS2 (0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */ 106 #define REG_UOTGHS_HSTDMACONTROL2 (0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */ 107 #define REG_UOTGHS_HSTDMASTATUS2 (0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */ 108 #define REG_UOTGHS_HSTDMANXTDSC3 (0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ 109 #define REG_UOTGHS_HSTDMAADDRESS3 (0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */ 110 #define REG_UOTGHS_HSTDMACONTROL3 (0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */ 111 #define REG_UOTGHS_HSTDMASTATUS3 (0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */ 112 #define REG_UOTGHS_HSTDMANXTDSC4 (0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ 113 #define REG_UOTGHS_HSTDMAADDRESS4 (0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */ 114 #define REG_UOTGHS_HSTDMACONTROL4 (0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */ 115 #define REG_UOTGHS_HSTDMASTATUS4 (0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */ 116 #define REG_UOTGHS_HSTDMANXTDSC5 (0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ 117 #define REG_UOTGHS_HSTDMAADDRESS5 (0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */ 118 #define REG_UOTGHS_HSTDMACONTROL5 (0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */ 119 #define REG_UOTGHS_HSTDMASTATUS5 (0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */ 120 #define REG_UOTGHS_HSTDMANXTDSC6 (0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ 121 #define REG_UOTGHS_HSTDMAADDRESS6 (0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */ 122 #define REG_UOTGHS_HSTDMACONTROL6 (0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */ 123 #define REG_UOTGHS_HSTDMASTATUS6 (0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */ 124 #define REG_UOTGHS_HSTDMANXTDSC7 (0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ 125 #define REG_UOTGHS_HSTDMAADDRESS7 (0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */ 126 #define REG_UOTGHS_HSTDMACONTROL7 (0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */ 127 #define REG_UOTGHS_HSTDMASTATUS7 (0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */ 128 #define REG_UOTGHS_CTRL (0x400AC800U) /**< \brief (UOTGHS) General Control Register */ 129 #define REG_UOTGHS_SR (0x400AC804U) /**< \brief (UOTGHS) General Status Register */ 130 #define REG_UOTGHS_SCR (0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */ 131 #define REG_UOTGHS_SFR (0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */ 132 #define REG_UOTGHS_FSM (0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */ 133 #else 134 #define REG_UOTGHS_DEVCTRL (*(__IO uint32_t*)0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */ 135 #define REG_UOTGHS_DEVISR (*(__I uint32_t*)0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */ 136 #define REG_UOTGHS_DEVICR (*(__O uint32_t*)0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */ 137 #define REG_UOTGHS_DEVIFR (*(__O uint32_t*)0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */ 138 #define REG_UOTGHS_DEVIMR (*(__I uint32_t*)0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */ 139 #define REG_UOTGHS_DEVIDR (*(__O uint32_t*)0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */ 140 #define REG_UOTGHS_DEVIER (*(__O uint32_t*)0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */ 141 #define REG_UOTGHS_DEVEPT (*(__IO uint32_t*)0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */ 142 #define REG_UOTGHS_DEVFNUM (*(__I uint32_t*)0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */ 143 #define REG_UOTGHS_DEVEPTCFG (*(__IO uint32_t*)0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */ 144 #define REG_UOTGHS_DEVEPTISR (*(__I uint32_t*)0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */ 145 #define REG_UOTGHS_DEVEPTICR (*(__O uint32_t*)0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */ 146 #define REG_UOTGHS_DEVEPTIFR (*(__O uint32_t*)0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */ 147 #define REG_UOTGHS_DEVEPTIMR (*(__I uint32_t*)0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */ 148 #define REG_UOTGHS_DEVEPTIER (*(__O uint32_t*)0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */ 149 #define REG_UOTGHS_DEVEPTIDR (*(__O uint32_t*)0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */ 150 #define REG_UOTGHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ 151 #define REG_UOTGHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */ 152 #define REG_UOTGHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */ 153 #define REG_UOTGHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */ 154 #define REG_UOTGHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ 155 #define REG_UOTGHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */ 156 #define REG_UOTGHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */ 157 #define REG_UOTGHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */ 158 #define REG_UOTGHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ 159 #define REG_UOTGHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */ 160 #define REG_UOTGHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */ 161 #define REG_UOTGHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */ 162 #define REG_UOTGHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ 163 #define REG_UOTGHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */ 164 #define REG_UOTGHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */ 165 #define REG_UOTGHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */ 166 #define REG_UOTGHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ 167 #define REG_UOTGHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */ 168 #define REG_UOTGHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */ 169 #define REG_UOTGHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */ 170 #define REG_UOTGHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ 171 #define REG_UOTGHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */ 172 #define REG_UOTGHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */ 173 #define REG_UOTGHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */ 174 #define REG_UOTGHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ 175 #define REG_UOTGHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */ 176 #define REG_UOTGHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */ 177 #define REG_UOTGHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */ 178 #define REG_UOTGHS_HSTCTRL (*(__IO uint32_t*)0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */ 179 #define REG_UOTGHS_HSTISR (*(__I uint32_t*)0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */ 180 #define REG_UOTGHS_HSTICR (*(__O uint32_t*)0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */ 181 #define REG_UOTGHS_HSTIFR (*(__O uint32_t*)0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */ 182 #define REG_UOTGHS_HSTIMR (*(__I uint32_t*)0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */ 183 #define REG_UOTGHS_HSTIDR (*(__O uint32_t*)0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */ 184 #define REG_UOTGHS_HSTIER (*(__O uint32_t*)0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */ 185 #define REG_UOTGHS_HSTPIP (*(__IO uint32_t*)0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */ 186 #define REG_UOTGHS_HSTFNUM (*(__IO uint32_t*)0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */ 187 #define REG_UOTGHS_HSTADDR1 (*(__IO uint32_t*)0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */ 188 #define REG_UOTGHS_HSTADDR2 (*(__IO uint32_t*)0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */ 189 #define REG_UOTGHS_HSTADDR3 (*(__IO uint32_t*)0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */ 190 #define REG_UOTGHS_HSTPIPCFG (*(__IO uint32_t*)0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */ 191 #define REG_UOTGHS_HSTPIPISR (*(__I uint32_t*)0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */ 192 #define REG_UOTGHS_HSTPIPICR (*(__O uint32_t*)0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */ 193 #define REG_UOTGHS_HSTPIPIFR (*(__O uint32_t*)0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */ 194 #define REG_UOTGHS_HSTPIPIMR (*(__I uint32_t*)0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */ 195 #define REG_UOTGHS_HSTPIPIER (*(__O uint32_t*)0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */ 196 #define REG_UOTGHS_HSTPIPIDR (*(__O uint32_t*)0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */ 197 #define REG_UOTGHS_HSTPIPINRQ (*(__IO uint32_t*)0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */ 198 #define REG_UOTGHS_HSTPIPERR (*(__IO uint32_t*)0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */ 199 #define REG_UOTGHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ 200 #define REG_UOTGHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */ 201 #define REG_UOTGHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */ 202 #define REG_UOTGHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */ 203 #define REG_UOTGHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ 204 #define REG_UOTGHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */ 205 #define REG_UOTGHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */ 206 #define REG_UOTGHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */ 207 #define REG_UOTGHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ 208 #define REG_UOTGHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */ 209 #define REG_UOTGHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */ 210 #define REG_UOTGHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */ 211 #define REG_UOTGHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ 212 #define REG_UOTGHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */ 213 #define REG_UOTGHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */ 214 #define REG_UOTGHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */ 215 #define REG_UOTGHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ 216 #define REG_UOTGHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */ 217 #define REG_UOTGHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */ 218 #define REG_UOTGHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */ 219 #define REG_UOTGHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ 220 #define REG_UOTGHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */ 221 #define REG_UOTGHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */ 222 #define REG_UOTGHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */ 223 #define REG_UOTGHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ 224 #define REG_UOTGHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */ 225 #define REG_UOTGHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */ 226 #define REG_UOTGHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */ 227 #define REG_UOTGHS_CTRL (*(__IO uint32_t*)0x400AC800U) /**< \brief (UOTGHS) General Control Register */ 228 #define REG_UOTGHS_SR (*(__I uint32_t*)0x400AC804U) /**< \brief (UOTGHS) General Status Register */ 229 #define REG_UOTGHS_SCR (*(__O uint32_t*)0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */ 230 #define REG_UOTGHS_SFR (*(__O uint32_t*)0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */ 231 #define REG_UOTGHS_FSM (*(__I uint32_t*)0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */ 232 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 233 234 #endif /* _SAM3XA_UOTGHS_INSTANCE_ */ 235
