1 /** 2 * \file 3 * 4 * \brief Instance description for TCC1 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_TCC1_INSTANCE_ 30 #define _SAML21_TCC1_INSTANCE_ 31 32 /* ========== Register definition for TCC1 peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_TCC1_CTRLA (0x42001800) /**< \brief (TCC1) Control A */ 35 #define REG_TCC1_CTRLBCLR (0x42001804) /**< \brief (TCC1) Control B Clear */ 36 #define REG_TCC1_CTRLBSET (0x42001805) /**< \brief (TCC1) Control B Set */ 37 #define REG_TCC1_SYNCBUSY (0x42001808) /**< \brief (TCC1) Synchronization Busy */ 38 #define REG_TCC1_FCTRLA (0x4200180C) /**< \brief (TCC1) Recoverable Fault A Configuration */ 39 #define REG_TCC1_FCTRLB (0x42001810) /**< \brief (TCC1) Recoverable Fault B Configuration */ 40 #define REG_TCC1_DRVCTRL (0x42001818) /**< \brief (TCC1) Driver Control */ 41 #define REG_TCC1_DBGCTRL (0x4200181E) /**< \brief (TCC1) Debug Control */ 42 #define REG_TCC1_EVCTRL (0x42001820) /**< \brief (TCC1) Event Control */ 43 #define REG_TCC1_INTENCLR (0x42001824) /**< \brief (TCC1) Interrupt Enable Clear */ 44 #define REG_TCC1_INTENSET (0x42001828) /**< \brief (TCC1) Interrupt Enable Set */ 45 #define REG_TCC1_INTFLAG (0x4200182C) /**< \brief (TCC1) Interrupt Flag Status and Clear */ 46 #define REG_TCC1_STATUS (0x42001830) /**< \brief (TCC1) Status */ 47 #define REG_TCC1_COUNT (0x42001834) /**< \brief (TCC1) Count */ 48 #define REG_TCC1_PATT (0x42001838) /**< \brief (TCC1) Pattern */ 49 #define REG_TCC1_WAVE (0x4200183C) /**< \brief (TCC1) Waveform Control */ 50 #define REG_TCC1_PER (0x42001840) /**< \brief (TCC1) Period */ 51 #define REG_TCC1_CC0 (0x42001844) /**< \brief (TCC1) Compare and Capture 0 */ 52 #define REG_TCC1_CC1 (0x42001848) /**< \brief (TCC1) Compare and Capture 1 */ 53 #define REG_TCC1_PATTBUF (0x42001864) /**< \brief (TCC1) Pattern Buffer */ 54 #define REG_TCC1_PERBUF (0x4200186C) /**< \brief (TCC1) Period Buffer */ 55 #define REG_TCC1_CCBUF0 (0x42001870) /**< \brief (TCC1) Compare and Capture Buffer 0 */ 56 #define REG_TCC1_CCBUF1 (0x42001874) /**< \brief (TCC1) Compare and Capture Buffer 1 */ 57 #else 58 #define REG_TCC1_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (TCC1) Control A */ 59 #define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42001804UL) /**< \brief (TCC1) Control B Clear */ 60 #define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42001805UL) /**< \brief (TCC1) Control B Set */ 61 #define REG_TCC1_SYNCBUSY (*(RoReg *)0x42001808UL) /**< \brief (TCC1) Synchronization Busy */ 62 #define REG_TCC1_FCTRLA (*(RwReg *)0x4200180CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */ 63 #define REG_TCC1_FCTRLB (*(RwReg *)0x42001810UL) /**< \brief (TCC1) Recoverable Fault B Configuration */ 64 #define REG_TCC1_DRVCTRL (*(RwReg *)0x42001818UL) /**< \brief (TCC1) Driver Control */ 65 #define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200181EUL) /**< \brief (TCC1) Debug Control */ 66 #define REG_TCC1_EVCTRL (*(RwReg *)0x42001820UL) /**< \brief (TCC1) Event Control */ 67 #define REG_TCC1_INTENCLR (*(RwReg *)0x42001824UL) /**< \brief (TCC1) Interrupt Enable Clear */ 68 #define REG_TCC1_INTENSET (*(RwReg *)0x42001828UL) /**< \brief (TCC1) Interrupt Enable Set */ 69 #define REG_TCC1_INTFLAG (*(RwReg *)0x4200182CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */ 70 #define REG_TCC1_STATUS (*(RwReg *)0x42001830UL) /**< \brief (TCC1) Status */ 71 #define REG_TCC1_COUNT (*(RwReg *)0x42001834UL) /**< \brief (TCC1) Count */ 72 #define REG_TCC1_PATT (*(RwReg16*)0x42001838UL) /**< \brief (TCC1) Pattern */ 73 #define REG_TCC1_WAVE (*(RwReg *)0x4200183CUL) /**< \brief (TCC1) Waveform Control */ 74 #define REG_TCC1_PER (*(RwReg *)0x42001840UL) /**< \brief (TCC1) Period */ 75 #define REG_TCC1_CC0 (*(RwReg *)0x42001844UL) /**< \brief (TCC1) Compare and Capture 0 */ 76 #define REG_TCC1_CC1 (*(RwReg *)0x42001848UL) /**< \brief (TCC1) Compare and Capture 1 */ 77 #define REG_TCC1_PATTBUF (*(RwReg16*)0x42001864UL) /**< \brief (TCC1) Pattern Buffer */ 78 #define REG_TCC1_PERBUF (*(RwReg *)0x4200186CUL) /**< \brief (TCC1) Period Buffer */ 79 #define REG_TCC1_CCBUF0 (*(RwReg *)0x42001870UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */ 80 #define REG_TCC1_CCBUF1 (*(RwReg *)0x42001874UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */ 81 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 83 /* ========== Instance parameters for TCC1 peripheral ========== */ 84 #define TCC1_CC_NUM 2 // Number of Compare/Capture units 85 #define TCC1_DITHERING 1 // Dithering feature implemented 86 #define TCC1_DMAC_ID_MC_0 17 87 #define TCC1_DMAC_ID_MC_1 18 88 #define TCC1_DMAC_ID_MC_LSB 17 89 #define TCC1_DMAC_ID_MC_MSB 18 90 #define TCC1_DMAC_ID_MC_SIZE 2 91 #define TCC1_DMAC_ID_OVF 16 // DMA overflow/underflow/retrigger trigger 92 #define TCC1_DTI 0 // Dead-Time-Insertion feature implemented 93 #define TCC1_EXT 24 // Coding of implemented extended features 94 #define TCC1_GCLK_ID 25 // Index of Generic Clock 95 #define TCC1_OTMX 0 // Output Matrix feature implemented 96 #define TCC1_OW_NUM 4 // Number of Output Waveforms 97 #define TCC1_PG 1 // Pattern Generation feature implemented 98 #define TCC1_SIZE 24 99 #define TCC1_SWAP 0 // DTI outputs swap feature implemented 100 #define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave 101 102 #endif /* _SAML21_TCC1_INSTANCE_ */ 103
