1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_TC3_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_TC3_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for TC3 peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_TC3_CTRLA (0x4101C000) /**< \brief (TC3) Control A */ 13 #define REG_TC3_CTRLBCLR (0x4101C004) /**< \brief (TC3) Control B Clear */ 14 #define REG_TC3_CTRLBSET (0x4101C005) /**< \brief (TC3) Control B Set */ 15 #define REG_TC3_EVCTRL (0x4101C006) /**< \brief (TC3) Event Control */ 16 #define REG_TC3_INTENCLR (0x4101C008) /**< \brief (TC3) Interrupt Enable Clear */ 17 #define REG_TC3_INTENSET (0x4101C009) /**< \brief (TC3) Interrupt Enable Set */ 18 #define REG_TC3_INTFLAG (0x4101C00A) /**< \brief (TC3) Interrupt Flag Status and Clear */ 19 #define REG_TC3_STATUS (0x4101C00B) /**< \brief (TC3) Status */ 20 #define REG_TC3_WAVE (0x4101C00C) /**< \brief (TC3) Waveform Generation Control */ 21 #define REG_TC3_DRVCTRL (0x4101C00D) /**< \brief (TC3) Control C */ 22 #define REG_TC3_DBGCTRL (0x4101C00F) /**< \brief (TC3) Debug Control */ 23 #define REG_TC3_SYNCBUSY (0x4101C010) /**< \brief (TC3) Synchronization Status */ 24 #define REG_TC3_COUNT16_COUNT (0x4101C014) /**< \brief (TC3) COUNT16 Count */ 25 #define REG_TC3_COUNT16_CC0 (0x4101C01C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ 26 #define REG_TC3_COUNT16_CC1 (0x4101C01E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ 27 #define REG_TC3_COUNT16_CCBUF0 (0x4101C030) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ 28 #define REG_TC3_COUNT16_CCBUF1 (0x4101C032) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ 29 #define REG_TC3_COUNT32_COUNT (0x4101C014) /**< \brief (TC3) COUNT32 Count */ 30 #define REG_TC3_COUNT32_CC0 (0x4101C01C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ 31 #define REG_TC3_COUNT32_CC1 (0x4101C020) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ 32 #define REG_TC3_COUNT32_CCBUF0 (0x4101C030) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ 33 #define REG_TC3_COUNT32_CCBUF1 (0x4101C034) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ 34 #define REG_TC3_COUNT8_COUNT (0x4101C014) /**< \brief (TC3) COUNT8 Count */ 35 #define REG_TC3_COUNT8_PER (0x4101C01B) /**< \brief (TC3) COUNT8 Period */ 36 #define REG_TC3_COUNT8_CC0 (0x4101C01C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ 37 #define REG_TC3_COUNT8_CC1 (0x4101C01D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ 38 #define REG_TC3_COUNT8_PERBUF (0x4101C02F) /**< \brief (TC3) COUNT8 Period Buffer */ 39 #define REG_TC3_COUNT8_CCBUF0 (0x4101C030) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ 40 #define REG_TC3_COUNT8_CCBUF1 (0x4101C031) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ 41 #else 42 #define REG_TC3_CTRLA (*(RwReg *)0x4101C000UL) /**< \brief (TC3) Control A */ 43 #define REG_TC3_CTRLBCLR (*(RwReg8 *)0x4101C004UL) /**< \brief (TC3) Control B Clear */ 44 #define REG_TC3_CTRLBSET (*(RwReg8 *)0x4101C005UL) /**< \brief (TC3) Control B Set */ 45 #define REG_TC3_EVCTRL (*(RwReg16*)0x4101C006UL) /**< \brief (TC3) Event Control */ 46 #define REG_TC3_INTENCLR (*(RwReg8 *)0x4101C008UL) /**< \brief (TC3) Interrupt Enable Clear */ 47 #define REG_TC3_INTENSET (*(RwReg8 *)0x4101C009UL) /**< \brief (TC3) Interrupt Enable Set */ 48 #define REG_TC3_INTFLAG (*(RwReg8 *)0x4101C00AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */ 49 #define REG_TC3_STATUS (*(RwReg8 *)0x4101C00BUL) /**< \brief (TC3) Status */ 50 #define REG_TC3_WAVE (*(RwReg8 *)0x4101C00CUL) /**< \brief (TC3) Waveform Generation Control */ 51 #define REG_TC3_DRVCTRL (*(RwReg8 *)0x4101C00DUL) /**< \brief (TC3) Control C */ 52 #define REG_TC3_DBGCTRL (*(RwReg8 *)0x4101C00FUL) /**< \brief (TC3) Debug Control */ 53 #define REG_TC3_SYNCBUSY (*(RoReg *)0x4101C010UL) /**< \brief (TC3) Synchronization Status */ 54 #define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x4101C014UL) /**< \brief (TC3) COUNT16 Count */ 55 #define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x4101C01CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ 56 #define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x4101C01EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ 57 #define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x4101C030UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ 58 #define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x4101C032UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ 59 #define REG_TC3_COUNT32_COUNT (*(RwReg *)0x4101C014UL) /**< \brief (TC3) COUNT32 Count */ 60 #define REG_TC3_COUNT32_CC0 (*(RwReg *)0x4101C01CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ 61 #define REG_TC3_COUNT32_CC1 (*(RwReg *)0x4101C020UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ 62 #define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x4101C030UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ 63 #define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x4101C034UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ 64 #define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x4101C014UL) /**< \brief (TC3) COUNT8 Count */ 65 #define REG_TC3_COUNT8_PER (*(RwReg8 *)0x4101C01BUL) /**< \brief (TC3) COUNT8 Period */ 66 #define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x4101C01CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ 67 #define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x4101C01DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ 68 #define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x4101C02FUL) /**< \brief (TC3) COUNT8 Period Buffer */ 69 #define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x4101C030UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ 70 #define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x4101C031UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ 71 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 #endif /* _MICROCHIP_PIC32CXSG_TC3_INSTANCE_FIXUP_H_ */ 74
