1 /** 2 * \file 3 * 4 * \brief Instance description for SERCOM5 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_SERCOM5_INSTANCE_ 30 #define _SAML21_SERCOM5_INSTANCE_ 31 32 /* ========== Register definition for SERCOM5 peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_SERCOM5_I2CM_CTRLA (0x43000400) /**< \brief (SERCOM5) I2CM Control A */ 35 #define REG_SERCOM5_I2CM_CTRLB (0x43000404) /**< \brief (SERCOM5) I2CM Control B */ 36 #define REG_SERCOM5_I2CM_BAUD (0x4300040C) /**< \brief (SERCOM5) I2CM Baud Rate */ 37 #define REG_SERCOM5_I2CM_INTENCLR (0x43000414) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ 38 #define REG_SERCOM5_I2CM_INTENSET (0x43000416) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ 39 #define REG_SERCOM5_I2CM_INTFLAG (0x43000418) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ 40 #define REG_SERCOM5_I2CM_STATUS (0x4300041A) /**< \brief (SERCOM5) I2CM Status */ 41 #define REG_SERCOM5_I2CM_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) I2CM Synchronization Busy */ 42 #define REG_SERCOM5_I2CM_ADDR (0x43000424) /**< \brief (SERCOM5) I2CM Address */ 43 #define REG_SERCOM5_I2CM_DATA (0x43000428) /**< \brief (SERCOM5) I2CM Data */ 44 #define REG_SERCOM5_I2CM_DBGCTRL (0x43000430) /**< \brief (SERCOM5) I2CM Debug Control */ 45 #define REG_SERCOM5_I2CS_CTRLA (0x43000400) /**< \brief (SERCOM5) I2CS Control A */ 46 #define REG_SERCOM5_I2CS_CTRLB (0x43000404) /**< \brief (SERCOM5) I2CS Control B */ 47 #define REG_SERCOM5_I2CS_INTENCLR (0x43000414) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ 48 #define REG_SERCOM5_I2CS_INTENSET (0x43000416) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ 49 #define REG_SERCOM5_I2CS_INTFLAG (0x43000418) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ 50 #define REG_SERCOM5_I2CS_STATUS (0x4300041A) /**< \brief (SERCOM5) I2CS Status */ 51 #define REG_SERCOM5_I2CS_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) I2CS Synchronization Busy */ 52 #define REG_SERCOM5_I2CS_ADDR (0x43000424) /**< \brief (SERCOM5) I2CS Address */ 53 #define REG_SERCOM5_I2CS_DATA (0x43000428) /**< \brief (SERCOM5) I2CS Data */ 54 #define REG_SERCOM5_SPI_CTRLA (0x43000400) /**< \brief (SERCOM5) SPI Control A */ 55 #define REG_SERCOM5_SPI_CTRLB (0x43000404) /**< \brief (SERCOM5) SPI Control B */ 56 #define REG_SERCOM5_SPI_BAUD (0x4300040C) /**< \brief (SERCOM5) SPI Baud Rate */ 57 #define REG_SERCOM5_SPI_INTENCLR (0x43000414) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ 58 #define REG_SERCOM5_SPI_INTENSET (0x43000416) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ 59 #define REG_SERCOM5_SPI_INTFLAG (0x43000418) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ 60 #define REG_SERCOM5_SPI_STATUS (0x4300041A) /**< \brief (SERCOM5) SPI Status */ 61 #define REG_SERCOM5_SPI_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) SPI Synchronization Busy */ 62 #define REG_SERCOM5_SPI_ADDR (0x43000424) /**< \brief (SERCOM5) SPI Address */ 63 #define REG_SERCOM5_SPI_DATA (0x43000428) /**< \brief (SERCOM5) SPI Data */ 64 #define REG_SERCOM5_SPI_DBGCTRL (0x43000430) /**< \brief (SERCOM5) SPI Debug Control */ 65 #define REG_SERCOM5_USART_CTRLA (0x43000400) /**< \brief (SERCOM5) USART Control A */ 66 #define REG_SERCOM5_USART_CTRLB (0x43000404) /**< \brief (SERCOM5) USART Control B */ 67 #define REG_SERCOM5_USART_BAUD (0x4300040C) /**< \brief (SERCOM5) USART Baud Rate */ 68 #define REG_SERCOM5_USART_RXPL (0x4300040E) /**< \brief (SERCOM5) USART Receive Pulse Length */ 69 #define REG_SERCOM5_USART_INTENCLR (0x43000414) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ 70 #define REG_SERCOM5_USART_INTENSET (0x43000416) /**< \brief (SERCOM5) USART Interrupt Enable Set */ 71 #define REG_SERCOM5_USART_INTFLAG (0x43000418) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ 72 #define REG_SERCOM5_USART_STATUS (0x4300041A) /**< \brief (SERCOM5) USART Status */ 73 #define REG_SERCOM5_USART_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) USART Synchronization Busy */ 74 #define REG_SERCOM5_USART_DATA (0x43000428) /**< \brief (SERCOM5) USART Data */ 75 #define REG_SERCOM5_USART_DBGCTRL (0x43000430) /**< \brief (SERCOM5) USART Debug Control */ 76 #else 77 #define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) I2CM Control A */ 78 #define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) I2CM Control B */ 79 #define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4300040CUL) /**< \brief (SERCOM5) I2CM Baud Rate */ 80 #define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ 81 #define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ 82 #define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ 83 #define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) I2CM Status */ 84 #define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */ 85 #define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x43000424UL) /**< \brief (SERCOM5) I2CM Address */ 86 #define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x43000428UL) /**< \brief (SERCOM5) I2CM Data */ 87 #define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) I2CM Debug Control */ 88 #define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) I2CS Control A */ 89 #define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) I2CS Control B */ 90 #define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ 91 #define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ 92 #define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ 93 #define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) I2CS Status */ 94 #define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */ 95 #define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x43000424UL) /**< \brief (SERCOM5) I2CS Address */ 96 #define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x43000428UL) /**< \brief (SERCOM5) I2CS Data */ 97 #define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) SPI Control A */ 98 #define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) SPI Control B */ 99 #define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4300040CUL) /**< \brief (SERCOM5) SPI Baud Rate */ 100 #define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ 101 #define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ 102 #define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ 103 #define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) SPI Status */ 104 #define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */ 105 #define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x43000424UL) /**< \brief (SERCOM5) SPI Address */ 106 #define REG_SERCOM5_SPI_DATA (*(RwReg *)0x43000428UL) /**< \brief (SERCOM5) SPI Data */ 107 #define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) SPI Debug Control */ 108 #define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) USART Control A */ 109 #define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) USART Control B */ 110 #define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4300040CUL) /**< \brief (SERCOM5) USART Baud Rate */ 111 #define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4300040EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */ 112 #define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ 113 #define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */ 114 #define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ 115 #define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) USART Status */ 116 #define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) USART Synchronization Busy */ 117 #define REG_SERCOM5_USART_DATA (*(RwReg16*)0x43000428UL) /**< \brief (SERCOM5) USART Data */ 118 #define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) USART Debug Control */ 119 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 120 121 /* ========== Instance parameters for SERCOM5 peripheral ========== */ 122 #define SERCOM5_DMAC_ID_RX // Index of DMA RX trigger 123 #define SERCOM5_DMAC_ID_TX // Index of DMA TX trigger 124 #define SERCOM5_GCLK_ID_CORE 24 125 #define SERCOM5_GCLK_ID_SLOW 23 126 #define SERCOM5_INT_MSB 3 127 #define SERCOM5_PMSB 3 128 129 #endif /* _SAML21_SERCOM5_INSTANCE_ */ 130
